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extmem: invert logic on "Cache enable" 

This seems to be inverted in hardware, at least according to what
actually works.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2023-08-05 19:27:37 +08:00
parent cc47e0576b
commit 79f515d63e
1 changed files with 7 additions and 6 deletions
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13
peripherals/ESP32S3_EXTMEM.cs
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@ -23,7 +23,8 @@ namespace Antmicro.Renode.Peripherals.Miscellaneous
var registersMap = new Dictionary<long, DoubleWordRegister>
{
{(long)Registers.DCACHE_CTRL, new DoubleWordRegister(this)
.WithFlag(0, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => dCacheEnabled, writeCallback: (_, val) => dCacheEnabled = val, name: "DCACHE_ENABLE") // The bit is used to activate the data cache. 0: disable, 1: enable
// NOTE: This appears to be inverted logic, i.e. `false` means `enable`
.WithFlag(0, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => dCacheEnabled, writeCallback: (_, val) => dCacheEnabled = !val, name: "DCACHE_ENABLE") // The bit is used to activate the data cache. 0: disable, 1: enable
.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "DCACHE_SIZE_MODE") // The bit is used to configure cache memory size.0: 32KB, 1: 64KB
.WithValueField(2, 2, FieldMode.Read | FieldMode.Write, name: "DCACHE_BLOCKSIZE_MODE") // The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes
},
@ -88,7 +89,8 @@ namespace Antmicro.Renode.Peripherals.Miscellaneous
},
// 0x60: ******* Description ***********
{(long)Registers.ICACHE_CTRL, new DoubleWordRegister(this)
.WithFlag(0, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => iCacheEnabled, writeCallback: (_, val) => iCacheEnabled = val, name: "ICACHE_ENABLE") // The bit is used to activate the data cache. 0: disable, 1: enable
// NOTE: This appears to be inverted logic, i.e. `false` means `enable`
.WithFlag(0, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => iCacheEnabled, writeCallback: (_, val) => iCacheEnabled = !val, name: "ICACHE_ENABLE") // The bit is used to activate the data cache. 0: disable, 1: enable
.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "ICACHE_WAY_MODE") // The bit is used to configure cache way mode.0: 4-way, 1: 8-way
.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "ICACHE_SIZE_MODE") // The bit is used to configure cache memory size.0: 16KB, 1: 32KB
.WithFlag(3, FieldMode.Read | FieldMode.Write, name: "ICACHE_BLOCKSIZE_MODE") // The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes
@ -115,7 +117,7 @@ namespace Antmicro.Renode.Peripherals.Miscellaneous
.WithValueField(7, 2, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_SIZE") // The bits are used to configure the numbers of the cache block for the issuing autoload operation.
.WithFlag(9, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_BUFFER_CLEAR") // The bit is used to clear autoload buffer in icache.
},
// ******* Description ***********
// 0x130: ******* Description ***********
{(long)Registers.CACHE_STATE, new DoubleWordRegister(this)
.WithValueField(0, 12, FieldMode.Read, valueProviderCallback: (_) => {if (iCacheEnabled) return 1; else return 0;}, name: "ICACHE_STATE") // The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state
.WithValueField(12, 12, FieldMode.Read, valueProviderCallback: (_) => {if (dCacheEnabled) return 1; else return 0;}, name: "DCACHE_STATE") // The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state
@ -168,9 +170,8 @@ namespace Antmicro.Renode.Peripherals.Miscellaneous
public long Size => 0x17C;
private readonly DoubleWordRegisterCollection registers;
private bool iCacheEnabled;
private bool dCacheEnabled;
private bool toggley;
public bool iCacheEnabled;
public bool dCacheEnabled;
private enum Registers : long
{