many hacks to get something booting
Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
parent
eb1ef4f6ab
commit
cc47e0576b
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@ -201,10 +201,10 @@ def mc_setup_hooks(cpu):
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log("skip_hal_map_region2", *args())
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cpu.PC = RegisterValue.Create(0x403cd936,32)
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@hook (0x403cd93c)
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def hook_skip_cache_setup(cpu, pc):
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log("skip_cache_setup", *args())
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cpu.PC = RegisterValue.Create(0x403cd97b,32)
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# @hook (0x403cd93c)
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# def hook_skip_cache_setup(cpu, pc):
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# log("skip_cache_setup", *args())
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# cpu.PC = RegisterValue.Create(0x403cd97b,32)
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@hook (0x403cd8eb)
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def hook_image_entry_addr(cpu, pc):
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@ -23,7 +23,7 @@ namespace Antmicro.Renode.Peripherals.Miscellaneous
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var registersMap = new Dictionary<long, DoubleWordRegister>
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{
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{(long)Registers.DCACHE_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "DCACHE_ENABLE") // The bit is used to activate the data cache. 0: disable, 1: enable
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.WithFlag(0, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => dCacheEnabled, writeCallback: (_, val) => dCacheEnabled = val, name: "DCACHE_ENABLE") // The bit is used to activate the data cache. 0: disable, 1: enable
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "DCACHE_SIZE_MODE") // The bit is used to configure cache memory size.0: 32KB, 1: 64KB
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.WithValueField(2, 2, FieldMode.Read | FieldMode.Write, name: "DCACHE_BLOCKSIZE_MODE") // The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes
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},
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@ -72,29 +72,6 @@ namespace Antmicro.Renode.Peripherals.Miscellaneous
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{(long)Registers.CACHE_WRAP_AROUND_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "CACHE_FLASH_WRAP_AROUND") // The bit is used to enable wrap around mode when read data from flash.
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "CACHE_SRAM_RD_WRAP_AROUND") // The bit is used to enable wrap around mode when read data from spiram.
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// .WithValueField(0, 2, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => 0, name: "SW_STALL_APPCPU_C0") // {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU
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// .WithValueField(2, 2, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => 0, name: "SW_STALL_PROCPU_C0") // {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU
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// .WithFlag(4, FieldMode.Read | FieldMode.Write, name: "SW_APPCPU_RST") // APP CPU SW reset
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// .WithFlag(5, FieldMode.Read | FieldMode.Write, name: "SW_PROCPU_RST") // PRO CPU SW reset
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// .WithFlag(6, FieldMode.Read | FieldMode.Write, name: "BB_I2C_FORCE_PD") // BB_I2C force power down
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// .WithFlag(7, FieldMode.Read | FieldMode.Write, name: "BB_I2C_FORCE_PU") // BB_I2C force power up
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// .WithFlag(8, FieldMode.Read | FieldMode.Write, name: "BBPLL_I2C_FORCE_PD") // BB_PLL _I2C force power down
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// .WithFlag(9, FieldMode.Read | FieldMode.Write, name: "BBPLL_I2C_FORCE_PU") // BB_PLL_I2C force power up
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// .WithFlag(10, FieldMode.Read | FieldMode.Write, name: "BBPLL_FORCE_PD") // BB_PLL force power down
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// .WithFlag(11, FieldMode.Read | FieldMode.Write, name: "BBPLL_FORCE_PU") // BB_PLL force power up
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// .WithFlag(12, FieldMode.Read | FieldMode.Write, name: "XTL_FORCE_PD") // crystall force power down
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// .WithFlag(13, FieldMode.Read | FieldMode.Write, name: "XTL_FORCE_PU") // crystall force power up
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// .WithValueField(14, 4, FieldMode.Read | FieldMode.Write, name: "XTL_EN_WAIT") // wait bias_sleep and current source wakeup
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// .WithFlag(23, FieldMode.Read | FieldMode.Write, name: "XTL_FORCE_ISO") // No public
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// .WithFlag(24, FieldMode.Read | FieldMode.Write, name: "PLL_FORCE_ISO") // No public
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// .WithFlag(25, FieldMode.Read | FieldMode.Write, name: "ANALOG_FORCE_ISO") // No public
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// .WithFlag(26, FieldMode.Read | FieldMode.Write, name: "XTL_FORCE_NOISO") // No public
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// .WithFlag(27, FieldMode.Read | FieldMode.Write, name: "PLL_FORCE_NOISO") // No public
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// .WithFlag(28, FieldMode.Read | FieldMode.Write, name: "ANALOG_FORCE_NOISO") // No public
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// .WithFlag(29, FieldMode.Read | FieldMode.Write, name: "DG_WRAP_FORCE_RST") // digital wrap force reset in deep sleep
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// .WithFlag(30, FieldMode.Read | FieldMode.Write, name: "DG_WRAP_FORCE_NORST") // digital core force no reset in deep sleep
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// .WithFlag(31, FieldMode.Write, name: "SW_SYS_RST") // SW system reset
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},
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{(long)Registers.CACHE_MMU_OWNER, new DoubleWordRegister(this)
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.WithValueField(7, 2, FieldMode.Read | FieldMode.Write, name: "CACHE_MMU_OWNER") // The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved.
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@ -109,6 +86,40 @@ namespace Antmicro.Renode.Peripherals.Miscellaneous
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "MODE") // The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss
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.WithFlag(2, FieldMode.Read, valueProviderCallback: (_) => true, name: "DONE") // The bit is used to indicate icache freeze success
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},
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// 0x60: ******* Description ***********
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{(long)Registers.ICACHE_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => iCacheEnabled, writeCallback: (_, val) => iCacheEnabled = val, name: "ICACHE_ENABLE") // The bit is used to activate the data cache. 0: disable, 1: enable
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "ICACHE_WAY_MODE") // The bit is used to configure cache way mode.0: 4-way, 1: 8-way
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.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "ICACHE_SIZE_MODE") // The bit is used to configure cache memory size.0: 16KB, 1: 32KB
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.WithFlag(3, FieldMode.Read | FieldMode.Write, name: "ICACHE_BLOCKSIZE_MODE") // The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes
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},
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// 0x88: ******* Description ***********
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{(long)Registers.ICACHE_SYNC_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "ICACHE_INVALIDATE_ENA") // The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.
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.WithFlag(1, FieldMode.Read, valueProviderCallback: (_) => true, name: "ICACHE_SYNC_DONE") // The bit is used to indicate invalidate operation is finished.
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},
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// 0x94: ******* Description ***********
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{(long)Registers.ICACHE_PRELOAD_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "ICACHE_PRELOAD_ENA") // The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.
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.WithFlag(1, FieldMode.Read, valueProviderCallback: (_) => true, name: "ICACHE_PRELOAD_DONE") // The bit is used to indicate preload operation is finished.
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.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "ICACHE_PRELOAD_ORDER") // The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.
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},
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// 0xa0: ******* Description ***********
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{(long)Registers.ICACHE_AUTOLOAD_CTRL, new DoubleWordRegister(this)
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.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_SCT0_ENA") // The bits are used to enable the first section for autoload operation.
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.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_SCT1_ENA") // The bits are used to enable the second section for autoload operation.
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.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_ENA") // The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.
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.WithFlag(3, FieldMode.Read, valueProviderCallback: (_) => true, name: "ICACHE_AUTOLOAD_DONE") // The bit is used to indicate autoload operation is finished.
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.WithFlag(4, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_ORDER") // The bits are used to configure the direction of autoload. 1: descending, 0: ascending.
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.WithValueField(5, 2, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_RQST") // The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.
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.WithValueField(7, 2, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_SIZE") // The bits are used to configure the numbers of the cache block for the issuing autoload operation.
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.WithFlag(9, FieldMode.Read | FieldMode.Write, name: "ICACHE_AUTOLOAD_BUFFER_CLEAR") // The bit is used to clear autoload buffer in icache.
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},
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// ******* Description ***********
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{(long)Registers.CACHE_STATE, new DoubleWordRegister(this)
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.WithValueField(0, 12, FieldMode.Read, valueProviderCallback: (_) => {if (iCacheEnabled) return 1; else return 0;}, name: "ICACHE_STATE") // The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state
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.WithValueField(12, 12, FieldMode.Read, valueProviderCallback: (_) => {if (dCacheEnabled) return 1; else return 0;}, name: "DCACHE_STATE") // The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state
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},
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};
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registers = new DoubleWordRegisterCollection(this, registersMap);
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@ -157,21 +168,107 @@ namespace Antmicro.Renode.Peripherals.Miscellaneous
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public long Size => 0x17C;
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private readonly DoubleWordRegisterCollection registers;
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private bool iCacheEnabled;
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private bool dCacheEnabled;
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private bool toggley;
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private enum Registers : long
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{
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DCACHE_CTRL = 0x00,
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DCACHE_CTRL1 = 0x04,
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DCACHE_CTRL = 0x0,
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DCACHE_CTRL1 = 0x4,
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DCACHE_TAG_POWER_CTRL = 0x8,
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DCACHE_PRELOCK_CTRL = 0xc,
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DCACHE_PRELOCK_SCT0_ADDR = 0x10,
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DCACHE_PRELOCK_SCT1_ADDR = 0x14,
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DCACHE_PRELOCK_SCT_SIZE = 0x18,
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DCACHE_LOCK_CTRL = 0x1c,
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DCACHE_LOCK_ADDR = 0x20,
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DCACHE_LOCK_SIZE = 0x24,
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DCACHE_SYNC_CTRL = 0x28,
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DCACHE_SYNC_ADDR = 0x2C,
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DCACHE_SYNC_ADDR = 0x2c,
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DCACHE_SYNC_SIZE = 0x30,
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DCACHE_OCCUPY_CTRL = 0x34,
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DCACHE_OCCUPY_ADDR = 0x38,
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DCACHE_OCCUPY_SIZE = 0x3c,
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DCACHE_PRELOAD_CTRL = 0x40,
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DCACHE_AUTOLOAD_CTRL = 0x4C,
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CACHE_ILG_INT_CLR = 0xE0,
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DCACHE_PRELOAD_ADDR = 0x44,
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DCACHE_PRELOAD_SIZE = 0x48,
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DCACHE_AUTOLOAD_CTRL = 0x4c,
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DCACHE_AUTOLOAD_SCT0_ADDR = 0x50,
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DCACHE_AUTOLOAD_SCT0_SIZE = 0x54,
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DCACHE_AUTOLOAD_SCT1_ADDR = 0x58,
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DCACHE_AUTOLOAD_SCT1_SIZE = 0x5c,
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ICACHE_CTRL = 0x60,
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ICACHE_CTRL1 = 0x64,
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ICACHE_TAG_POWER_CTRL = 0x68,
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ICACHE_PRELOCK_CTRL = 0x6c,
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ICACHE_PRELOCK_SCT0_ADDR = 0x70,
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ICACHE_PRELOCK_SCT1_ADDR = 0x74,
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ICACHE_PRELOCK_SCT_SIZE = 0x78,
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ICACHE_LOCK_CTRL = 0x7c,
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ICACHE_LOCK_ADDR = 0x80,
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ICACHE_LOCK_SIZE = 0x84,
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ICACHE_SYNC_CTRL = 0x88,
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ICACHE_SYNC_ADDR = 0x8c,
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ICACHE_SYNC_SIZE = 0x90,
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ICACHE_PRELOAD_CTRL = 0x94,
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ICACHE_PRELOAD_ADDR = 0x98,
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ICACHE_PRELOAD_SIZE = 0x9c,
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ICACHE_AUTOLOAD_CTRL = 0xa0,
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ICACHE_AUTOLOAD_SCT0_ADDR = 0xa4,
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ICACHE_AUTOLOAD_SCT0_SIZE = 0xa8,
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ICACHE_AUTOLOAD_SCT1_ADDR = 0xac,
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ICACHE_AUTOLOAD_SCT1_SIZE = 0xb0,
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IBUS_TO_FLASH_START_VADDR = 0xb4,
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IBUS_TO_FLASH_END_VADDR = 0xb8,
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DBUS_TO_FLASH_START_VADDR = 0xbc,
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DBUS_TO_FLASH_END_VADDR = 0xc0,
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CACHE_ACS_CNT_CLR = 0xc4,
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IBUS_ACS_MISS_CNT = 0xc8,
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IBUS_ACS_CNT = 0xcc,
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DBUS_ACS_FLASH_MISS_CNT = 0xd0,
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DBUS_ACS_SPIRAM_MISS_CNT = 0xd4,
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DBUS_ACS_CNT = 0xd8,
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CACHE_ILG_INT_ENA = 0xdc,
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CACHE_ILG_INT_CLR = 0xe0,
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CACHE_ILG_INT_ST = 0xe4,
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CORE0_ACS_CACHE_INT_ENA = 0xe8,
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CORE0_ACS_CACHE_INT_CLR = 0xec,
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CORE0_ACS_CACHE_INT_ST = 0xf0,
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CORE1_ACS_CACHE_INT_ENA = 0xf4,
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CORE1_ACS_CACHE_INT_CLR = 0xf8,
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CORE1_ACS_CACHE_INT_ST = 0xfc,
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CORE0_DBUS_REJECT_ST = 0x100,
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CORE0_DBUS_REJECT_VADDR = 0x104,
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CORE0_IBUS_REJECT_ST = 0x108,
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CORE0_IBUS_REJECT_VADDR = 0x10c,
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CORE1_DBUS_REJECT_ST = 0x110,
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CORE1_DBUS_REJECT_VADDR = 0x114,
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CORE1_IBUS_REJECT_ST = 0x118,
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CORE1_IBUS_REJECT_VADDR = 0x11c,
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CACHE_MMU_FAULT_CONTENT = 0x120,
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CACHE_MMU_FAULT_VADDR = 0x124,
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CACHE_WRAP_AROUND_CTRL = 0x128,
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CACHE_MMU_POWER_CTRL = 0x12c,
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CACHE_STATE = 0x130,
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CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE = 0x134,
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CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON = 0x138,
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CACHE_BRIDGE_ARBITER_CTRL = 0x13c,
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CACHE_PRELOAD_INT_CTRL = 0x140,
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CACHE_SYNC_INT_CTRL = 0x144,
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CACHE_MMU_OWNER = 0x148,
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CACHE_CONF_MISC = 0x14c,
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DCACHE_FREEZE = 0x150,
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ICACHE_FREEZE = 0x154,
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ICACHE_ATOMIC_OPERATE_ENA = 0x158,
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DCACHE_ATOMIC_OPERATE_ENA = 0x15c,
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CACHE_REQUEST = 0x160,
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CLOCK_GATE = 0x164,
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CACHE_TAG_OBJECT_CTRL = 0x180,
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CACHE_TAG_WAY_OBJECT = 0x184,
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CACHE_VADDR = 0x188,
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CACHE_TAG_CONTENT = 0x18c,
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DATE = 0x3fc,
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}
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}
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}
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@ -0,0 +1,437 @@
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using System.Linq;
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using System.Collections.Generic;
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using Antmicro.Renode.Core;
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using Antmicro.Renode.Core.Structure;
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using Antmicro.Renode.Core.Structure.Registers;
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using Antmicro.Renode.Logging;
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using Antmicro.Renode.Peripherals.Bus;
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using Antmicro.Renode.Peripherals.Memory;
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using Antmicro.Renode.Peripherals.MTD;
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namespace Antmicro.Renode.Peripherals.SPI
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{
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public class ESP32S3_SPIController : NullRegistrationPointPeripheralContainer<ISPIPeripheral>, IDoubleWordPeripheral, IProvidesRegisterCollection<DoubleWordRegisterCollection>, IKnownSize
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{
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public GPIO IRQ { get; private set; }
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public DoubleWordRegisterCollection RegistersCollection { get; }
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public long Size => 0x1000; // 0xb4
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private readonly Machine machine;
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public ESP32S3_SPIController(Machine machine) : base(machine)
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{
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this.machine = machine;
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IRQ = new GPIO();
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RegistersCollection = new DoubleWordRegisterCollection(this);
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DefineRegisters();
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Reset();
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}
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private void DefineRegisters()
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{
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// SPI1 memory command register
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Registers.CMD.Define(this, 0x0)
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.WithFlag(17, FieldMode.Read | FieldMode.Write, name: "FLASH_PE") // In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable.
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.WithFlag(18, FieldMode.Read | FieldMode.Write, name: "USR") // User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
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.WithFlag(19, FieldMode.Read | FieldMode.Write, name: "FLASH_HPM") // Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.
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.WithFlag(20, FieldMode.Read | FieldMode.Write, valueProviderCallback: (_) => { var val = flashReset; flashReset = false; return val; }, writeCallback: (_, val) => { if (val) flashReset = true; }, name: "FLASH_RES") // This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.
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.WithFlag(21, FieldMode.Read | FieldMode.Write, name: "FLASH_DP") // Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
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.WithFlag(22, FieldMode.Read | FieldMode.Write, name: "FLASH_CE") // Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
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.WithFlag(23, FieldMode.Read | FieldMode.Write, name: "FLASH_BE") // Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
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.WithFlag(24, FieldMode.Read | FieldMode.Write, name: "FLASH_SE") // Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
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.WithFlag(25, FieldMode.Read | FieldMode.Write, name: "FLASH_PP") // Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.
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.WithFlag(26, FieldMode.Read | FieldMode.Write, name: "FLASH_WRSR") // Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
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.WithFlag(27, FieldMode.Read | FieldMode.Write, name: "FLASH_RDSR") // Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
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.WithFlag(28, FieldMode.Read | FieldMode.Write, name: "FLASH_RDID") // Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
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.WithFlag(29, FieldMode.Read | FieldMode.Write, name: "FLASH_WRDI") // Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
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.WithFlag(30, FieldMode.Read | FieldMode.Write, name: "FLASH_WREN") // Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
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.WithFlag(31, FieldMode.Read | FieldMode.Write, name: "FLASH_READ") // Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
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;
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// SPI1 address register
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Registers.ADDR.Define(this, 0x0)
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.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "USR_ADDR_VALUE") // In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.
|
||||
;
|
||||
|
||||
// SPI1 control register
|
||||
Registers.CTRL.Define(this, 0x2ca000)
|
||||
.WithFlag(3, FieldMode.Read | FieldMode.Write, name: "FDUMMY_OUT") // In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.
|
||||
.WithFlag(4, FieldMode.Read | FieldMode.Write, name: "FDOUT_OCT") // Set this bit to enable 8-bit-mode(8-bm) in DOUT phase.
|
||||
.WithFlag(5, FieldMode.Read | FieldMode.Write, name: "FDIN_OCT") // Set this bit to enable 8-bit-mode(8-bm) in DIN phase.
|
||||
.WithFlag(6, FieldMode.Read | FieldMode.Write, name: "FADDR_OCT") // Set this bit to enable 8-bit-mode(8-bm) in ADDR phase.
|
||||
.WithFlag(7, FieldMode.Read | FieldMode.Write, name: "FCMD_DUAL") // Set this bit to enable 2-bit-mode(2-bm) in CMD phase.
|
||||
.WithFlag(8, FieldMode.Read | FieldMode.Write, name: "FCMD_QUAD") // Set this bit to enable 4-bit-mode(4-bm) in CMD phase.
|
||||
.WithFlag(9, FieldMode.Read | FieldMode.Write, name: "FCMD_OCT") // Set this bit to enable 8-bit-mode(8-bm) in CMD phase.
|
||||
.WithFlag(10, FieldMode.Read | FieldMode.Write, name: "FCS_CRC_EN") // For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.
|
||||
.WithFlag(11, FieldMode.Read | FieldMode.Write, name: "TX_CRC_EN") // For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
|
||||
.WithFlag(13, FieldMode.Read | FieldMode.Write, name: "FASTRD_MODE") // This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set.
|
||||
.WithFlag(14, FieldMode.Read | FieldMode.Write, name: "FREAD_DUAL") // In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable.
|
||||
.WithFlag(15, FieldMode.Read | FieldMode.Write, name: "RESANDRES") // The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.
|
||||
.WithFlag(18, FieldMode.Read | FieldMode.Write, name: "Q_POL") // The bit is used to set MISO line polarity, 1: high 0, low
|
||||
.WithFlag(19, FieldMode.Read | FieldMode.Write, name: "D_POL") // The bit is used to set MOSI line polarity, 1: high 0, low
|
||||
.WithFlag(20, FieldMode.Read | FieldMode.Write, name: "FREAD_QUAD") // In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable.
|
||||
.WithFlag(21, FieldMode.Read | FieldMode.Write, name: "WP") // Write protect signal output when SPI is idle. 1: output high, 0: output low.
|
||||
.WithFlag(22, FieldMode.Read | FieldMode.Write, name: "WRSR_2B") // Two bytes data will be written to status register when it is set. 1: enable 0: disable.
|
||||
.WithFlag(23, FieldMode.Read | FieldMode.Write, name: "FREAD_DIO") // In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable.
|
||||
.WithFlag(24, FieldMode.Read | FieldMode.Write, name: "FREAD_QIO") // In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable.
|
||||
;
|
||||
|
||||
// SPI1 control1 register
|
||||
Registers.CTRL1.Define(this, 0xffc)
|
||||
.WithValueField(0, 2, FieldMode.Read | FieldMode.Write, name: "CLK_MODE") // SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.
|
||||
.WithValueField(2, 10, FieldMode.Read | FieldMode.Write, name: "CS_HOLD_DLY_RES") // After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles.
|
||||
;
|
||||
|
||||
// SPI1 control2 register
|
||||
Registers.CTRL2.Define(this, 0x0)
|
||||
.WithFlag(31, FieldMode.Read | FieldMode.Write, name: "SYNC_RESET") // The FSM will be reset.
|
||||
;
|
||||
|
||||
// SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM.
|
||||
Registers.CLOCK.Define(this, 0x30103)
|
||||
.WithValueField(0, 8, FieldMode.Read | FieldMode.Write, name: "CLKCNT_L") // It must equal to the value of SPI_MEM_CLKCNT_N.
|
||||
.WithValueField(8, 8, FieldMode.Read | FieldMode.Write, name: "CLKCNT_H") // It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1).
|
||||
.WithValueField(16, 8, FieldMode.Read | FieldMode.Write, name: "CLKCNT_N") // When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)
|
||||
.WithFlag(31, FieldMode.Read | FieldMode.Write, name: "CLK_EQU_SYSCLK") // When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.
|
||||
;
|
||||
|
||||
// SPI1 user register.
|
||||
Registers.USER.Define(this, 0x80000000)
|
||||
.WithFlag(9, FieldMode.Read | FieldMode.Write, name: "CK_OUT_EDGE") // This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK.
|
||||
.WithFlag(12, FieldMode.Read | FieldMode.Write, name: "FWRITE_DUAL") // Set this bit to enable 2-bm in DOUT phase in SPI1 write operation.
|
||||
.WithFlag(13, FieldMode.Read | FieldMode.Write, name: "FWRITE_QUAD") // Set this bit to enable 4-bm in DOUT phase in SPI1 write operation.
|
||||
.WithFlag(14, FieldMode.Read | FieldMode.Write, name: "FWRITE_DIO") // Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation.
|
||||
.WithFlag(15, FieldMode.Read | FieldMode.Write, name: "FWRITE_QIO") // Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation.
|
||||
.WithFlag(24, FieldMode.Read | FieldMode.Write, name: "USR_MISO_HIGHPART") // DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable.
|
||||
.WithFlag(25, FieldMode.Read | FieldMode.Write, name: "USR_MOSI_HIGHPART") // DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable.
|
||||
.WithFlag(26, FieldMode.Read | FieldMode.Write, name: "USR_DUMMY_IDLE") // SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable.
|
||||
.WithFlag(27, FieldMode.Read | FieldMode.Write, name: "USR_MOSI") // Set this bit to enable the DOUT phase of an write-data operation.
|
||||
.WithFlag(28, FieldMode.Read | FieldMode.Write, name: "USR_MISO") // Set this bit to enable enable the DIN phase of a read-data operation.
|
||||
.WithFlag(29, FieldMode.Read | FieldMode.Write, name: "USR_DUMMY") // Set this bit to enable enable the DUMMY phase of an operation.
|
||||
.WithFlag(30, FieldMode.Read | FieldMode.Write, name: "USR_ADDR") // Set this bit to enable enable the ADDR phase of an operation.
|
||||
.WithFlag(31, FieldMode.Read | FieldMode.Write, name: "USR_COMMAND") // Set this bit to enable enable the CMD phase of an operation.
|
||||
;
|
||||
|
||||
// SPI1 user1 register.
|
||||
Registers.USER1.Define(this, 0x5c000007)
|
||||
.WithValueField(0, 6, FieldMode.Read | FieldMode.Write, name: "USR_DUMMY_CYCLELEN") // The SPI_CLK cycle length minus 1 of DUMMY phase.
|
||||
.WithValueField(26, 6, FieldMode.Read | FieldMode.Write, name: "USR_ADDR_BITLEN") // The length in bits of ADDR phase. The register value shall be (bit_num-1).
|
||||
;
|
||||
|
||||
// SPI1 user2 register.
|
||||
Registers.USER2.Define(this, 0x70000000)
|
||||
.WithValueField(0, 16, FieldMode.Read | FieldMode.Write, name: "USR_COMMAND_VALUE") // The value of user defined(USR) command.
|
||||
.WithValueField(28, 4, FieldMode.Read | FieldMode.Write, name: "USR_COMMAND_BITLEN") // The length in bits of CMD phase. The register value shall be (bit_num-1)
|
||||
;
|
||||
|
||||
// SPI1 write-data bit length register.
|
||||
Registers.MOSI_DLEN.Define(this, 0x0)
|
||||
.WithValueField(0, 10, FieldMode.Read | FieldMode.Write, name: "USR_MOSI_DBITLEN") // The length in bits of DOUT phase. The register value shall be (bit_num-1).
|
||||
;
|
||||
|
||||
// SPI1 read-data bit length register.
|
||||
Registers.MISO_DLEN.Define(this, 0x0)
|
||||
.WithValueField(0, 10, FieldMode.Read | FieldMode.Write, name: "USR_MISO_DBITLEN") // The length in bits of DIN phase. The register value shall be (bit_num-1).
|
||||
;
|
||||
|
||||
// SPI1 read control register.
|
||||
Registers.RD_STATUS.Define(this, 0x0)
|
||||
.WithValueField(0, 16, FieldMode.Read | FieldMode.Write, name: "STATUS") // The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit.
|
||||
.WithValueField(16, 8, FieldMode.Read | FieldMode.Write, name: "WB_MODE") // Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit.
|
||||
;
|
||||
|
||||
// SPI1 extended address register.
|
||||
Registers.EXT_ADDR.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "EXT_ADDR") // The register are the higher 32bits in the 64 bits address mode.
|
||||
;
|
||||
|
||||
// SPI1 misc register.
|
||||
Registers.MISC.Define(this, 0x2)
|
||||
.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "CS0_DIS") // Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts.
|
||||
.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "CS1_DIS") // Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts.
|
||||
.WithFlag(9, FieldMode.Read | FieldMode.Write, name: "CK_IDLE_EDGE") // 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle.
|
||||
.WithFlag(10, FieldMode.Read | FieldMode.Write, name: "CS_KEEP_ACTIVE") // SPI_CS line keep low when the bit is set.
|
||||
.WithFlag(11, FieldMode.Read | FieldMode.Write, name: "AUTO_PER") // Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent.
|
||||
;
|
||||
|
||||
// SPI1 CRC data register.
|
||||
Registers.TX_CRC.Define(this, 0xffffffff)
|
||||
.WithValueField(0, 32, FieldMode.Read, name: "DATA") // For SPI1, the value of crc32.
|
||||
;
|
||||
|
||||
// SPI1 bit mode control register.
|
||||
Registers.CACHE_FCTRL.Define(this, 0x0)
|
||||
.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "CACHE_USR_CMD_4BYTE") // Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.
|
||||
.WithFlag(3, FieldMode.Read | FieldMode.Write, name: "FDIN_DUAL") // When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase.
|
||||
.WithFlag(4, FieldMode.Read | FieldMode.Write, name: "FDOUT_DUAL") // When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase.
|
||||
.WithFlag(5, FieldMode.Read | FieldMode.Write, name: "FADDR_DUAL") // When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase.
|
||||
.WithFlag(6, FieldMode.Read | FieldMode.Write, name: "FDIN_QUAD") // When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase.
|
||||
.WithFlag(7, FieldMode.Read | FieldMode.Write, name: "FDOUT_QUAD") // When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase.
|
||||
.WithFlag(8, FieldMode.Read | FieldMode.Write, name: "FADDR_QUAD") // When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase.
|
||||
;
|
||||
|
||||
// SPI1 state machine(FSM) status register.
|
||||
Registers.FSM.Define(this, 0x0)
|
||||
.WithValueField(0, 3, FieldMode.Read, name: "ST") // The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE).
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer0
|
||||
Registers.W0.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF0") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer1
|
||||
Registers.W1.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF1") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer2
|
||||
Registers.W2.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF2") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer3
|
||||
Registers.W3.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF3") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer4
|
||||
Registers.W4.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF4") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer5
|
||||
Registers.W5.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF5") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer6
|
||||
Registers.W6.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF6") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer7
|
||||
Registers.W7.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF7") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer8
|
||||
Registers.W8.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF8") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer9
|
||||
Registers.W9.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF9") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer10
|
||||
Registers.W10.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF10") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer11
|
||||
Registers.W11.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF11") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer12
|
||||
Registers.W12.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF12") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer13
|
||||
Registers.W13.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF13") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer14
|
||||
Registers.W14.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF14") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 memory data buffer15
|
||||
Registers.W15.Define(this, 0x0)
|
||||
.WithValueField(0, 32, FieldMode.Read | FieldMode.Write, name: "BUF15") // data buffer
|
||||
;
|
||||
|
||||
// SPI1 wait idle control register
|
||||
Registers.FLASH_WAITI_CTRL.Define(this, 0x14)
|
||||
.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "WAITI_EN") // Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent.
|
||||
.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "WAITI_DUMMY") // Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR).
|
||||
.WithValueField(2, 8, FieldMode.Read | FieldMode.Write, name: "WAITI_CMD") // The command value of auto wait flash idle transfer(RDSR).
|
||||
.WithValueField(10, 6, FieldMode.Read | FieldMode.Write, name: "WAITI_DUMMY_CYCLELEN") // The dummy cycle length when wait flash idle(RDSR).
|
||||
;
|
||||
|
||||
// SPI1 flash suspend control register
|
||||
Registers.FLASH_SUS_CMD.Define(this, 0x0)
|
||||
.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "FLASH_PER") // program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
|
||||
.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "FLASH_PES") // program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
|
||||
.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "FLASH_PER_WAIT_EN") // Set this bit to add delay time after program erase resume(PER) is sent.
|
||||
.WithFlag(3, FieldMode.Read | FieldMode.Write, name: "FLASH_PES_WAIT_EN") // Set this bit to add delay time after program erase suspend(PES) command is sent.
|
||||
.WithFlag(4, FieldMode.Read | FieldMode.Write, name: "PES_PER_EN") // Set this bit to enable PES transfer trigger PES transfer option.
|
||||
.WithFlag(5, FieldMode.Read | FieldMode.Write, name: "PESR_IDLE_EN") // 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate.
|
||||
;
|
||||
|
||||
// SPI1 flash suspend command register
|
||||
Registers.FLASH_SUS_CTRL.Define(this, 0xeaf4)
|
||||
.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "FLASH_PES_EN") // Set this bit to enable auto-suspend function.
|
||||
.WithValueField(1, 8, FieldMode.Read | FieldMode.Write, name: "FLASH_PER_COMMAND") // Program/Erase resume command value.
|
||||
.WithValueField(9, 8, FieldMode.Read | FieldMode.Write, name: "FLASH_PES_COMMAND") // Program/Erase suspend command value.
|
||||
;
|
||||
|
||||
// SPI1 flash suspend status register
|
||||
Registers.SUS_STATUS.Define(this, 0x0)
|
||||
.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "FLASH_SUS") // The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1.
|
||||
.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "FLASH_HPM_DLY_256") // 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.
|
||||
.WithFlag(3, FieldMode.Read | FieldMode.Write, name: "FLASH_RES_DLY_256") // 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.
|
||||
.WithFlag(4, FieldMode.Read | FieldMode.Write, name: "FLASH_DP_DLY_256") // 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.
|
||||
.WithFlag(5, FieldMode.Read | FieldMode.Write, name: "FLASH_PER_DLY_256") // Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.
|
||||
.WithFlag(6, FieldMode.Read | FieldMode.Write, name: "FLASH_PES_DLY_256") // Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.
|
||||
;
|
||||
|
||||
// SPI1 timing compensation register when accesses to flash or Ext_RAM.
|
||||
Registers.TIMING_CALI.Define(this, 0x0)
|
||||
.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "TIMING_CALI") // Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.
|
||||
.WithValueField(2, 3, FieldMode.Read | FieldMode.Write, name: "EXTRA_DUMMY_CYCLELEN") // Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when SPI_MEM_TIMING_CALI bit is set.
|
||||
;
|
||||
|
||||
// SPI1 DDR control register
|
||||
Registers.DDR.Define(this, 0x20)
|
||||
.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DDR_EN") // 1: in DDR mode, 0: in SDR mode.
|
||||
.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_VAR_DUMMY") // Set the bit to enable variable dummy cycle in DDRmode.
|
||||
.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DDR_RDAT_SWP") // Set the bit to reorder RX data of the word in DDR mode.
|
||||
.WithFlag(3, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DDR_WDAT_SWP") // Set the bit to reorder TX data of the word in DDR mode.
|
||||
.WithFlag(4, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DDR_CMD_DIS") // the bit is used to disable dual edge in command phase when DDR mode.
|
||||
.WithValueField(5, 7, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_OUTMINBYTELEN") // It is the minimum output data length in the panda device.
|
||||
.WithValueField(14, 7, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_USR_DDR_DQS_THD") // The delay number of data strobe which from memory based on SPI_CLK.
|
||||
.WithFlag(21, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DDR_DQS_LOOP") // 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module
|
||||
.WithFlag(22, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DDR_DQS_LOOP_MODE") // When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.
|
||||
.WithFlag(24, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_CLK_DIFF_EN") // Set this bit to enable the differential SPI_CLK#.
|
||||
.WithFlag(25, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_HYPERBUS_MODE") // Set this bit to enable the SPI HyperBus mode.
|
||||
.WithFlag(26, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_DQS_CA_IN") // Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
|
||||
.WithFlag(27, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_HYPERBUS_DUMMY_2X") // Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.
|
||||
.WithFlag(28, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_CLK_DIFF_INV") // Set this bit to invert SPI_DIFF when accesses to flash. .
|
||||
.WithFlag(29, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_OCTA_RAM_ADDR") // Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.
|
||||
.WithFlag(30, FieldMode.Read | FieldMode.Write, name: "SPI_FMEM_HYPERBUS_CA") // Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
|
||||
;
|
||||
|
||||
// SPI1 clk_gate register
|
||||
Registers.CLOCK_GATE.Define(this, 0x1)
|
||||
.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "CLK_EN") // Register clock gate enable signal. 1: Enable. 0: Disable.
|
||||
;
|
||||
|
||||
// SPI1 interrupt enable register
|
||||
Registers.INT_ENA.Define(this, 0x0)
|
||||
.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "PER_END_INT_ENA") // The enable bit for SPI_MEM_PER_END_INT interrupt.
|
||||
.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "PES_END_INT_ENA") // The enable bit for SPI_MEM_PES_END_INT interrupt.
|
||||
.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "TOTAL_TRANS_END_INT_ENA") // The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.
|
||||
.WithFlag(3, FieldMode.Read | FieldMode.Write, name: "BROWN_OUT_INT_ENA") // The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.
|
||||
;
|
||||
|
||||
// SPI1 interrupt clear register
|
||||
Registers.INT_CLR.Define(this, 0x0)
|
||||
.WithFlag(0, FieldMode.Write, name: "PER_END_INT_CLR") // The clear bit for SPI_MEM_PER_END_INT interrupt.
|
||||
.WithFlag(1, FieldMode.Write, name: "PES_END_INT_CLR") // The clear bit for SPI_MEM_PES_END_INT interrupt.
|
||||
.WithFlag(2, FieldMode.Write, name: "TOTAL_TRANS_END_INT_CLR") // The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.
|
||||
.WithFlag(3, FieldMode.Write, name: "BROWN_OUT_INT_CLR") // The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
|
||||
;
|
||||
|
||||
// SPI1 interrupt raw register
|
||||
Registers.INT_RAW.Define(this, 0x0)
|
||||
.WithFlag(0, FieldMode.Read | FieldMode.Write, name: "PER_END_INT_RAW") // The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.
|
||||
.WithFlag(1, FieldMode.Read | FieldMode.Write, name: "PES_END_INT_RAW") // The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.
|
||||
.WithFlag(2, FieldMode.Read | FieldMode.Write, name: "TOTAL_TRANS_END_INT_RAW") // The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others.
|
||||
.WithFlag(3, FieldMode.Read | FieldMode.Write, name: "BROWN_OUT_INT_RAW") // The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.
|
||||
;
|
||||
|
||||
// SPI1 interrupt status register
|
||||
Registers.INT_ST.Define(this, 0x0)
|
||||
.WithFlag(0, FieldMode.Read, name: "PER_END_INT_ST") // The status bit for SPI_MEM_PER_END_INT interrupt.
|
||||
.WithFlag(1, FieldMode.Read, name: "PES_END_INT_ST") // The status bit for SPI_MEM_PES_END_INT interrupt.
|
||||
.WithFlag(2, FieldMode.Read, name: "TOTAL_TRANS_END_INT_ST") // The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.
|
||||
.WithFlag(3, FieldMode.Read, name: "BROWN_OUT_INT_ST") // The status bit for SPI_MEM_BROWN_OUT_INT interrupt.
|
||||
;
|
||||
|
||||
// SPI0 version control register
|
||||
Registers.DATE.Define(this, 0x2101040)
|
||||
.WithValueField(0, 28, FieldMode.Read | FieldMode.Write, name: "DATE") // SPI register version.
|
||||
;
|
||||
|
||||
}
|
||||
|
||||
public override void Reset()
|
||||
{
|
||||
RegistersCollection.Reset();
|
||||
UpdateInterrupts();
|
||||
}
|
||||
|
||||
public uint ReadDoubleWord(long offset)
|
||||
{
|
||||
return RegistersCollection.Read(offset);
|
||||
}
|
||||
|
||||
public void WriteDoubleWord(long offset, uint value)
|
||||
{
|
||||
RegistersCollection.Write(offset, value);
|
||||
}
|
||||
private void UpdateInterrupts()
|
||||
{
|
||||
var status = false;
|
||||
this.Log(LogLevel.Noisy, "Setting IRQ to {0}", status);
|
||||
IRQ.Set(status);
|
||||
}
|
||||
|
||||
private bool flashReset;
|
||||
|
||||
private enum Registers
|
||||
{
|
||||
CMD = 0x0,
|
||||
ADDR = 0x4,
|
||||
CTRL = 0x8,
|
||||
CTRL1 = 0xc,
|
||||
CTRL2 = 0x10,
|
||||
CLOCK = 0x14,
|
||||
USER = 0x18,
|
||||
USER1 = 0x1c,
|
||||
USER2 = 0x20,
|
||||
MOSI_DLEN = 0x24,
|
||||
MISO_DLEN = 0x28,
|
||||
RD_STATUS = 0x2c,
|
||||
EXT_ADDR = 0x30,
|
||||
MISC = 0x34,
|
||||
TX_CRC = 0x38,
|
||||
CACHE_FCTRL = 0x3c,
|
||||
FSM = 0x54,
|
||||
W0 = 0x58,
|
||||
W1 = 0x5c,
|
||||
W2 = 0x60,
|
||||
W3 = 0x64,
|
||||
W4 = 0x68,
|
||||
W5 = 0x6c,
|
||||
W6 = 0x70,
|
||||
W7 = 0x74,
|
||||
W8 = 0x78,
|
||||
W9 = 0x7c,
|
||||
W10 = 0x80,
|
||||
W11 = 0x84,
|
||||
W12 = 0x88,
|
||||
W13 = 0x8c,
|
||||
W14 = 0x90,
|
||||
W15 = 0x94,
|
||||
FLASH_WAITI_CTRL = 0x98,
|
||||
FLASH_SUS_CMD = 0x9c,
|
||||
FLASH_SUS_CTRL = 0xa0,
|
||||
SUS_STATUS = 0xa4,
|
||||
TIMING_CALI = 0xa8,
|
||||
DDR = 0xe0,
|
||||
CLOCK_GATE = 0xe8,
|
||||
INT_ENA = 0xf0,
|
||||
INT_CLR = 0xf4,
|
||||
INT_RAW = 0xf8,
|
||||
INT_ST = 0xfc,
|
||||
DATE = 0x3fc,
|
||||
}
|
||||
}
|
||||
}
|
||||
180
svd-to-renode.py
180
svd-to-renode.py
|
|
@ -8,7 +8,7 @@ class SVDExtractor:
|
|||
self.root = self.tree.getroot()
|
||||
self.peripherals = self.root.find("peripherals")
|
||||
|
||||
def extract(
|
||||
def extract_register_collection(
|
||||
self,
|
||||
peripheral_to_print,
|
||||
namespace,
|
||||
|
|
@ -151,10 +151,156 @@ class SVDExtractor:
|
|||
print(" }")
|
||||
print("}")
|
||||
|
||||
def extract_register_collection(
|
||||
self,
|
||||
peripheral_to_print,
|
||||
namespace,
|
||||
generated_peripheral_name,
|
||||
imports=None,
|
||||
extra_subclasses=None,
|
||||
):
|
||||
for peripheral in self.peripherals.iter("peripheral"):
|
||||
peripheral_name = peripheral.find("name").text
|
||||
if peripheral_name != peripheral_to_print:
|
||||
continue
|
||||
|
||||
register_list = dict()
|
||||
|
||||
peripheral_size = int(peripheral.find("addressBlock").find("size").text, 0)
|
||||
registers = peripheral.find("registers")
|
||||
|
||||
if imports is not None:
|
||||
for i in imports:
|
||||
print(f"using {i};")
|
||||
print()
|
||||
|
||||
print(f"namespace {namespace}")
|
||||
print("{")
|
||||
print(f" public class {generated_peripheral_name} : ", end="")
|
||||
if extra_subclasses is not None:
|
||||
for esc in extra_subclasses:
|
||||
print(f"{esc}, ", end="")
|
||||
print(
|
||||
"IDoubleWordPeripheral, IKnownSize"
|
||||
)
|
||||
print(" {")
|
||||
|
||||
print(" public GPIO IRQ { get; private set; }")
|
||||
print(
|
||||
" private readonly DoubleWordRegisterCollection registers;"
|
||||
)
|
||||
print(f" public long Size => 0x1000; // {hex(peripheral_size)}")
|
||||
print(" private readonly Machine machine;")
|
||||
print()
|
||||
|
||||
print(
|
||||
f" public {generated_peripheral_name}(Machine machine) : base(machine)"
|
||||
)
|
||||
print(" {")
|
||||
print(" this.machine = machine;")
|
||||
print()
|
||||
print(" IRQ = new GPIO();")
|
||||
print()
|
||||
print(
|
||||
" RegistersCollection = new DoubleWordRegisterCollection(this);"
|
||||
)
|
||||
print(" DefineRegisters();")
|
||||
print(" Reset();")
|
||||
print(" }")
|
||||
print()
|
||||
|
||||
print(" private void DefineRegisters()")
|
||||
print(" {")
|
||||
print(" var registersMap = new Dictionary<long, DoubleWordRegister>")
|
||||
print(" {")
|
||||
|
||||
for register in registers.iter("register"):
|
||||
register_name = register.find("name").text
|
||||
register_description = register.find("description").text
|
||||
register_offset = int(register.find("addressOffset").text, 0)
|
||||
register_default = 0
|
||||
register_reset_value_field = register.find("resetValue")
|
||||
if register_reset_value_field is not None:
|
||||
register_default = int(register_reset_value_field.text, 0)
|
||||
register_list[register_offset] = register_name
|
||||
|
||||
if "\n" in register_description:
|
||||
raise Exception("Register description contains a newline")
|
||||
print(f" // {hex(register_offset)}: {register_description}")
|
||||
print(
|
||||
f" {{(long)Registers.{register_name}, new DoubleWordRegister(this)"
|
||||
)
|
||||
for field in register.find("fields").iter("field"):
|
||||
field_offset = int(field.find("bitOffset").text, 0)
|
||||
field_width = int(field.find("bitWidth").text, 0)
|
||||
field_name = field.find("name").text
|
||||
field_description = field.find("description").text
|
||||
field_access = field.find("access").text
|
||||
|
||||
field_access_mask = ""
|
||||
if field_access == "read-write":
|
||||
field_access_mask = "FieldMode.Read | FieldMode.Write, "
|
||||
elif field_access == "read-only":
|
||||
field_access_mask = "FieldMode.Read, "
|
||||
elif field_access == "write-only":
|
||||
field_access_mask = "FieldMode.Write, "
|
||||
else:
|
||||
raise Exception(
|
||||
f"Unrecognized field access type: {field_access}"
|
||||
)
|
||||
|
||||
if "\n" in field_description:
|
||||
raise Exception("Field description contains a newline")
|
||||
|
||||
if field_width == 1:
|
||||
print(
|
||||
f' .WithFlag({field_offset}, {field_access_mask}name: "{field_name}") // {field_description}'
|
||||
)
|
||||
else:
|
||||
print(
|
||||
f' .WithValueField({field_offset}, {field_width}, {field_access_mask}name: "{field_name}") // {field_description}'
|
||||
)
|
||||
print(" },")
|
||||
print(" };")
|
||||
print(" registers = new DoubleWordRegisterCollection(this, registersMap);")
|
||||
print(" }")
|
||||
print()
|
||||
|
||||
print(" public override void Reset()")
|
||||
print(" {")
|
||||
print(" RegistersCollection.Reset();")
|
||||
print(" UpdateInterrupts();")
|
||||
print(" }")
|
||||
print()
|
||||
print(" public uint ReadDoubleWord(long offset)")
|
||||
print(" {")
|
||||
print(" return RegistersCollection.Read(offset);")
|
||||
print(" }")
|
||||
print()
|
||||
print(" public void WriteDoubleWord(long offset, uint value)")
|
||||
print(" {")
|
||||
print(" RegistersCollection.Write(offset, value);")
|
||||
print(" }")
|
||||
|
||||
print(" private void UpdateInterrupts()")
|
||||
print(" {")
|
||||
print(" var status = false;")
|
||||
print(' this.Log(LogLevel.Noisy, "Setting IRQ to {0}", status);')
|
||||
print(" IRQ.Set(status);")
|
||||
print(" }")
|
||||
print()
|
||||
print(" private enum Registers")
|
||||
print(" {")
|
||||
for offset, name in register_list.items():
|
||||
print(f" {name} = {hex(offset)},")
|
||||
print(" }")
|
||||
print(" }")
|
||||
print("}")
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
extractor = SVDExtractor("esp32s3.svd")
|
||||
# extractor.extract(
|
||||
# extractor.extract_register_collection(
|
||||
# "SPI1",
|
||||
# "Antmicro.Renode.Peripherals.SPI",
|
||||
# "ESP32_SPIController",
|
||||
|
|
@ -171,19 +317,35 @@ if __name__ == "__main__":
|
|||
# ],
|
||||
# extra_subclasses=["NullRegistrationPointPeripheralContainer<ISPIPeripheral>"],
|
||||
# )
|
||||
extractor.extract(
|
||||
"INTERRUPT_CORE0",
|
||||
"Antmicro.Renode.Peripherals.IRQControllers",
|
||||
# extractor.extract_register_collection(
|
||||
# "INTERRUPT_CORE0",
|
||||
# "Antmicro.Renode.Peripherals.IRQControllers",
|
||||
# "ESP32S3",
|
||||
# imports=[
|
||||
# "System",
|
||||
# "System.Collections.ObjectModel",
|
||||
# "Antmicro.Renode.Peripherals.Bus",
|
||||
# "Antmicro.Renode.Core",
|
||||
# "Antmicro.Renode.Core.Structure.Registers",
|
||||
# "Antmicro.Renode.Logging",
|
||||
# "System.Collections.Generic",
|
||||
# "Antmicro.Renode.Utilities",
|
||||
# ],
|
||||
# extra_subclasses=["IIRQController", "INumberedGPIOOutput"],
|
||||
# )
|
||||
extractor.extract_register_collection(
|
||||
"EXTMEM",
|
||||
"Antmicro.Renode.Peripherals.Miscellaneous",
|
||||
"ESP32S3",
|
||||
imports=[
|
||||
"System",
|
||||
"System.Collections.ObjectModel",
|
||||
"Antmicro.Renode.Peripherals.Bus",
|
||||
"Antmicro.Renode.Core",
|
||||
"Antmicro.Renode.Core.Structure.Registers",
|
||||
"Antmicro.Renode.Peripherals",
|
||||
"Antmicro.Renode.Utilities",
|
||||
"Antmicro.Renode.Logging",
|
||||
"System.Collections.Generic",
|
||||
"Antmicro.Renode.Utilities",
|
||||
"Antmicro.Renode.Core.Structure.Registers",
|
||||
],
|
||||
extra_subclasses=["IIRQController", "INumberedGPIOOutput"],
|
||||
extra_subclasses=[],
|
||||
)
|
||||
|
|
|
|||
Loading…
Reference in New Issue