index: add section headers
Signed-off-by: Sean Cross <sean@xobs.io>
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index.html
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index.html
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@ -94,6 +94,7 @@
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</section>
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<section>
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<h2>Introduction</h2>
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<aside class="notes">
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This is the Open ISA miniconf, which today tends to mean FPGAs. This means that
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hardware and software are both extensible, and developers will be able to extend
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@ -102,6 +103,21 @@
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</section>
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<section>
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<h2>About Me</h2>
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<aside class="notes">
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My name is Sean Cross, also known as "xobs". I will be speaking later this week
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on the Betrusted project, but many know me as the main developer behind the Fomu
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project. Fomu is an FPGA that fits in your USB port. One of my goals with the
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Fomu project was to allow people to treat it as just a RISC-V CPU in their USB
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port, which means now we need to make documentation. This talk covers some of
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the problems I ran into while working on this project, and the solutions I came
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up with.
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</aside>
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</section>
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<section>
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<h2>Undocumented Hardware = Bad</h2>
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<h4>(But so easy to do!)</h4>
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<aside class="notes">
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Undocumented hardware is bad. There are all sorts of quirks, and even if you have
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the source code, it can be very difficult to read. I'm the primary developer for
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@ -109,10 +125,15 @@
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respect to documentation. It is most directly related to the LiteX and Migen
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projects, but the concepts will carry over into any other Hardware Description
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Language you may use.
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The goal of this talk is to show how it's easy to document hardware with
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the right framework, and how it's easier to have a project that's documented
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than one that isn't.
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</aside>
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</section>
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<section>
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<h2>Talk Outline</h2>
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<aside class="notes">
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I'll briefly cover various methods of writing HDL code, then cover the rationale
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behind the approach we take with lxsocdoc, then give an example of how to use
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@ -122,6 +143,7 @@
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</section>
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<section>
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<h2>Motivation</h2>
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<aside class="notes">
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Verilog and VHDL are kind of the C or assembly of the FPGA world. They're universal,
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but somewhat unwieldy to use. You need to manually set up your address decoders,
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@ -134,6 +156,7 @@
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</section>
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<section>
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<h2>About LiteX and lxsocdoc</h2>
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<aside class="notes">
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Fomu uses LiteX, which is related to Migen. This is a hardware description language
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written in Python. You write Python code and run the program, and it generates
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@ -146,6 +169,7 @@
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</section>
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<section>
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<h2>LiteX Primitives</h2>
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<aside class="notes">
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In LiteX, two of the primitives used to expose hardware registers to the CPU softcore
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are CSRStorage and CSRStatus. Instead of manually wiring up a crossbar and decoding
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@ -163,10 +187,13 @@ If(self.bitbang.storage[3],
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).Else(
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dq.oe.eq(1)
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),
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If(self.bitbang.storage[1], # CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
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# CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
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If(self.bitbang.storage[1],
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self.miso.status.eq(dq.i[1])
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),
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dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))</code></pre>
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dq.o.eq(
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Cat(self.bitbang.storage[0], Replicate(1, spi_width-1))
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)</code></pre>
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<aside class="notes">
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This works well, but exposes a new problem: Documentation. As an example, I was
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working with the SPI Flash block in litex, and wanted to know how the bitbang
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@ -180,6 +207,7 @@ dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))</code></pre>
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</section>
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<section>
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<h2>Aside: Python Docstrings</h2>
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<aside class="notes">
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As an aside, Python has something called Pydoc and Docstrings. These are
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comments that go at the top of functions and classes that let you describe
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@ -191,42 +219,45 @@ dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))</code></pre>
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</section>
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<section>
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<h4>New Register Definition</h4>
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<pre><code class="python" data-trim>self.bitbang = CSRStorage(4, fields=[
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CSRField("mosi", description="Output value for MOSI pin, valid whenever ``dir`` is ``0``."),
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CSRField("clk", description="Output value for SPI CLK pin."),
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CSRField("cs_n", description="Output value for SPI CSn pin."),
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CSRField("dir", description="Sets the direction for *ALL* SPI data pins except CLK and CSn.", values=[
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("0", "OUT", "SPI pins are all output"),
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("1", "IN", "SPI pins are all input"),
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])
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], description="""
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Bitbang controls for SPI output. Only standard 1x SPI is supported, and as
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a result all four wires are ganged together. This means that it is only possible
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to perform half-duplex operations, using this SPI core.
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""")</code></pre>
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<aside class="notes">
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This is when I hit upon the idea of `lxsocdoc`. The basic idea is that
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Python is really good at introspecting Python, so let's add a little bit
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more information to the CSR objects to make our life easier. And so, after
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working with the LiteX creator Florent, we refactored the bitbang
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definition to this:
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self.bitbang = CSRStorage(4, fields=[
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CSRField("mosi", description="Output value for MOSI pin, valid whenever ``dir`` is ``0``."),
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CSRField("clk", description="Output value for SPI CLK pin."),
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CSRField("cs_n", description="Output value for SPI CSn pin."),
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CSRField("dir", description="Sets the direction for *ALL* SPI data pins except CLK and CSn.", values=[
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("0", "OUT", "SPI pins are all output"),
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("1", "IN", "SPI pins are all input"),
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])
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], description="""
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Bitbang controls for SPI output. Only standard 1x SPI is supported, and as
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a result all four wires are ganged together. This means that it is only possible
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to perform half-duplex operations, using this SPI core.
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""")
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definition to this.
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</aside>
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</section>
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<section>
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<h4>Refactored SPI Bitbang</h4>
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<pre><code class="python" data-trim>If(self.bitbang.fields.dir,
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dq.oe.eq(0)
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).Else(
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dq.oe.eq(1)
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),
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# CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
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If(self.bitbang.fields.clk,
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self.miso.status.eq(dq.i[1])
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),
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dq.o.eq(
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Cat(self.bitbang.fields.mosi, Replicate(1, spi_width-1))
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)</code></pre>
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<aside class="notes">
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Now the actual bitbang logic looks like:
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If(self.bitbang.fields.dir,
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dq.oe.eq(0)
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).Else(
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dq.oe.eq(1)
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),
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If(self.bitbang.fields.clk, # CPOL=0/CPHA=0 or CPOL=1/CPHA=1 only.
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self.miso.status.eq(dq.i[1])
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),
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dq.o.eq(Cat(self.bitbang.fields.mosi, Replicate(1, spi_width-1)))
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Now the actual bitbang logic looks like this.
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This is a little bit easier to understand -- no longer are we looking at indices
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in an array to determine what field does what. Instead we get actual named fields.
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@ -235,6 +266,7 @@ dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))</code></pre>
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</section>
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<section>
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<h2>Generating a Manual</h2>
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<aside class="notes">
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After the design is elaborated and the output file is generated, we can iterate
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through the resulting tree and pick out any CSR objects and using any additional
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@ -255,6 +287,7 @@ dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))</code></pre>
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</section>
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<section>
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<h2>More Documentation: ModuleDoc</h2>
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<aside class="notes">
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So now we have register documentation. Can we do better? Of course we can.
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SoC reference manuals are more than just register definitions. They also include
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@ -263,9 +296,19 @@ dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))</code></pre>
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in a similar fashion.
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</aside>
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</section>
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---ModuleDoc---
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<section>
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<h2>Protocol Documentation</h2>
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<aside class="notes">
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We can add additional documentation such as protocol waveforms. Here
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we use WaveDrom to define the protocol of Wishbone-over-SPI. There
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are multiple formats of the protocol depending on which version is
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instantiated.
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</aside>
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</section>
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<section>
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<h2>SVD: Documentation for Machines</h2>
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<aside class="notes">
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Having documentation for humans is great, but we can go one step further and
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make documentation for computers. SVD is an XML format defined by ARM that
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@ -276,6 +319,7 @@ dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))</code></pre>
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</section>
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<section>
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<h2>SVD2Rust: Generating Safe Accessors</h2>
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<aside class="notes">
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In addition to generating a reference manual for humans, we can generate an SVD
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file that's usable in a wide variety of areas. For example, we can turn an SVD
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@ -285,28 +329,13 @@ dq.o.eq(Cat(self.bitbang.storage[0], Replicate(1, spi_width-1)))</code></pre>
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</section>
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<section>
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<h2>Renode: Fancy Register Logging</h2>
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<aside class="notes">
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We can also import this SVD file into an emulator such as Renode, which will
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print out fields and flags that get accessed, giving us greater visibility into
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what a program is doing.
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</aside>
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</section>
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lxsocdoc
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intro to litex/migen
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concept of mixins
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concept of documentation sections
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what the output can look like
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what's coming in the future
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documenting interrupts
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introspecting classes
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other approaches
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how you can help
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why this helps you
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Benefits:
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* Generating reference manuals
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* SVD
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* SVD2Rust
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</div>
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</div> <!-- class="reveal" -->
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<!-- End of main presentation -->
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