self.bitbang = CSRStorage(4, fields=[
+ CSRField("mosi", description="Output value for MOSI pin, valid whenever ``dir`` is ``0``."),
+ CSRField("clk", description="Output value for SPI CLK pin."),
+ CSRField("cs_n", description="Output value for SPI CSn pin."),
+ CSRField("dir", description="Sets the direction for *ALL* SPI data pins except CLK and CSn.", values=[
+ ("0", "OUT", "SPI pins are all output"),
+ ("1", "IN", "SPI pins are all input"),
+ ])
+], description="""
+ Bitbang controls for SPI output. Only standard 1x SPI is supported, and as
+ a result all four wires are ganged together. This means that it is only possible
+ to perform half-duplex operations, using this SPI core.
+""")
- lxsocdoc
- intro to litex/migen
- concept of mixins
- concept of documentation sections
- what the output can look like
- what's coming in the future
- documenting interrupts
- introspecting classes
- other approaches
- how you can help
- why this helps you
-
- Benefits:
- * Generating reference manuals
- * SVD
- * SVD2Rust