619 lines
23 KiB
Python
Executable File
619 lines
23 KiB
Python
Executable File
#!/usr/bin/env python3
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# This variable defines all the external programs that this module
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# relies on. lxbuildenv reads this variable in order to ensure
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# the build will finish without exiting due to missing third-party
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# programs.
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LX_DEPENDENCIES = ["riscv", "icestorm", "yosys"]
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# Import lxbuildenv to integrate the deps/ directory
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import lxbuildenv
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# Disable pylint's E1101, which breaks completely on migen
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#pylint:disable=E1101
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#from migen import *
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from migen import Module, Signal, Instance, ClockDomain, If
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.fhdl.specials import TSTriple
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from migen.fhdl.structure import ClockSignal, ResetSignal, Replicate, Cat
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from litex.build.lattice.platform import LatticePlatform
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from litex.build.generic_platform import Pins, IOStandard, Misc, Subsignal
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from litex.soc.integration import SoCCore
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from litex.soc.integration.builder import Builder
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from litex.soc.integration.soc_core import csr_map_update
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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from valentyusb import usbcore
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from valentyusb.usbcore import io as usbio
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from valentyusb.usbcore.cpu import epmem, unififo, epfifo
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from valentyusb.usbcore.endpoint import EndpointType
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from lxsocsupport import up5kspram, spi_flash
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import argparse
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_io_evt = [
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("serial", 0,
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Subsignal("rx", Pins("21")),
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Subsignal("tx", Pins("13"), Misc("PULLUP")),
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IOStandard("LVCMOS33")
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),
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("usb", 0,
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Subsignal("d_p", Pins("34")),
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Subsignal("d_n", Pins("37")),
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Subsignal("pullup", Pins("35")),
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IOStandard("LVCMOS33")
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),
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("pmoda", 0,
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Subsignal("p1", Pins("28"), IOStandard("LVCMOS33")),
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Subsignal("p2", Pins("27"), IOStandard("LVCMOS33")),
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Subsignal("p3", Pins("26"), IOStandard("LVCMOS33")),
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Subsignal("p4", Pins("23"), IOStandard("LVCMOS33")),
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),
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("pmodb", 0,
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Subsignal("p1", Pins("48"), IOStandard("LVCMOS33")),
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Subsignal("p2", Pins("47"), IOStandard("LVCMOS33")),
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Subsignal("p3", Pins("46"), IOStandard("LVCMOS33")),
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Subsignal("p4", Pins("45"), IOStandard("LVCMOS33")),
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")),
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Subsignal("wp", Pins("18"), IOStandard("LVCMOS33")),
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Subsignal("hold", Pins("19"), IOStandard("LVCMOS33")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
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Subsignal("dq", Pins("14 17 19 18"), IOStandard("LVCMOS33")),
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),
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("clk48", 0, Pins("44"), IOStandard("LVCMOS33"))
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]
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_io_dvt = [
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("serial", 0,
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Subsignal("rx", Pins("C3")),
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Subsignal("tx", Pins("B3"), Misc("PULLUP")),
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IOStandard("LVCMOS33")
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),
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("usb", 0,
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Subsignal("d_p", Pins("A1")),
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Subsignal("d_n", Pins("A2")),
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Subsignal("pullup", Pins("A4")),
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IOStandard("LVCMOS33")
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("C1"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("D1"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("E1"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("F1"), IOStandard("LVCMOS33")),
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Subsignal("wp", Pins("F2"), IOStandard("LVCMOS33")),
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Subsignal("hold", Pins("B1"), IOStandard("LVCMOS33")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("C1"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("D1"), IOStandard("LVCMOS33")),
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Subsignal("dq", Pins("E1 F1 F2 B1"), IOStandard("LVCMOS33")),
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),
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("clk48", 0, Pins("F4"), IOStandard("LVCMOS33"))
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]
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_connectors = []
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class _CRG(Module):
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def __init__(self, platform, use_pll):
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if use_pll:
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clk48_raw = platform.request("clk48")
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clk12_raw = Signal()
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clk48 = Signal()
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clk12 = Signal()
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# Divide clk48 down to clk12, to ensure they're synchronized.
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# By doing this, we avoid needing clock-domain crossing.
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clk12_counter = Signal(2)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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self.clock_domains.cd_usb_48_raw = ClockDomain()
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platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6)
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platform.add_period_constraint(self.cd_usb_48_raw.clk, 1e9/48e6)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6)
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platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6)
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platform.add_period_constraint(clk48, 1e9/48e6)
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platform.add_period_constraint(clk48_raw, 1e9/48e6)
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self.reset = Signal()
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.clock_domains.cd_por = ClockDomain()
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reset_delay = Signal(10, reset=1023)
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self.comb += [
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self.cd_por.clk.eq(self.cd_sys.clk),
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self.cd_sys.rst.eq(reset_delay != 0),
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self.cd_usb_12.rst.eq(reset_delay != 0),
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self.cd_usb_48.rst.eq(reset_delay != 0),
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# self.cd_usb_48_raw.rst.eq(reset_delay != 0),
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]
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self.comb += self.cd_usb_48_raw.clk.eq(clk48_raw)
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self.comb += self.cd_usb_48.clk.eq(clk48)
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self.sync.usb_48_raw += clk12_counter.eq(clk12_counter + 1)
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self.comb += clk12_raw.eq(clk12_counter[1])
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw,
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o_GLOBAL_BUFFER_OUTPUT=clk12,
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)
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platform.add_period_constraint(clk12_raw, 1e9/12e6)
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self.specials += Instance(
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"SB_PLL40_CORE",
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# Parameters
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p_DIVR = 0,
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p_DIVF = 3,
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p_DIVQ = 2,
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p_FILTER_RANGE = 1,
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p_FEEDBACK_PATH = "PHASE_AND_DELAY",
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p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED",
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p_FDA_FEEDBACK = 15,
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p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED",
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p_FDA_RELATIVE = 0,
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p_SHIFTREG_DIV_MODE = 1,
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p_PLLOUT_SELECT = "SHIFTREG_0deg",
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p_ENABLE_ICEGATE = 0,
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# IO
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i_REFERENCECLK = clk12,
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# o_PLLOUTCORE = clk12,
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o_PLLOUTGLOBAL = clk48,
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#i_EXTFEEDBACK,
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#i_DYNAMICDELAY,
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#o_LOCK,
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i_BYPASS = 0,
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i_RESETB = 1,
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#i_LATCHINPUTVALUE,
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#o_SDO,
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#i_SDI,
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)
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else:
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clk48_raw = platform.request("clk48")
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clk12_raw = Signal()
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clk48 = Signal()
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clk12 = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6)
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platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6)
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platform.add_period_constraint(clk48, 1e9/48e6)
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self.reset = Signal()
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.clock_domains.cd_por = ClockDomain()
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reset_delay = Signal(10, reset=1023)
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self.comb += [
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self.cd_por.clk.eq(self.cd_sys.clk),
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self.cd_sys.rst.eq(reset_delay != 0),
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self.cd_usb_12.rst.eq(reset_delay != 0),
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# self.cd_usb_48.rst.eq(reset_delay != 0),
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]
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk48_raw,
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o_GLOBAL_BUFFER_OUTPUT=clk48,
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)
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self.comb += self.cd_usb_48.clk.eq(clk48)
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clk12_counter = Signal(2)
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self.sync.usb_48 += clk12_counter.eq(clk12_counter + 1)
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self.comb += clk12_raw.eq(clk12_counter[1])
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platform.add_period_constraint(clk12_raw, 1e9/12e6)
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw,
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o_GLOBAL_BUFFER_OUTPUT=clk12,
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)
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self.comb += self.cd_sys.clk.eq(clk12)
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self.comb += self.cd_usb_12.clk.eq(clk12)
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self.sync.por += \
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If(reset_delay != 0,
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reset_delay.eq(reset_delay - 1)
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)
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self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
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class RandomFirmwareROM(wishbone.SRAM):
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"""
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Seed the random data with a fixed number, so different bitstreams
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can all share firmware.
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"""
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def __init__(self, size, seed=2373):
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def xorshift32(x):
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x = x ^ (x << 13) & 0xffffffff
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x = x ^ (x >> 17) & 0xffffffff
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x = x ^ (x << 5) & 0xffffffff
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return x & 0xffffffff
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def get_rand(x):
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out = 0
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for i in range(32):
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x = xorshift32(x)
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if (x & 1) == 1:
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out = out | (1 << i)
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return out & 0xffffffff
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data = []
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seed = 1
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for d in range(int(size / 4)):
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seed = get_rand(seed)
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data.append(seed)
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wishbone.SRAM.__init__(self, size, read_only=True, init=data)
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class FirmwareROM(wishbone.SRAM):
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def __init__(self, size, filename):
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data = []
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with open(filename, 'rb') as inp:
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data = inp.read()
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wishbone.SRAM.__init__(self, size, read_only=True, init=data)
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class Platform(LatticePlatform):
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default_clk_name = "clk48"
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default_clk_period = 20.833
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gateware_size = 0x20000
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def __init__(self, revision=None, toolchain="icestorm"):
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if revision == "evt":
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LatticePlatform.__init__(self, "ice40-up5k-sg48", _io_evt, _connectors, toolchain="icestorm")
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elif revision == "dvt":
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LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io_dvt, _connectors, toolchain="icestorm")
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else:
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raise ValueError("Unrecognized reivsion: {}. Known values: evt, dvt".format(revision))
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def create_programmer(self):
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raise ValueError("programming is not supported")
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class SBWarmBoot(Module, AutoCSR):
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def __init__(self):
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self.ctrl = CSRStorage(size=3)
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# do_reset = Signal()
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# self.comb += [
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# # "Reset Key" is 0xac
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# do_reset.eq(self.ctrl.storage[2] & self.ctrl.storage[3] & ~self.ctrl.storage[4]
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# & self.ctrl.storage[5] & ~self.ctrl.storage[6] & self.ctrl.storage[7])
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# ]
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self.specials += Instance("SB_WARMBOOT",
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i_S0 = self.ctrl.storage[0],
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i_S1 = self.ctrl.storage[1],
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i_BOOT = self.ctrl.storage[2] & self.ctrl.re,
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)
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class BBSpi(Module, AutoCSR):
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def __init__(self, platform, pads):
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self.reset = Signal()
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# self.rdata = Signal(32)
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# self.addr = Signal(24)
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# self.ready = Signal()
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# self.valid = Signal()
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# self.flash_csb = Signal()
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# self.flash_clk = Signal()
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# cfgreg_we = Signal(4)
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# cfgreg_di = Signal(32)
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# cfgreg_do = Signal(32)
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mosi_pad = TSTriple()
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miso_pad = TSTriple()
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cs_n_pad = TSTriple()
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clk_pad = TSTriple()
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wp_pad = TSTriple()
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hold_pad = TSTriple()
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self.do = CSRStorage(size=6)
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self.oe = CSRStorage(size=6)
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self.di = CSRStatus(size=6)
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# self.cfg = CSRStorage(size=8)
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# cfg_remapped = Cat(self.cfg.storage[0:7], Signal(7), self.cfg.storage[7])
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# self.comb += self.reset.eq(0)
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# self.comb += [
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# cfgreg_di.eq(Cat(self.do.storage, Replicate(2, 0), # Attach "DO" to lower 6 bits
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# self.oe.storage, Replicate(4, 0), # Attach "OE" to bits 8-11
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# cfg_remapped)),
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# cfgreg_we.eq(Cat(self.do.re, self.oe.re, self.cfg.re, self.cfg.re)),
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# self.di.status.eq(cfgreg_do),
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# clk_pad.oe.eq(~self.reset),
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# cs_n_pad.oe.eq(~self.reset),
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# ]
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self.specials += mosi_pad.get_tristate(pads.mosi)
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self.specials += miso_pad.get_tristate(pads.miso)
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self.specials += cs_n_pad.get_tristate(pads.cs_n)
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self.specials += clk_pad.get_tristate(pads.clk)
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self.specials += wp_pad.get_tristate(pads.wp)
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self.specials += hold_pad.get_tristate(pads.hold)
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self.comb += [
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mosi_pad.oe.eq(self.oe.storage[0]),
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miso_pad.oe.eq(self.oe.storage[1]),
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wp_pad.oe.eq(self.oe.storage[2]),
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hold_pad.oe.eq(self.oe.storage[3]),
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clk_pad.oe.eq(self.oe.storage[4]),
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cs_n_pad.oe.eq(self.oe.storage[5]),
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mosi_pad.o.eq(self.do.storage[0]),
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miso_pad.o.eq(self.do.storage[1]),
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wp_pad.o.eq(self.do.storage[2]),
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hold_pad.o.eq(self.do.storage[3]),
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clk_pad.o.eq(self.do.storage[4]),
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cs_n_pad.o.eq(self.do.storage[5]),
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self.di.status.eq(Cat(mosi_pad.i, miso_pad.i, wp_pad.i, hold_pad.i, clk_pad.i, cs_n_pad.i)),
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]
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# self.specials += Instance("spimemio",
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# o_flash_io0_oe = mosi_pad.oe,
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# o_flash_io1_oe = miso_pad.oe,
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# o_flash_io2_oe = wp_pad.oe,
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# o_flash_io3_oe = hold_pad.oe,
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# o_flash_io0_do = mosi_pad.o,
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# o_flash_io1_do = miso_pad.o,
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# o_flash_io2_do = wp_pad.o,
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# o_flash_io3_do = hold_pad.o,
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# i_flash_io0_di = mosi_pad.i,
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# i_flash_io1_di = miso_pad.i,
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# i_flash_io2_di = wp_pad.i,
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# i_flash_io3_di = hold_pad.i,
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# i_resetn = ResetSignal() | self.reset,
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# i_clk = ClockSignal(),
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# i_valid = self.valid,
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# o_ready = self.ready,
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# i_addr = self.addr,
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# o_rdata = self.rdata,
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# i_cfgreg_we = cfgreg_we,
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# i_cfgreg_di = cfgreg_di,
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# o_cfgreg_do = cfgreg_do,
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# o_flash_csb = self.flash_csb,
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# o_flash_clk = self.flash_clk,
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# )
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# platform.add_source("spimemio.v")
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class BaseSoC(SoCCore):
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csr_peripherals = [
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"cpu_or_bridge",
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"usb",
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"bbspi",
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"reboot",
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]
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csr_map_update(SoCCore.csr_map, csr_peripherals)
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mem_map = {
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"spiflash": 0x20000000, # (default shadow @0xa0000000)
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}
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mem_map.update(SoCCore.mem_map)
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interrupt_map = {
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"usb": 3,
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}
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interrupt_map.update(SoCCore.interrupt_map)
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def __init__(self, platform, boot_source="random_rom", debug=False, bios_file=None, use_pll=True, **kwargs):
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# Disable integrated RAM as we'll add it later
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self.integrated_sram_size = 0
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clk_freq = int(12e6)
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self.submodules.crg = _CRG(platform, use_pll=use_pll)
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SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, with_uart=False, **kwargs)
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if debug:
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self.cpu.use_external_variant("2-stage-1024-cache-debug.v")
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from litex.soc.cores.uart import UARTWishboneBridge
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self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x10)
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self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
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self.add_wb_master(self.uart_bridge.wishbone)
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else:
|
|
self.cpu.use_external_variant("2-stage-1024-cache.v")
|
|
|
|
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
|
|
# free up scarce block RAM.
|
|
spram_size = 128*1024
|
|
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
|
|
self.register_mem("sram", 0x10000000, self.spram.bus, spram_size)
|
|
|
|
if boot_source == "random_rom":
|
|
kwargs['cpu_reset_address']=0
|
|
bios_size = 0x2000
|
|
self.submodules.random_rom = RandomFirmwareROM(bios_size)
|
|
self.add_constant("ROM_DISABLE", 1)
|
|
self.register_rom(self.random_rom.bus, bios_size)
|
|
elif boot_source == "bios_rom":
|
|
kwargs['cpu_reset_address']=0
|
|
if bios_file is None:
|
|
bios_size = 0x2000
|
|
self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size)
|
|
else:
|
|
bios_size = 0x2000
|
|
self.submodules.firmware_rom = FirmwareROM(bios_size, bios_file)
|
|
self.add_constant("ROM_DISABLE", 1)
|
|
self.register_rom(self.firmware_rom.bus, bios_size)
|
|
|
|
elif boot_source == "spi_rom":
|
|
bios_size = 0x8000
|
|
kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size
|
|
self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size)
|
|
self.add_constant("ROM_DISABLE", 1)
|
|
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size
|
|
self.add_memory_region("user_flash",
|
|
self.flash_boot_address,
|
|
# Leave a grace area- possible one-by-off bug in add_memory_region?
|
|
# Possible fix: addr < origin + length - 1
|
|
platform.spiflash_total_size - (self.flash_boot_address - self.mem_map["spiflash"]) - 0x100)
|
|
else:
|
|
raise ValueError("unrecognized boot_source: {}".format(boot_source))
|
|
|
|
# Add a simple bit-banged SPI Flash module
|
|
spi_pads = platform.request("spiflash")
|
|
self.submodules.bbspi = BBSpi(platform, spi_pads)
|
|
|
|
self.submodules.reboot = SBWarmBoot()
|
|
|
|
# Add USB pads
|
|
usb_pads = platform.request("usb")
|
|
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
|
|
self.submodules.usb = epfifo.PerEndpointFifoInterface(usb_iobuf, endpoints=[EndpointType.BIDIR])
|
|
# self.submodules.usb = epmem.MemInterface(usb_iobuf)
|
|
# self.submodules.usb = unififo.UsbUniFifo(usb_iobuf)
|
|
|
|
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
|
|
# The "-reult" adds an additional LUT pass to pack more stuff in,
|
|
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
|
|
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
|
|
# This increases density, and lets us use the FPGA more efficiently.
|
|
platform.toolchain.nextpnr_yosys_template[2] += " -dsp -relut -dffe_min_ce_use 5"
|
|
|
|
# Disable final deep-sleep power down so firmware words are loaded
|
|
# onto softcore's address bus.
|
|
platform.toolchain.build_template[3] = "icepack -s {build_name}.txt {build_name}.bin"
|
|
platform.toolchain.nextpnr_build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
|
|
|
|
# # Add a "Multiboot" variant
|
|
# platform.toolchain.nextpnr_build_template[3] = "icepack -s {build_name}.txt {build_name}-multi.bin"
|
|
|
|
def make_multiboot_header(filename, boot_offsets=[128]):
|
|
"""
|
|
ICE40 allows you to program the SB_WARMBOOT state machine by adding the following
|
|
values to the bitstream, before any given image:
|
|
|
|
[7e aa 99 7e] Sync Header
|
|
[92 00 k0] Boot mode (k = 1 for cold boot, 0 for warmboot)
|
|
[44 03 o1 o2 o3] Boot address
|
|
[82 00 00] Bank offset
|
|
[01 08] Reboot
|
|
|
|
Note that in ICE40, the second nybble indicates the number of remaining bytes
|
|
(with the exception of the sync header)
|
|
"""
|
|
with open(filename, 'wb') as output:
|
|
for offset in boot_offsets:
|
|
# Sync Header
|
|
output.write(bytes([0x7e, 0xaa, 0x99, 0x7e]))
|
|
|
|
# Boot mode
|
|
output.write(bytes([0x92, 0x00, 0x00]))
|
|
|
|
# Boot address
|
|
output.write(bytes([0x44, 0x03,
|
|
(offset >> 16) & 0xff,
|
|
(offset >> 8) & 0xff,
|
|
(offset >> 0) & 0xff]))
|
|
|
|
# Bank offset
|
|
output.write(bytes([0x82, 0x00, 0x00]))
|
|
|
|
# Reboot command
|
|
output.write(bytes([0x01, 0x08]))
|
|
|
|
for x in range(17, 32):
|
|
output.write(bytes([0]))
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description="Build Fomu Main Gateware")
|
|
parser.add_argument(
|
|
"--boot-source", choices=["spi", "rand", "bios"], default="rand",
|
|
help="where to have the CPU obtain its executable code from"
|
|
)
|
|
parser.add_argument(
|
|
"--revision", choices=["dvt", "evt"], required=True,
|
|
help="build foboot for a particular hardware revision"
|
|
)
|
|
parser.add_argument(
|
|
"--bios", help="use specified file as a BIOS, rather than building one"
|
|
)
|
|
parser.add_argument(
|
|
"--with-debug", help="enable debug support", action="store_true"
|
|
)
|
|
parser.add_argument(
|
|
"--no-pll", help="disable pll (possibly improving timing)", action="store_false"
|
|
)
|
|
parser.add_argument(
|
|
"--export-random-rom-file", help="Generate a random ROM file and save it to a file"
|
|
)
|
|
args = parser.parse_args()
|
|
|
|
if args.export_random_rom_file is not None:
|
|
size = 0x2000
|
|
def xorshift32(x):
|
|
x = x ^ (x << 13) & 0xffffffff
|
|
x = x ^ (x >> 17) & 0xffffffff
|
|
x = x ^ (x << 5) & 0xffffffff
|
|
return x & 0xffffffff
|
|
|
|
def get_rand(x):
|
|
out = 0
|
|
for i in range(32):
|
|
x = xorshift32(x)
|
|
if (x & 1) == 1:
|
|
out = out | (1 << i)
|
|
return out & 0xffffffff
|
|
seed = 1
|
|
with open(args.export_random_rom_file, "w", newline="\n") as output:
|
|
for d in range(int(size / 4)):
|
|
seed = get_rand(seed)
|
|
print("{:08x}".format(seed), file=output)
|
|
return 0
|
|
|
|
bios_file = None
|
|
compile_software = False
|
|
if args.boot_source == "rand":
|
|
boot_source = "random_rom"
|
|
elif args.boot_source == "bios":
|
|
boot_source = "bios_rom"
|
|
if args.bios is not None:
|
|
bios_file = args.bios
|
|
else:
|
|
compile_software = True
|
|
elif args.boot_source == "spi":
|
|
boot_source = "spi_rom"
|
|
|
|
cpu_variant = "min"
|
|
debug = False
|
|
if args.with_debug:
|
|
cpu_variant = "debug"
|
|
debug = True
|
|
|
|
platform = Platform(revision=args.revision)
|
|
soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant=cpu_variant,
|
|
debug=debug, boot_source=boot_source,
|
|
bios_file=bios_file, use_pll=args.no_pll)
|
|
builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv", compile_software=compile_software)
|
|
vns = builder.build()
|
|
soc.do_exit(vns)
|
|
|
|
if __name__ == "__main__":
|
|
main()
|