hw: add spi and new vexriscv to foboot
This is the beginning of having SPI. Also add a new two-stage pipeline. Signed-off-by: Sean Cross <sean@xobs.io>
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@ -20,6 +20,7 @@ from litex.soc.integration import SoCCore
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from litex.soc.integration.builder import Builder
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from litex.soc.integration.builder import Builder
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from litex.soc.integration.soc_core import csr_map_update
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from litex.soc.integration.soc_core import csr_map_update
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.spi import SPIMaster
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from valentyusb import usbcore
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from valentyusb import usbcore
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from valentyusb.usbcore import io as usbio
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from valentyusb.usbcore import io as usbio
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@ -215,7 +216,7 @@ class Platform(LatticePlatform):
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for i in range(len(self.toolchain.nextpnr_yosys_template)):
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for i in range(len(self.toolchain.nextpnr_yosys_template)):
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entry = self.toolchain.nextpnr_yosys_template[i]
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entry = self.toolchain.nextpnr_yosys_template[i]
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if "synth_ice40" in entry:
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if "synth_ice40" in entry:
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self.toolchain.nextpnr_yosys_template[i] = entry + " -relut -dffe_min_ce_use 4"
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self.toolchain.nextpnr_yosys_template[i] = entry + " -dsp -relut -dffe_min_ce_use 4"
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def create_programmer(self):
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def create_programmer(self):
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raise ValueError("programming is not supported")
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raise ValueError("programming is not supported")
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@ -228,6 +229,7 @@ class BaseSoC(SoCCore):
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"usb",
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"usb",
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"usb_obuf",
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"usb_obuf",
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"usb_ibuf",
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"usb_ibuf",
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"spi",
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]
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]
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csr_map_update(SoCCore.csr_map, csr_peripherals)
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csr_map_update(SoCCore.csr_map, csr_peripherals)
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@ -241,7 +243,7 @@ class BaseSoC(SoCCore):
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}
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}
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interrupt_map.update(SoCCore.interrupt_map)
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interrupt_map.update(SoCCore.interrupt_map)
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def __init__(self, platform, boot_source="random_rom", **kwargs):
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def __init__(self, platform, boot_source="random_rom", debug=False, **kwargs):
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# Disable integrated RAM as we'll add it later
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# Disable integrated RAM as we'll add it later
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self.integrated_sram_size = 0
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self.integrated_sram_size = 0
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@ -249,6 +251,10 @@ class BaseSoC(SoCCore):
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self.submodules.crg = _CRG(platform)
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self.submodules.crg = _CRG(platform)
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SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, **kwargs)
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SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, **kwargs)
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self.cpu.use_external_variant("vexriscv-2-stage-with-debug.v")
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if debug:
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self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x10)
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# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
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# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
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# free up scarce block RAM.
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# free up scarce block RAM.
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@ -283,6 +289,9 @@ class BaseSoC(SoCCore):
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# pmoda = platform.request("pmoda")
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# pmoda = platform.request("pmoda")
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# pmodb = platform.request("pmodb")
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# pmodb = platform.request("pmodb")
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spi_pads = platform.request("spiflash")
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self.submodules.spi = SPIMaster(spi_pads)
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# Add USB pads
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# Add USB pads
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usb_pads = platform.request("usb")
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usb_pads = platform.request("usb")
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usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
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usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
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@ -318,6 +327,9 @@ def main():
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parser.add_argument(
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parser.add_argument(
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"--spi", help="boot from spi", action="store_true"
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"--spi", help="boot from spi", action="store_true"
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)
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)
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parser.add_argument(
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"--with-debug", help="enable debug support", action="store_true"
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)
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(args, rest) = parser.parse_known_args()
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(args, rest) = parser.parse_known_args()
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if args.rand:
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if args.rand:
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@ -329,8 +341,16 @@ def main():
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elif args.spi:
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elif args.spi:
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boot_source = "spi_rom"
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boot_source = "spi_rom"
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compile_software = False
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compile_software = False
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# if args.with_debug:
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# cpu_variant = "debug"
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# debug = True
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# else:
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# cpu_variant = "min"
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# debug = False
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cpu_variant = "debug"
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debug = True
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soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant="min", boot_source=boot_source)
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soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant=cpu_variant, debug=debug, boot_source=boot_source)
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builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv", compile_software=compile_software)
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builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv", compile_software=compile_software)
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vns = builder.build()
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vns = builder.build()
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soc.do_exit(vns)
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soc.do_exit(vns)
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3683
hw/vexriscv-2-stage-with-debug.v
Normal file
3683
hw/vexriscv-2-stage-with-debug.v
Normal file
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