sw: add spi base
This is taken from fomu-flash, and needs to be adapted. Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
parent
c7632ae8bd
commit
03327067ff
89
sw/include/spi.h
Normal file
89
sw/include/spi.h
Normal file
@ -0,0 +1,89 @@
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#ifndef BB_SPI_H_
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#define BB_SPI_H_
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#include <stdint.h>
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enum spi_state {
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SS_UNCONFIGURED = 0,
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SS_SINGLE,
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SS_DUAL_RX,
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SS_DUAL_TX,
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SS_QUAD_RX,
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SS_QUAD_TX,
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SS_HARDWARE,
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};
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enum spi_type {
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ST_UNCONFIGURED,
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ST_SINGLE,
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ST_DUAL,
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ST_QUAD,
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ST_QPI,
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};
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enum spi_pin {
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SP_MOSI,
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SP_MISO,
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SP_HOLD,
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SP_WP,
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SP_CS,
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SP_CLK,
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SP_D0,
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SP_D1,
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SP_D2,
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SP_D3,
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};
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struct spi_id {
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uint8_t manufacturer_id; // Result from 0x90
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uint8_t device_id; // Result from 0x90
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uint8_t _manufacturer_id; // Result from 0x9f
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uint8_t memory_type; // Result from 0x9f
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uint8_t memory_size; // Result from 0x9f
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uint8_t signature; // Result from 0xab
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uint8_t serial[4]; // Result from 0x4b
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int bytes; // -1 if unknown
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const char *manufacturer;
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const char *model;
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const char *capacity;
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};
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struct ff_spi;
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void spiPause(struct ff_spi *spi);
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void spiBegin(struct ff_spi *spi);
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void spiEnd(struct ff_spi *spi);
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//void spiSingleTx(struct ff_spi *spi, uint8_t out);
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//uint8_t spiSingleRx(struct ff_spi *spi);
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//void spiDualTx(struct ff_spi *spi, uint8_t out);
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//void spiQuadTx(struct ff_spi *spi, uint8_t out);
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void spiCommand(struct ff_spi *spi, uint8_t cmd);
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//uint8_t spiDualRx(struct ff_spi *spi);
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//uint8_t spiQuadRx(struct ff_spi *spi);
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int spiTx(struct ff_spi *spi, uint8_t word);
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uint8_t spiRx(struct ff_spi *spi);
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uint8_t spiReadStatus(struct ff_spi *spi, uint8_t sr);
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void spiWriteStatus(struct ff_spi *spi, uint8_t sr, uint8_t val);
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void spiReadSecurity(struct ff_spi *spi, uint8_t sr, uint8_t security[256]);
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void spiWriteSecurity(struct ff_spi *spi, uint8_t sr, uint8_t security[256]);
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int spiSetType(struct ff_spi *spi, enum spi_type type);
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int spiRead(struct ff_spi *spi, uint32_t addr, uint8_t *data, unsigned int count);
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struct spi_id spiId(struct ff_spi *spi);
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void spiOverrideSize(struct ff_spi *spi, uint32_t new_size);
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//int spi_wait_for_not_busy(struct ff_spi *spi);
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int spiWrite(struct ff_spi *spi, uint32_t addr, const uint8_t *data, unsigned int count);
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uint8_t spiReset(struct ff_spi *spi);
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int spiInit(struct ff_spi *spi);
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void spiHold(struct ff_spi *spi);
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void spiUnhold(struct ff_spi *spi);
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void spiSwapTxRx(struct ff_spi *spi);
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struct ff_spi *spiAlloc(void);
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void spiSetPin(struct ff_spi *spi, enum spi_pin pin, int val);
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void spiFree(struct ff_spi **spi);
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#endif /* BB_SPI_H_ */
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851
sw/src/spi.c
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851
sw/src/spi.c
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@ -0,0 +1,851 @@
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#include <stdint.h>
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#include <stdio.h>
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#include <fcntl.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <string.h>
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#include <stdlib.h>
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#include "spi.h"
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#define gpioSetMode(pin, mode)
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#define gpioWrite(pin, val)
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#define gpioRead(pin)
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enum ff_spi_quirks {
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// There is no separate "Write SR 2" command. Instead,
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// you must write SR2 after writing SR1
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SQ_SR2_FROM_SR1 = (1 << 0),
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// Don't issue a "Write Enable" command prior to writing
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// a status register
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SQ_SKIP_SR_WEL = (1 << 1),
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// Security registers are shifted up by 4 bits
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SQ_SECURITY_NYBBLE_SHIFT = (1 << 2),
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};
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struct ff_spi {
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enum spi_state state;
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enum spi_type type;
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enum spi_type desired_type;
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struct spi_id id;
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enum ff_spi_quirks quirks;
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int size_override;
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struct {
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int clk;
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int d0;
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int d1;
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int d2;
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int d3;
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int wp;
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int hold;
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int cs;
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int miso;
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int mosi;
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} pins;
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};
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static void spi_get_id(struct ff_spi *spi);
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static void spi_set_state(struct ff_spi *spi, enum spi_state state) {
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if (spi->state == state)
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return;
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switch (state) {
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case SS_SINGLE:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_INPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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case SS_DUAL_RX:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_INPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_INPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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case SS_DUAL_TX:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_OUTPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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case SS_QUAD_RX:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_INPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_INPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_INPUT);
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gpioSetMode(spi->pins.wp, PI_INPUT);
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break;
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case SS_QUAD_TX:
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gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK
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gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0#
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gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI
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gpioSetMode(spi->pins.miso, PI_OUTPUT); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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case SS_HARDWARE:
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gpioSetMode(spi->pins.clk, PI_ALT0); // CLK
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gpioSetMode(spi->pins.cs, PI_ALT0); // CE0#
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gpioSetMode(spi->pins.mosi, PI_ALT0); // MOSI
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gpioSetMode(spi->pins.miso, PI_ALT0); // MISO
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gpioSetMode(spi->pins.hold, PI_OUTPUT);
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gpioSetMode(spi->pins.wp, PI_OUTPUT);
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break;
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default:
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fprintf(stderr, "Unrecognized spi state\n");
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return;
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}
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spi->state = state;
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}
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void spiPause(struct ff_spi *spi) {
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(void)spi;
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// usleep(1);
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return;
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}
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void spiBegin(struct ff_spi *spi) {
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spi_set_state(spi, SS_SINGLE);
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if ((spi->type == ST_SINGLE) || (spi->type == ST_DUAL)) {
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gpioWrite(spi->pins.wp, 1);
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gpioWrite(spi->pins.hold, 1);
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}
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gpioWrite(spi->pins.cs, 0);
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}
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void spiEnd(struct ff_spi *spi) {
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(void)spi;
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gpioWrite(spi->pins.cs, 1);
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}
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static uint8_t spiXfer(struct ff_spi *spi, uint8_t out) {
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int bit;
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uint8_t in = 0;
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#if 0
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for (bit = 7; bit >= 0; bit--) {
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if (out & (1 << bit)) {
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gpioWrite(spi->pins.mosi, 1);
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}
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else {
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gpioWrite(spi->pins.mosi, 0);
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}
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gpioWrite(spi->pins.clk, 1);
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spiPause(spi);
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in |= ((!!gpioRead(spi->pins.miso)) << bit);
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gpioWrite(spi->pins.clk, 0);
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spiPause(spi);
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}
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#endif
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return in;
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}
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static void spiSingleTx(struct ff_spi *spi, uint8_t out) {
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spi_set_state(spi, SS_SINGLE);
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spiXfer(spi, out);
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}
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static uint8_t spiSingleRx(struct ff_spi *spi) {
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spi_set_state(spi, SS_SINGLE);
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return spiXfer(spi, 0xff);
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}
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static void spiDualTx(struct ff_spi *spi, uint8_t out) {
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#if 0
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int bit;
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spi_set_state(spi, SS_DUAL_TX);
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for (bit = 7; bit >= 0; bit -= 2) {
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if (out & (1 << (bit - 1))) {
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gpioWrite(spi->pins.d0, 1);
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}
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else {
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gpioWrite(spi->pins.d0, 0);
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}
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if (out & (1 << (bit - 0))) {
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gpioWrite(spi->pins.d1, 1);
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}
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else {
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gpioWrite(spi->pins.d1, 0);
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}
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gpioWrite(spi->pins.clk, 1);
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spiPause(spi);
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gpioWrite(spi->pins.clk, 0);
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spiPause(spi);
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}
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#endif
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}
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static void spiQuadTx(struct ff_spi *spi, uint8_t out) {
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#if 0
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int bit;
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spi_set_state(spi, SS_QUAD_TX);
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for (bit = 7; bit >= 0; bit -= 4) {
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if (out & (1 << (bit - 3))) {
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gpioWrite(spi->pins.d0, 1);
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}
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else {
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gpioWrite(spi->pins.d0, 0);
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}
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if (out & (1 << (bit - 2))) {
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gpioWrite(spi->pins.d1, 1);
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}
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else {
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gpioWrite(spi->pins.d1, 0);
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}
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if (out & (1 << (bit - 1))) {
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gpioWrite(spi->pins.d2, 1);
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}
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else {
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gpioWrite(spi->pins.d2, 0);
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}
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if (out & (1 << (bit - 0))) {
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gpioWrite(spi->pins.d3, 1);
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}
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else {
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gpioWrite(spi->pins.d3, 0);
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}
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gpioWrite(spi->pins.clk, 1);
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spiPause(spi);
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gpioWrite(spi->pins.clk, 0);
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spiPause(spi);
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}
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#endif
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}
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static uint8_t spiDualRx(struct ff_spi *spi) {
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#if 0
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int bit;
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uint8_t in = 0;
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spi_set_state(spi, SS_QUAD_RX);
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for (bit = 7; bit >= 0; bit -= 2) {
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gpioWrite(spi->pins.clk, 1);
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spiPause(spi);
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in |= ((!!gpioRead(spi->pins.d0)) << (bit - 1));
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in |= ((!!gpioRead(spi->pins.d1)) << (bit - 0));
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gpioWrite(spi->pins.clk, 0);
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spiPause(spi);
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}
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return in;
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}
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static uint8_t spiQuadRx(struct ff_spi *spi) {
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int bit;
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uint8_t in = 0;
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spi_set_state(spi, SS_QUAD_RX);
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for (bit = 7; bit >= 0; bit -= 4) {
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gpioWrite(spi->pins.clk, 1);
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spiPause(spi);
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in |= ((!!gpioRead(spi->pins.d0)) << (bit - 3));
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in |= ((!!gpioRead(spi->pins.d1)) << (bit - 2));
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in |= ((!!gpioRead(spi->pins.d2)) << (bit - 1));
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in |= ((!!gpioRead(spi->pins.d3)) << (bit - 0));
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gpioWrite(spi->pins.clk, 0);
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spiPause(spi);
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}
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return in;
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#endif
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}
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int spiTx(struct ff_spi *spi, uint8_t word) {
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switch (spi->type) {
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case ST_SINGLE:
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spiSingleTx(spi, word);
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break;
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case ST_DUAL:
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spiDualTx(spi, word);
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break;
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case ST_QUAD:
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case ST_QPI:
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spiQuadTx(spi, word);
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break;
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default:
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return -1;
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}
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return 0;
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}
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uint8_t spiRx(struct ff_spi *spi) {
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switch (spi->type) {
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case ST_SINGLE:
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return spiSingleRx(spi);
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case ST_DUAL:
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return spiDualRx(spi);
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case ST_QUAD:
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case ST_QPI:
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return spiQuadRx(spi);
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default:
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return 0xff;
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}
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}
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void spiCommand(struct ff_spi *spi, uint8_t cmd) {
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if (spi->type == ST_QPI)
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spiQuadTx(spi, cmd);
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else
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spiSingleTx(spi, cmd);
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}
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uint8_t spiCommandRx(struct ff_spi *spi) {
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if (spi->type == ST_QPI)
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return spiQuadRx(spi);
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else
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return spiSingleRx(spi);
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}
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uint8_t spiReadStatus(struct ff_spi *spi, uint8_t sr) {
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uint8_t val = 0xff;
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switch (sr) {
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case 1:
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spiBegin(spi);
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spiCommand(spi, 0x05);
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val = spiCommandRx(spi);
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spiEnd(spi);
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break;
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case 2:
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spiBegin(spi);
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spiCommand(spi, 0x35);
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val = spiCommandRx(spi);
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spiEnd(spi);
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break;
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case 3:
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spiBegin(spi);
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spiCommand(spi, 0x15);
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val = spiCommandRx(spi);
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spiEnd(spi);
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break;
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default:
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fprintf(stderr, "unrecognized status register: %d\n", sr);
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break;
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}
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return val;
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}
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void spiWriteSecurity(struct ff_spi *spi, uint8_t sr, uint8_t security[256]) {
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if (spi->quirks & SQ_SECURITY_NYBBLE_SHIFT)
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sr <<= 4;
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spiBegin(spi);
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spiCommand(spi, 0x06);
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spiEnd(spi);
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// erase the register
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spiBegin(spi);
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spiCommand(spi, 0x44);
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spiCommand(spi, 0x00); // A23-16
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spiCommand(spi, sr); // A15-8
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spiCommand(spi, 0x00); // A0-7
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spiEnd(spi);
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spi_get_id(spi);
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sleep(1);
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// write enable
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spiBegin(spi);
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spiCommand(spi, 0x06);
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spiEnd(spi);
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spiBegin(spi);
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spiCommand(spi, 0x42);
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spiCommand(spi, 0x00); // A23-16
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spiCommand(spi, sr); // A15-8
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spiCommand(spi, 0x00); // A0-7
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int i;
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for (i = 0; i < 256; i++)
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spiCommand(spi, security[i]);
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spiEnd(spi);
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spi_get_id(spi);
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}
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void spiReadSecurity(struct ff_spi *spi, uint8_t sr, uint8_t security[256]) {
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if (spi->quirks & SQ_SECURITY_NYBBLE_SHIFT)
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sr <<= 4;
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spiBegin(spi);
|
||||
spiCommand(spi, 0x48); // Read security registers
|
||||
spiCommand(spi, 0x00); // A23-16
|
||||
spiCommand(spi, sr); // A15-8
|
||||
spiCommand(spi, 0x00); // A0-7
|
||||
int i;
|
||||
for (i = 0; i < 256; i++)
|
||||
security[i] = spiCommandRx(spi);
|
||||
spiEnd(spi);
|
||||
}
|
||||
|
||||
void spiWriteStatus(struct ff_spi *spi, uint8_t sr, uint8_t val) {
|
||||
|
||||
switch (sr) {
|
||||
case 1:
|
||||
if (!(spi->quirks & SQ_SKIP_SR_WEL)) {
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x06);
|
||||
spiEnd(spi);
|
||||
}
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x50);
|
||||
spiEnd(spi);
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x01);
|
||||
spiCommand(spi, val);
|
||||
spiEnd(spi);
|
||||
break;
|
||||
|
||||
case 2: {
|
||||
uint8_t sr1 = 0x00;
|
||||
if (spi->quirks & SQ_SR2_FROM_SR1)
|
||||
sr1 = spiReadStatus(spi, 1);
|
||||
|
||||
if (!(spi->quirks & SQ_SKIP_SR_WEL)) {
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x06);
|
||||
spiEnd(spi);
|
||||
}
|
||||
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x50);
|
||||
spiEnd(spi);
|
||||
|
||||
spiBegin(spi);
|
||||
if (spi->quirks & SQ_SR2_FROM_SR1) {
|
||||
spiCommand(spi, 0x01);
|
||||
spiCommand(spi, sr1);
|
||||
spiCommand(spi, val);
|
||||
}
|
||||
else {
|
||||
spiCommand(spi, 0x31);
|
||||
spiCommand(spi, val);
|
||||
}
|
||||
spiEnd(spi);
|
||||
break;
|
||||
}
|
||||
|
||||
case 3:
|
||||
if (!(spi->quirks & SQ_SKIP_SR_WEL)) {
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x06);
|
||||
spiEnd(spi);
|
||||
}
|
||||
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x50);
|
||||
spiEnd(spi);
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x11);
|
||||
spiCommand(spi, val);
|
||||
spiEnd(spi);
|
||||
break;
|
||||
|
||||
default:
|
||||
fprintf(stderr, "unrecognized status register: %d\n", sr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
struct spi_id spiId(struct ff_spi *spi) {
|
||||
return spi->id;
|
||||
}
|
||||
|
||||
static void spi_decode_id(struct ff_spi *spi) {
|
||||
|
||||
spi->id.manufacturer = "unknown";
|
||||
spi->id.model = "unknown";
|
||||
spi->id.capacity = "unknown";
|
||||
spi->id.bytes = -1; // unknown
|
||||
|
||||
if (spi->id.manufacturer_id == 0xef) {
|
||||
spi->id.manufacturer = "Winbond";
|
||||
if ((spi->id.memory_type == 0x70)
|
||||
&& (spi->id.memory_size == 0x18)) {
|
||||
spi->id.model = "W25Q128JV";
|
||||
spi->id.capacity = "128 Mbit";
|
||||
spi->id.bytes = 16 * 1024 * 1024;
|
||||
}
|
||||
}
|
||||
|
||||
if (spi->id.manufacturer_id == 0x1f) {
|
||||
spi->id.manufacturer = "Adesto";
|
||||
if ((spi->id.memory_type == 0x86)
|
||||
&& (spi->id.memory_size == 0x01)) {
|
||||
spi->id.model = "AT25SF161";
|
||||
spi->id.capacity = "16 Mbit";
|
||||
spi->id.bytes = 1 * 1024 * 1024;
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void spi_get_id(struct ff_spi *spi) {
|
||||
memset(&spi->id, 0xff, sizeof(spi->id));
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x90); // Read manufacturer ID
|
||||
spiCommand(spi, 0x00); // Dummy byte 1
|
||||
spiCommand(spi, 0x00); // Dummy byte 2
|
||||
spiCommand(spi, 0x00); // Dummy byte 3
|
||||
spi->id.manufacturer_id = spiCommandRx(spi);
|
||||
spi->id.device_id = spiCommandRx(spi);
|
||||
spiEnd(spi);
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x9f); // Read device id
|
||||
spi->id._manufacturer_id = spiCommandRx(spi);
|
||||
spi->id.memory_type = spiCommandRx(spi);
|
||||
spi->id.memory_size = spiCommandRx(spi);
|
||||
spiEnd(spi);
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0xab); // Read electronic signature
|
||||
spiCommand(spi, 0x00); // Dummy byte 1
|
||||
spiCommand(spi, 0x00); // Dummy byte 2
|
||||
spiCommand(spi, 0x00); // Dummy byte 3
|
||||
spi->id.signature = spiCommandRx(spi);
|
||||
spiEnd(spi);
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x4b); // Read unique ID
|
||||
spiCommand(spi, 0x00); // Dummy byte 1
|
||||
spiCommand(spi, 0x00); // Dummy byte 2
|
||||
spiCommand(spi, 0x00); // Dummy byte 3
|
||||
spiCommand(spi, 0x00); // Dummy byte 4
|
||||
spi->id.serial[0] = spiCommandRx(spi);
|
||||
spi->id.serial[1] = spiCommandRx(spi);
|
||||
spi->id.serial[2] = spiCommandRx(spi);
|
||||
spi->id.serial[3] = spiCommandRx(spi);
|
||||
spiEnd(spi);
|
||||
|
||||
spi_decode_id(spi);
|
||||
return;
|
||||
}
|
||||
|
||||
void spiOverrideSize(struct ff_spi *spi, uint32_t size) {
|
||||
spi->size_override = size;
|
||||
|
||||
// If size is 0, re-read the capacity
|
||||
if (!size)
|
||||
spi_decode_id(spi);
|
||||
else
|
||||
spi->id.bytes = size;
|
||||
}
|
||||
|
||||
int spiSetType(struct ff_spi *spi, enum spi_type type) {
|
||||
|
||||
if (spi->type == type)
|
||||
return 0;
|
||||
|
||||
switch (type) {
|
||||
|
||||
case ST_SINGLE:
|
||||
if (spi->type == ST_QPI) {
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0xff); // Exit QPI Mode
|
||||
spiEnd(spi);
|
||||
}
|
||||
spi->type = type;
|
||||
spi_set_state(spi, SS_SINGLE);
|
||||
break;
|
||||
|
||||
case ST_DUAL:
|
||||
if (spi->type == ST_QPI) {
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0xff); // Exit QPI Mode
|
||||
spiEnd(spi);
|
||||
}
|
||||
spi->type = type;
|
||||
spi_set_state(spi, SS_DUAL_TX);
|
||||
break;
|
||||
|
||||
case ST_QUAD:
|
||||
if (spi->type == ST_QPI) {
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0xff); // Exit QPI Mode
|
||||
spiEnd(spi);
|
||||
}
|
||||
|
||||
// Enable QE bit
|
||||
spiWriteStatus(spi, 2, spiReadStatus(spi, 2) | (1 << 1));
|
||||
|
||||
spi->type = type;
|
||||
spi_set_state(spi, SS_QUAD_TX);
|
||||
break;
|
||||
|
||||
case ST_QPI:
|
||||
// Enable QE bit
|
||||
spiWriteStatus(spi, 2, spiReadStatus(spi, 2) | (1 << 1));
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x38); // Enter QPI Mode
|
||||
spiEnd(spi);
|
||||
spi->type = type;
|
||||
spi_set_state(spi, SS_QUAD_TX);
|
||||
break;
|
||||
|
||||
default:
|
||||
fprintf(stderr, "Unrecognized SPI type: %d\n", type);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spiRead(struct ff_spi *spi, uint32_t addr, uint8_t *data, unsigned int count) {
|
||||
|
||||
unsigned int i;
|
||||
|
||||
spiBegin(spi);
|
||||
switch (spi->type) {
|
||||
case ST_SINGLE:
|
||||
case ST_QPI:
|
||||
spiCommand(spi, 0x0b);
|
||||
break;
|
||||
case ST_DUAL:
|
||||
spiCommand(spi, 0x3b);
|
||||
break;
|
||||
case ST_QUAD:
|
||||
spiCommand(spi, 0x6b);
|
||||
break;
|
||||
default:
|
||||
fprintf(stderr, "unrecognized spi mode\n");
|
||||
spiEnd(spi);
|
||||
return 1;
|
||||
}
|
||||
spiCommand(spi, addr >> 16);
|
||||
spiCommand(spi, addr >> 8);
|
||||
spiCommand(spi, addr >> 0);
|
||||
spiCommand(spi, 0x00);
|
||||
for (i = 0; i < count; i++) {
|
||||
if ((i & 0x3fff) == 0) {
|
||||
printf("\rReading @ %06x / %06x", i, count);
|
||||
fflush(stdout);
|
||||
}
|
||||
data[i] = spiRx(spi);
|
||||
}
|
||||
printf("\rReading @ %06x / %06x Done\n", i, count);
|
||||
|
||||
spiEnd(spi);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int spi_wait_for_not_busy(struct ff_spi *spi) {
|
||||
uint8_t sr1;
|
||||
sr1 = spiReadStatus(spi, 1);
|
||||
|
||||
do {
|
||||
sr1 = spiReadStatus(spi, 1);
|
||||
} while (sr1 & (1 << 0));
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spiSwapTxRx(struct ff_spi *spi) {
|
||||
int tmp = spi->pins.mosi;
|
||||
spi->pins.mosi = spi->pins.miso;
|
||||
spi->pins.miso = tmp;
|
||||
spiSetType(spi, ST_SINGLE);
|
||||
spi->state = SS_UNCONFIGURED;
|
||||
spi_set_state(spi, SS_SINGLE);
|
||||
}
|
||||
|
||||
int spiWrite(struct ff_spi *spi, uint32_t addr, const uint8_t *data, unsigned int count) {
|
||||
|
||||
unsigned int i;
|
||||
|
||||
if (addr & 0xff) {
|
||||
fprintf(stderr, "Error: Target address is not page-aligned to 256 bytes\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
// Erase all applicable blocks
|
||||
uint32_t erase_addr;
|
||||
for (erase_addr = 0; erase_addr < count; erase_addr += 32768) {
|
||||
printf("\rErasing @ %06x / %06x", erase_addr, count);
|
||||
fflush(stdout);
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x06);
|
||||
spiEnd(spi);
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x52);
|
||||
spiCommand(spi, erase_addr >> 16);
|
||||
spiCommand(spi, erase_addr >> 8);
|
||||
spiCommand(spi, erase_addr >> 0);
|
||||
spiEnd(spi);
|
||||
|
||||
spi_wait_for_not_busy(spi);
|
||||
}
|
||||
printf(" Done\n");
|
||||
|
||||
uint8_t write_cmd;
|
||||
switch (spi->type) {
|
||||
case ST_DUAL:
|
||||
fprintf(stderr, "dual writes are broken -- need to temporarily set SINGLE mode\n");
|
||||
return 1;
|
||||
case ST_SINGLE:
|
||||
case ST_QPI:
|
||||
write_cmd = 0x02;
|
||||
break;
|
||||
case ST_QUAD:
|
||||
write_cmd = 0x32;
|
||||
break;
|
||||
default:
|
||||
fprintf(stderr, "unrecognized spi mode\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
int total = count;
|
||||
while (count) {
|
||||
printf("\rProgramming @ %06x / %06x", addr, total);
|
||||
fflush(stdout);
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x06);
|
||||
spiEnd(spi);
|
||||
|
||||
uint8_t sr1 = spiReadStatus(spi, 1);
|
||||
if (!(sr1 & (1 << 1)))
|
||||
fprintf(stderr, "error: write-enable latch (WEL) not set, write will probably fail\n");
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, write_cmd);
|
||||
spiCommand(spi, addr >> 16);
|
||||
spiCommand(spi, addr >> 8);
|
||||
spiCommand(spi, addr >> 0);
|
||||
for (i = 0; (i < count) && (i < 256); i++)
|
||||
spiTx(spi, *data++);
|
||||
spiEnd(spi);
|
||||
count -= i;
|
||||
addr += i;
|
||||
spi_wait_for_not_busy(spi);
|
||||
}
|
||||
printf("\rProgramming @ %06x / %06x", addr, total);
|
||||
printf(" Done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8_t spiReset(struct ff_spi *spi) {
|
||||
// XXX You should check the "Ready" bit before doing this!
|
||||
|
||||
// Shift to QPI mode, then back to Single mode, to ensure
|
||||
// we're actually in Single mode.
|
||||
spiSetType(spi, ST_QPI);
|
||||
spiSetType(spi, ST_SINGLE);
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x66); // "Enable Reset" command
|
||||
spiEnd(spi);
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0x99); // "Reset Device" command
|
||||
spiEnd(spi);
|
||||
|
||||
usleep(30);
|
||||
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0xab); // "Resume from Deep Power-Down" command
|
||||
spiEnd(spi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spiInit(struct ff_spi *spi) {
|
||||
spi->state = SS_UNCONFIGURED;
|
||||
spi->type = ST_UNCONFIGURED;
|
||||
|
||||
// Reset the SPI flash, which will return it to SPI mode even
|
||||
// if it's in QPI mode.
|
||||
spiReset(spi);
|
||||
|
||||
spiSetType(spi, ST_SINGLE);
|
||||
|
||||
// Have the SPI flash pay attention to us
|
||||
gpioWrite(spi->pins.hold, 1);
|
||||
|
||||
// Disable WP
|
||||
gpioWrite(spi->pins.wp, 1);
|
||||
|
||||
spi_get_id(spi);
|
||||
|
||||
spi->quirks |= SQ_SR2_FROM_SR1;
|
||||
// if (spi->id.manufacturer_id == 0x1f)
|
||||
if (spi->id.manufacturer_id == 0xef)
|
||||
spi->quirks |= SQ_SKIP_SR_WEL | SQ_SECURITY_NYBBLE_SHIFT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct ff_spi *spiAlloc(void) {
|
||||
struct ff_spi *spi = (struct ff_spi *)malloc(sizeof(struct ff_spi));
|
||||
memset(spi, 0, sizeof(*spi));
|
||||
return spi;
|
||||
}
|
||||
|
||||
void spiSetPin(struct ff_spi *spi, enum spi_pin pin, int val) {
|
||||
switch (pin) {
|
||||
case SP_MOSI: spi->pins.mosi = val; break;
|
||||
case SP_MISO: spi->pins.miso = val; break;
|
||||
case SP_HOLD: spi->pins.hold = val; break;
|
||||
case SP_WP: spi->pins.wp = val; break;
|
||||
case SP_CS: spi->pins.cs = val; break;
|
||||
case SP_CLK: spi->pins.clk = val; break;
|
||||
case SP_D0: spi->pins.d0 = val; break;
|
||||
case SP_D1: spi->pins.d1 = val; break;
|
||||
case SP_D2: spi->pins.d2 = val; break;
|
||||
case SP_D3: spi->pins.d3 = val; break;
|
||||
default: fprintf(stderr, "unrecognized pin: %d\n", pin); break;
|
||||
}
|
||||
}
|
||||
|
||||
void spiHold(struct ff_spi *spi) {
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0xb9);
|
||||
spiEnd(spi);
|
||||
}
|
||||
void spiUnhold(struct ff_spi *spi) {
|
||||
spiBegin(spi);
|
||||
spiCommand(spi, 0xab);
|
||||
spiEnd(spi);
|
||||
}
|
||||
|
||||
void spiFree(struct ff_spi **spi) {
|
||||
if (!spi)
|
||||
return;
|
||||
if (!*spi)
|
||||
return;
|
||||
|
||||
spi_set_state(*spi, SS_HARDWARE);
|
||||
free(*spi);
|
||||
*spi = NULL;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user