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sw: update to latest generated files

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Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-04-02 18:11:25 +08:00
parent dbc0f81715
commit 85b6d75882
2 changed files with 30 additions and 3 deletions
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30
sw/include/generated/csr.h
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@ -93,6 +93,36 @@ static inline void reboot_ctrl_write(unsigned char value) {
csr_writel(value, 0xe0005800); csr_writel(value, 0xe0005800);
} }
/* rgb */
#define CSR_RGB_BASE 0xe0006000
#define CSR_RGB_DAT_ADDR 0xe0006000
#define CSR_RGB_DAT_SIZE 1
static inline unsigned char rgb_dat_read(void) {
unsigned char r = csr_readl(0xe0006000);
return r;
}
static inline void rgb_dat_write(unsigned char value) {
csr_writel(value, 0xe0006000);
}
#define CSR_RGB_ADDR_ADDR 0xe0006004
#define CSR_RGB_ADDR_SIZE 1
static inline unsigned char rgb_addr_read(void) {
unsigned char r = csr_readl(0xe0006004);
return r;
}
static inline void rgb_addr_write(unsigned char value) {
csr_writel(value, 0xe0006004);
}
#define CSR_RGB_CTRL_ADDR 0xe0006008
#define CSR_RGB_CTRL_SIZE 1
static inline unsigned char rgb_ctrl_read(void) {
unsigned char r = csr_readl(0xe0006008);
return r;
}
static inline void rgb_ctrl_write(unsigned char value) {
csr_writel(value, 0xe0006008);
}
/* timer0 */ /* timer0 */
#define CSR_TIMER0_BASE 0xe0002800 #define CSR_TIMER0_BASE 0xe0002800
#define CSR_TIMER0_LOAD_ADDR 0xe0002800 #define CSR_TIMER0_LOAD_ADDR 0xe0002800

3
sw/include/generated/mem.h
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@ -1,9 +1,6 @@
#ifndef __GENERATED_MEM_H #ifndef __GENERATED_MEM_H
#define __GENERATED_MEM_H #define __GENERATED_MEM_H
#define VEXRISCV_DEBUG_BASE 0xf00f0000
#define VEXRISCV_DEBUG_SIZE 0x00000010
#define SRAM_BASE 0x10000000 #define SRAM_BASE 0x10000000
#define SRAM_SIZE 0x00020000 #define SRAM_SIZE 0x00020000