fa23-si/talk.md
Sean Cross 86a661f686 slight reworking
Signed-off-by: Sean Cross <sean@xobs.io>
2023-04-08 14:44:52 +08:00

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Markdown

- [The State of Open Silicon](#the-state-of-open-silicon)
- [Talk Outline](#talk-outline)
- [About Me](#about-me)
- [What does it mean for silicon to be "Open"?](#what-does-it-mean-for-silicon-to-be-open)
- [Levels of "open"](#levels-of-open)
- [Parts of chip design](#parts-of-chip-design)
- [Process Design Kit](#process-design-kit)
- [Intellectual Property / Libraries](#intellectual-property--libraries)
- [Digital design (In The Beginning)](#digital-design-in-the-beginning)
- [Digital logic overview (Today)](#digital-logic-overview-today)
- [How can we use standard cells?](#how-can-we-use-standard-cells)
- [Tooling](#tooling)
- [End-to-end runs take weeks or months](#end-to-end-runs-take-weeks-or-months)
- [Method to tape out](#method-to-tape-out)
- [Where are we now (in open source)?](#where-are-we-now-in-open-source)
- [Things are looking pretty good](#things-are-looking-pretty-good)
- [End-to-end tool flow possible](#end-to-end-tool-flow-possible)
- [Open PDKs](#open-pdks)
- [Available IP](#available-ip)
- [Standard cells](#standard-cells)
- [What about tooling?](#what-about-tooling)
- [Hardware synthesis](#hardware-synthesis)
- [High level languages](#high-level-languages)
- [Floorplanning, Placement, Routing](#floorplanning-placement-routing)
- [Power and Clock generation](#power-and-clock-generation)
- [Verification](#verification)
- [What about taping out chips?](#what-about-taping-out-chips)
- [What can't we do today?](#what-cant-we-do-today)
- [Memories are still hard](#memories-are-still-hard)
- [Nonvolatile storage is still hard](#nonvolatile-storage-is-still-hard)
- [Analogue IP is still difficult](#analogue-ip-is-still-difficult)
- [Where are we going from here?](#where-are-we-going-from-here)
- [Improved languages](#improved-languages)
- [Improved memories](#improved-memories)
- [Better inference](#better-inference)
- [More analogue IP](#more-analogue-ip)
- [Getting involved!](#getting-involved)
# The State of Open Silicon
# Talk Outline
- What does it mean to be "open"?
- What can we do today?
- What can't we do today?
- Where can we go from here?
# About Me
# What does it mean for silicon to be "Open"?
## Levels of "open"
1. Manuals available
2. Source available
3. GDSII available
## Parts of chip design
1. PDKs
2. IP
3. Tooling
4. Method to tape out
## Process Design Kit
- <https://skywater-pdk.readthedocs.io/en/main/_images/metal_stack.svg>
- Process design kits (PDKs) are closed and under NDA
- Mostly just a blank canvas
## Intellectual Property / Libraries
- Memories
- IO blocks
- Standard cells
## Digital design (In The Beginning)
- [Picture of Z80 or 6502]
- Magic
- [Picture of Siliwiz]
## Digital logic overview (Today)
- Standard cells
- Basic boolean logic
## How can we use standard cells?
- Manual synthesis
- Automated synthesis
Almost all code is automatically synthesized from source code!
[Example of live generation of cells]
## Tooling
- Synthesis
- Power generation
- Clock tree
- Place and route
- Verification
- **Industry tools cost $1mm plus per seat**
## End-to-end runs take weeks or months
- Specialized tooling requires specialized engineers
- Large separation between digital designers and tapeout
## Method to tape out
- Shuttle runs
- Full wafer
- Turnaround time is in months
# Where are we now (in open source)?
## Things are looking pretty good
## End-to-end tool flow possible
- Open tooling, open PDK
- Chips have been produced using this flow
- Digital logic is very doable
## Open PDKs
- Real PDKs
- SKY130
- SKY90FD
- GF180MCU
- "Fake" PDKs
- FreePDK45
- ASAP5
## Available IP
- OpenMPW projects
- ADC, LDO, Bandgap, DAC, and more
## Standard cells
- SKY130
- GF180MCU
- OSU
- LibreSilicon
## What about tooling?
## Hardware synthesis
- Yosys (Verilog)
- VHDL
- SystemVerilog
## High level languages
- LiteX [Python]
- SpinalHDL [Scala]
- Clash
These all generate Verilog, and are fully open!
## Floorplanning, Placement, Routing
- OpenROAD is the current gold-standard
- Competitive with closed tools
## Power and Clock generation
- Setup and hold timing validation
- Basic power nets supported
- Straps are generated as expected
## Verification
- Parasitic extraction works
- Layout-versus-Schematics
- Simulation of extracted netlist
- Design Rule Checking
## What about taping out chips?
- Google OpenMPW shuttles
- MPW shuttle runs
# What can't we do today?
## Memories are still hard
- Density is constantly improving
- Expect kilobytes of RAM on a chip
- Compare to megabytes of cache
- A ~4x increase is possible
## Nonvolatile storage is still hard
- No EEPROM or flash
- ReRAM is experimental on SKY130
## Analogue IP is still difficult
- Some tapeouts exist, but documentation is scarce
- Need more integration examples
# Where are we going from here?
## Improved languages
- Type-checking for timing?
- Bus integration
- Documentation generation
## Improved memories
- OpenRAM coming to more processes
## Better inference
## More analogue IP
# Getting involved!
- Siliwiz for raw tapeout
- TinyTapeout
- Write more blogposts
- Give it a try
Thank you!