4.8 KiB
4.8 KiB
- What does it mean for silicon to be "Open"?
- What is the current state of the art?
- Where are we going from here?
- Getting involved!
What does it mean for silicon to be "Open"?
Parts of chip design
- Tooling
- PDKs
- IP
Open tooling
- Industry tools cost $1mm plus per seat
- Process design kits (PDKs) are closed and under NDA
- Tooling includes synthesis, placement, and routing
- Tooling also includes verification, clock generation, and power generation
Manual design (In The Beginning)
- Rubylith
- Magic
- [Picture of Siliwiz]
Digital logic overview
- Boolean values
How can we use standard cells?
- Manual synthesis
- Automated synthesis
Almost all code is automatically synthesized from source code!
Digital design
Source code can be in a Hardware Description Language. For example:
- Verilog
- SystemVerilog
- VHDL
[Example of live generation of cells]
Process Design Kits
- Very low-level logic
- AND
- NOR
- NOT
- Diode
- Tie
Digital logic is, for the most part, a collection of these standard cells!
[Image of standard cells]
What about blackboxes?
- Frequently called "IP"
- Blackboxes allow for more functionality, or higher performance
- Memories, RF, ADC, etc.
- Usually have Verilog models that are non-synthesizable.
- Place-and-route tool wires up the ports
- Blackboxes are how we get analogue!
Place and route
The tool will automatically place cells, and will add wires between them!
Other tools
- Clock generation
- Power generation
- Reset inserters
- Parasitic extraction
- Layout-vs-Schematic
What is the current state of the art?
Things are looking pretty good!
End-to-end tool flow possible!
- Open tooling, open PDK
- Chips have been produced using this flow
- Production is still an issue
Current open PDKs are "ginormous"
- 180nm and 130nm are peak-1999 technology
- Still can do interesting things at 180/130nm!
- "Fake" PDKs exist
Hardware synthesis
- Yosys
- GHDL
Ingests Verilog or VHDL and generates basic netlists
High level languages
- LiteX [Python]
- SpinalHDL [Scala]
- [Rust]
These all geneate Verilog, and are fully open!
Floorplanning, Placement, Routing
- OpenROAD is the current gold-standard
- Compatitive with closed tools
Power and Clock generation
- Setup and hold timing validation
- Basic power nets supported
- Straps are generated as expected
Verification
- Parasitic extraction works
- Layout-versus-Schematics
- Simulation of extracted netlist
- Design Rule Checking
Wide selection of existing chips
- Taped out
- Still being characterized
Large selection of existing IP
- [Picture of MPW list]
Where are we going from here?
More open PDKs
- GF180MCU is relatively new
- ??? PDKs
Improved analogue IP
- Each run adds even more designs
Better IP discoverability
- Indexes of IP cores
Better integration
- Wishbone is standard in open source
- AXI4 is common in industry