talk: initial outline
Signed-off-by: Sean Cross <sean@xobs.io>
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- [What does it mean for silicon to be "Open"?](#what-does-it-mean-for-silicon-to-be-open)
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- [Parts of chip design](#parts-of-chip-design)
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- [Open tooling](#open-tooling)
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- [Manual design (In The Beginning)](#manual-design-in-the-beginning)
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- [Digital logic overview](#digital-logic-overview)
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- [How can we use standard cells?](#how-can-we-use-standard-cells)
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- [Digital design](#digital-design)
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- [Process Design Kits](#process-design-kits)
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- [What about blackboxes?](#what-about-blackboxes)
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- [Place and route](#place-and-route)
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- [Other tools](#other-tools)
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- [What is the current state of the art?](#what-is-the-current-state-of-the-art)
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- [Things are looking pretty good!](#things-are-looking-pretty-good)
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- [End-to-end tool flow possible!](#end-to-end-tool-flow-possible)
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- [Current open PDKs are "ginormous"](#current-open-pdks-are-ginormous)
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- [Hardware synthesis](#hardware-synthesis)
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- [High level languages](#high-level-languages)
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- [Floorplanning, Placement, Routing](#floorplanning-placement-routing)
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- [Power and Clock generation](#power-and-clock-generation)
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- [Verification](#verification)
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- [Wide selection of existing chips](#wide-selection-of-existing-chips)
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- [Large selection of existing IP](#large-selection-of-existing-ip)
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- [Where are we going from here?](#where-are-we-going-from-here)
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- [More open PDKs](#more-open-pdks)
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- [Improved analogue IP](#improved-analogue-ip)
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- [Better IP discoverability](#better-ip-discoverability)
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- [Better integration](#better-integration)
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- [Memories are still hard](#memories-are-still-hard)
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- [Flash is still hard](#flash-is-still-hard)
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- [EEPROM is still hard](#eeprom-is-still-hard)
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- [Exotic, non-digital IP is hard!](#exotic-non-digital-ip-is-hard)
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- [Getting involved!](#getting-involved)
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- [Siliwiz for raw tapeout](#siliwiz-for-raw-tapeout)
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- [TinyTapeout](#tinytapeout)
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- [](#)
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# What does it mean for silicon to be "Open"?
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## Parts of chip design
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* Tooling
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* PDKs
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* IP
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## Open tooling
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* Industry tools cost $1mm plus per seat
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* Process design kits (PDKs) are closed and under NDA
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* Tooling includes synthesis, placement, and routing
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* Tooling also includes verification, clock generation, and power generation
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## Manual design (In The Beginning)
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* Rubylith
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* Magic
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* [Picture of Siliwiz]
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## Digital logic overview
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* Boolean values
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## How can we use standard cells?
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* Manual synthesis
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* Automated synthesis
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Almost all code is automatically synthesized from source code!
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## Digital design
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Source code can be in a Hardware Description Language. For example:
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* Verilog
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* SystemVerilog
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* VHDL
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[Example of live generation of cells]
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## Process Design Kits
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* Very low-level logic
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* AND
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* NOR
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* NOT
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* Diode
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* Tie
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Digital logic is, for the most part, a collection of these standard cells!
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[Image of standard cells]
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## What about blackboxes?
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* Frequently called "IP"
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* Blackboxes allow for more functionality, or higher performance
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* Memories, RF, ADC, etc.
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* Usually have Verilog models that are non-synthesizable.
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* Place-and-route tool wires up the ports
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* Blackboxes are how we get analogue!
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## Place and route
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The tool will automatically place cells, and will add wires between them!
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## Other tools
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* Clock generation
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* Power generation
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* Reset inserters
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* Parasitic extraction
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* Layout-vs-Schematic
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# What is the current state of the art?
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## Things are looking pretty good!
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## End-to-end tool flow possible!
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* Open tooling, open PDK
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* Chips have been produced using this flow
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* Production is still an issue
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## Current open PDKs are "ginormous"
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* 180nm and 130nm are peak-1999 technology
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* Still can do interesting things at 180/130nm!
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* "Fake" PDKs exist
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## Hardware synthesis
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* Yosys
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* GHDL
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Ingests Verilog or VHDL and generates basic netlists
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## High level languages
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* LiteX [Python]
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* SpinalHDL [Scala]
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* [Rust]
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These all geneate Verilog, and are fully open!
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## Floorplanning, Placement, Routing
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* OpenROAD is the current gold-standard
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* Compatitive with closed tools
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## Power and Clock generation
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* Setup and hold timing validation
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* Basic power nets supported
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* Straps are generated as expected
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## Verification
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* Parasitic extraction works
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* Layout-versus-Schematics
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* Simulation of extracted netlist
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* Design Rule Checking
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## Wide selection of existing chips
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* Taped out
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* Still being characterized
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## Large selection of existing IP
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* [Picture of MPW list]
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# Where are we going from here?
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## More open PDKs
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* GF180MCU is relatively new
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* ??? PDKs
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## Improved analogue IP
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* Each run adds even more designs
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## Better IP discoverability
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* Indexes of IP cores
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## Better integration
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* Wishbone is standard in open source
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* AXI4 is common in industry
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## Memories are still hard
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## Flash is still hard
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## EEPROM is still hard
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## Exotic, non-digital IP is hard!
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# Getting involved!
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## Siliwiz for raw tapeout
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## TinyTapeout
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##
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