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Signed-off-by: Sean Cross <sean@xobs.io>
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index.html
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<section> <section>
<h2>Outline</h2> <h2>Outline</h2>
<ol> <ol>
<li>What is Open Silicon?</li> <li>What does it mean to be "open"?</li>
<li>What can we do now?</li> <li>What can we do today?</li>
<li>What's to come?</li> <li>What can't we do today?</li>
<li>Where can we go from here?</li>
</ol> </ol>
</section> </section>
<section> <section>
<h2>About Me</h2>
</section>
<section> <section>
<h2>What is Open Silicon?</h2> <section>
<h2>What does it mean to be "open"?</h2>
<ol> <ol>
<li>A process design kit that can be manufactured</li> <li>Manuals available</li>
<li>An open set of tools to go from design to production</li> <li>Source available</li>
<li>Easy access to a silicon foundary for small-volume production</li> <li>Tooling available</li>
<li>GDSII available</li>
</ol> </ol>
</section> </section>
<section>
<h2>Parts of chip design</h2>
<ul>
<li>Process Design Kit (PDK)</li>
<li>IP (libraries)</li>
<li>Tooling</li>
<li>Fabrication method</li>
</ul>
</section>
<section>
<h2>Process Design Kit</h2>
<ul>
<li>https://skywater-pdk.readthedocs.io/en/main/_images/metal_stack.svg</li>
<li>Process design kits (PDKs) are closed and under NDA</li>
<li>Mostly just a blank canvas</li>
</ul>
</section>
<section>
<h2>IP / Libraries</h2>
<ul>
<li>Memories</li>
<li>IO blocks</li>
<li>Standard cells</li>
</ul>
</section>
<section>
<h2>Digital design (In The Beginning)</h2>
<ul>
<li>[Picture of Z80 or 6502]</li>
<li>Magic</li>
<li>[Picture of Siliwiz]</li>
</ul>
</section>
<section>
<h2>Digital logic overview (Today)</h2>
<ul>
<li>Standard cells</li>
<li>Basic boolean logic</li>
</ul>
</section>
<section>
<h2>How can we use standard cells?</h2>
<ul>
<li>Manual synthesis</li>
<li>Automated synthesis</li>
</ul>
Almost all code is automatically synthesized from source code!
[Example of live generation of cells]
</section>
<section>
<h2>Tooling</h2>
<ul>
<li>Synthesis</li>
<li>Power generation</li>
<li>Clock tree</li>
<li>Place and route</li>
<li>Verification</li>
<li><strong>Industry tools cost $1mm plus per seat</strong></li>
</ul>
</section>
<section>
<h2>Method to tape out</h2>
<ul>
<li>Shuttle runs</li>
<li>Full wafer</li>
<li>Turnaround time is in months</li>
</ul>
</section>
</section> </section>
<section> <section>
<section> <section>
<h2>The State of the Toolchin</h2> <h2>Where are we now (in open source)?</h2>
</section> </section>
<section> <section>
<h2>Process Design Kits (PDKs)</h2> <h2>Things are looking pretty good!</h2>
</section>
<section>
<h2>Open PDKs</h2>
<ul>
<li>Real PDKs</li>
<ul>
<li>SKY130</li>
<li>SKY90FD</li>
<li>GF180MCU </li>
</ul>
<li>"Fake" PDKs</li>
<ul>
<li>FreePDK45</li>
<li>ASAP5 </li>
</ul>
</ul>
</section>
<section>
<h2>Available IP</h2>
Projects that have been taped out
<ul>
<li>ADC</li>
<li>LDO</li>
<li>Bandgap</li>
<li>DAC</li>
<li>...more...</li>
</ul>
</section>
<section>
<h2>Standard cells</h2>
<ul> <ul>
<li>SKY130</li> <li>SKY130</li>
<li>GF180MCU</li> <li>GF180MCU</li>
<li><small>FreePDK</small></li> <li>OSU</li>
<li>LibreSilicon</li>
</ul>
</section>
<section>
<h2>Simulation</h2>
<ul>
<li>GHDL</li>
<li>Icarus Verilog</li>
<li>Verilator</li>
<li>GTKWave</li>
</ul>
</section>
<section>
<h2>Design Synthesis</h2>
<ul>
<li>Verilog / VHDL -> Verilog</li>
</ul>
</section>
<section>
<h2>Place and Route</h2>
</section>
<section>
<h2>Direct Cell Design</h2>
<ul>
<li>Magic</li>
<li>KLayout</li>
</ul>
</section>
</section>
<section>
<section>
<h1>What can we do now?</h1>
</section>
<section>
<h2>Examples of 130 nm</h2>
<ul>
<li>Gamecube CPU "Gekko": 43 mm<sup>2</sup> (2001)</li>
</ul>
<h2>Examples of 180 nm</h2>
<ul>
<li>Playstation 2 "Emotion Engine"</li>
</ul> </ul>
</section> </section>
</section> </section>

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- [The State of Open Silicon](#the-state-of-open-silicon)
- [Talk Outline](#talk-outline)
- [About Me](#about-me)
- [What does it mean for silicon to be "Open"?](#what-does-it-mean-for-silicon-to-be-open) - [What does it mean for silicon to be "Open"?](#what-does-it-mean-for-silicon-to-be-open)
- [Levels of "open"](#levels-of-open)
- [Parts of chip design](#parts-of-chip-design) - [Parts of chip design](#parts-of-chip-design)
- [Open tooling](#open-tooling) - [Process Design Kit](#process-design-kit)
- [Manual design (In The Beginning)](#manual-design-in-the-beginning) - [Intellectual Property / Libraries](#intellectual-property--libraries)
- [Digital logic overview](#digital-logic-overview) - [Digital design (In The Beginning)](#digital-design-in-the-beginning)
- [Digital logic overview (Today)](#digital-logic-overview-today)
- [How can we use standard cells?](#how-can-we-use-standard-cells) - [How can we use standard cells?](#how-can-we-use-standard-cells)
- [Digital design](#digital-design) - [Tooling](#tooling)
- [Process Design Kits](#process-design-kits) - [End-to-end runs take weeks or months](#end-to-end-runs-take-weeks-or-months)
- [What about blackboxes?](#what-about-blackboxes) - [Method to tape out](#method-to-tape-out)
- [Place and route](#place-and-route) - [Where are we now (in open source)?](#where-are-we-now-in-open-source)
- [Other tools](#other-tools) - [Things are looking pretty good](#things-are-looking-pretty-good)
- [What is the current state of the art?](#what-is-the-current-state-of-the-art) - [End-to-end tool flow possible](#end-to-end-tool-flow-possible)
- [Things are looking pretty good!](#things-are-looking-pretty-good) - [Open PDKs](#open-pdks)
- [End-to-end tool flow possible!](#end-to-end-tool-flow-possible) - [Available IP](#available-ip)
- [Current open PDKs are "ginormous"](#current-open-pdks-are-ginormous) - [Standard cells](#standard-cells)
- [What about tooling?](#what-about-tooling)
- [Hardware synthesis](#hardware-synthesis) - [Hardware synthesis](#hardware-synthesis)
- [High level languages](#high-level-languages) - [High level languages](#high-level-languages)
- [Floorplanning, Placement, Routing](#floorplanning-placement-routing) - [Floorplanning, Placement, Routing](#floorplanning-placement-routing)
- [Power and Clock generation](#power-and-clock-generation) - [Power and Clock generation](#power-and-clock-generation)
- [Verification](#verification) - [Verification](#verification)
- [Wide selection of existing chips](#wide-selection-of-existing-chips) - [What about taping out chips?](#what-about-taping-out-chips)
- [Large selection of existing IP](#large-selection-of-existing-ip) - [What can't we do today?](#what-cant-we-do-today)
- [Where are we going from here?](#where-are-we-going-from-here)
- [More open PDKs](#more-open-pdks)
- [Improved analogue IP](#improved-analogue-ip)
- [Better IP discoverability](#better-ip-discoverability)
- [Better integration](#better-integration)
- [Memories are still hard](#memories-are-still-hard) - [Memories are still hard](#memories-are-still-hard)
- [Flash is still hard](#flash-is-still-hard) - [Nonvolatile storage is still hard](#nonvolatile-storage-is-still-hard)
- [EEPROM is still hard](#eeprom-is-still-hard) - [Current PDKs are large nodes](#current-pdks-are-large-nodes)
- [Exotic, non-digital IP is hard!](#exotic-non-digital-ip-is-hard) - [Analogue IP is still difficult](#analogue-ip-is-still-difficult)
- [Where are we going from here?](#where-are-we-going-from-here)
- [Improved languages](#improved-languages)
- [Improved memories](#improved-memories)
- [Better inference](#better-inference)
- [More analogue IP](#more-analogue-ip)
- [Getting involved!](#getting-involved) - [Getting involved!](#getting-involved)
- [Siliwiz for raw tapeout](#siliwiz-for-raw-tapeout)
- [TinyTapeout](#tinytapeout) # The State of Open Silicon
- [](#)
# Talk Outline
- What does it mean to be "open"?
- What can we do today?
- What can't we do today?
- Where can we go from here?
# About Me
# What does it mean for silicon to be "Open"? # What does it mean for silicon to be "Open"?
## Levels of "open"
1. Manuals available
2. Source available
3. GDSII available
## Parts of chip design ## Parts of chip design
* Tooling 1. PDKs
* PDKs 2. IP
* IP 3. Tooling
4. Method to tape out
## Open tooling ## Process Design Kit
* Industry tools cost $1mm plus per seat - <https://skywater-pdk.readthedocs.io/en/main/_images/metal_stack.svg>
* Process design kits (PDKs) are closed and under NDA - Process design kits (PDKs) are closed and under NDA
* Tooling includes synthesis, placement, and routing - Mostly just a blank canvas
* Tooling also includes verification, clock generation, and power generation
## Manual design (In The Beginning) ## Intellectual Property / Libraries
* Rubylith - Memories
* Magic - IO blocks
* [Picture of Siliwiz] - Standard cells
## Digital logic overview ## Digital design (In The Beginning)
* Boolean values - [Picture of Z80 or 6502]
- Magic
- [Picture of Siliwiz]
## Digital logic overview (Today)
- Standard cells
- Basic boolean logic
## How can we use standard cells? ## How can we use standard cells?
* Manual synthesis - Manual synthesis
* Automated synthesis - Automated synthesis
Almost all code is automatically synthesized from source code! Almost all code is automatically synthesized from source code!
## Digital design
Source code can be in a Hardware Description Language. For example:
* Verilog
* SystemVerilog
* VHDL
[Example of live generation of cells] [Example of live generation of cells]
## Process Design Kits ## Tooling
* Very low-level logic - Synthesis
* AND - Power generation
* NOR - Clock tree
* NOT - Place and route
* Diode - Verification
* Tie - **Industry tools cost $1mm plus per seat**
Digital logic is, for the most part, a collection of these standard cells! ## End-to-end runs take weeks or months
[Image of standard cells] - Specialized tooling requires specialized engineers
- Large separation between digital designers and tapeout
## What about blackboxes? ## Method to tape out
* Frequently called "IP" - Shuttle runs
* Blackboxes allow for more functionality, or higher performance - Full wafer
* Memories, RF, ADC, etc. - Turnaround time is in months
* Usually have Verilog models that are non-synthesizable.
* Place-and-route tool wires up the ports
* Blackboxes are how we get analogue!
## Place and route # Where are we now (in open source)?
The tool will automatically place cells, and will add wires between them! ## Things are looking pretty good
## Other tools ## End-to-end tool flow possible
* Clock generation - Open tooling, open PDK
* Power generation - Chips have been produced using this flow
* Reset inserters - Digital logic is very doable
* Parasitic extraction
* Layout-vs-Schematic
# What is the current state of the art? ## Open PDKs
## Things are looking pretty good! - Real PDKs
- SKY130
- SKY90FD
- GF180MCU
- "Fake" PDKs
- FreePDK45
- ASAP5
## End-to-end tool flow possible! ## Available IP
* Open tooling, open PDK - OpenMPW projects
* Chips have been produced using this flow - ADC, LDO, Bandgap, DAC, and more
* Production is still an issue
## Current open PDKs are "ginormous" ## Standard cells
* 180nm and 130nm are peak-1999 technology - SKY130
* Still can do interesting things at 180/130nm! - GF180MCU
* "Fake" PDKs exist - OSU
- LibreSilicon
## What about tooling?
## Hardware synthesis ## Hardware synthesis
* Yosys - Yosys (Verilog)
* GHDL - VHDL
- SystemVerilog
Ingests Verilog or VHDL and generates basic netlists
## High level languages ## High level languages
* LiteX [Python] - LiteX [Python]
* SpinalHDL [Scala] - SpinalHDL [Scala]
* [Rust] - Clash
These all geneate Verilog, and are fully open! These all generate Verilog, and are fully open!
## Floorplanning, Placement, Routing ## Floorplanning, Placement, Routing
* OpenROAD is the current gold-standard - OpenROAD is the current gold-standard
* Compatitive with closed tools - Competitive with closed tools
## Power and Clock generation ## Power and Clock generation
* Setup and hold timing validation - Setup and hold timing validation
* Basic power nets supported - Basic power nets supported
* Straps are generated as expected - Straps are generated as expected
## Verification ## Verification
* Parasitic extraction works - Parasitic extraction works
* Layout-versus-Schematics - Layout-versus-Schematics
* Simulation of extracted netlist - Simulation of extracted netlist
* Design Rule Checking - Design Rule Checking
## Wide selection of existing chips ## What about taping out chips?
* Taped out - Google OpenMPW shuttles
* Still being characterized - MPW shuttle runs
## Large selection of existing IP # What can't we do today?
* [Picture of MPW list]
# Where are we going from here?
## More open PDKs
* GF180MCU is relatively new
* ??? PDKs
## Improved analogue IP
* Each run adds even more designs
## Better IP discoverability
* Indexes of IP cores
## Better integration
* Wishbone is standard in open source
* AXI4 is common in industry
## Memories are still hard ## Memories are still hard
## Flash is still hard - Density is constantly improving
- Expect kilobytes of RAM on a chip
- Compare to megabytes of cache
- A ~4x increase is possible
## EEPROM is still hard ## Nonvolatile storage is still hard
## Exotic, non-digital IP is hard! - No EEPROM or flash
- ReRAM is experimental on SKY130
## Current PDKs are large nodes
- 180nm was cutting edge in 1999
## Analogue IP is still difficult
- Some tapeouts exist, but documentation is scarce
- Need more integration examples
# Where are we going from here?
## Improved languages
- Type-checking for timing?
- Bus integration
- Documentation generation
## Improved memories
- OpenRAM coming to more processes
## Better inference
## More analogue IP
# Getting involved! # Getting involved!
## Siliwiz for raw tapeout - Siliwiz for raw tapeout
- TinyTapeout
- Write more blogposts
- Give it a try
## TinyTapeout Thank you!
##