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Outline

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  1. What is Open Silicon?
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  2. What can we do now?
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  3. What's to come?
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  4. What does it mean to be "open"?
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  5. What can we do today?
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  6. What can't we do today?
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  7. Where can we go from here?
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About Me

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What is Open Silicon?

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What does it mean to be "open"?

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  1. A process design kit that can be manufactured
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  2. An open set of tools to go from design to production
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  3. Easy access to a silicon foundary for small-volume production
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  4. Manuals available
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  5. Source available
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  6. Tooling available
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  7. GDSII available
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Parts of chip design

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Process Design Kit

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IP / Libraries

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Digital design (In The Beginning)

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Digital logic overview (Today)

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How can we use standard cells?

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Tooling

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Method to tape out

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The State of the Toolchin

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Where are we now (in open source)?

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Process Design Kits (PDKs)

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Things are looking pretty good!

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Open PDKs

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Available IP

+ Projects that have been taped out + +
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Standard cells

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Simulation

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Design Synthesis

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Place and Route

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Direct Cell Design

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What can we do now?

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Examples of 130 nm

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Examples of 180 nm

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diff --git a/talk.md b/talk.md index 81e44fa..97f3e3b 100644 --- a/talk.md +++ b/talk.md @@ -1,206 +1,236 @@ +- [The State of Open Silicon](#the-state-of-open-silicon) +- [Talk Outline](#talk-outline) +- [About Me](#about-me) - [What does it mean for silicon to be "Open"?](#what-does-it-mean-for-silicon-to-be-open) + - [Levels of "open"](#levels-of-open) - [Parts of chip design](#parts-of-chip-design) - - [Open tooling](#open-tooling) - - [Manual design (In The Beginning)](#manual-design-in-the-beginning) - - [Digital logic overview](#digital-logic-overview) + - [Process Design Kit](#process-design-kit) + - [Intellectual Property / Libraries](#intellectual-property--libraries) + - [Digital design (In The Beginning)](#digital-design-in-the-beginning) + - [Digital logic overview (Today)](#digital-logic-overview-today) - [How can we use standard cells?](#how-can-we-use-standard-cells) - - [Digital design](#digital-design) - - [Process Design Kits](#process-design-kits) - - [What about blackboxes?](#what-about-blackboxes) - - [Place and route](#place-and-route) - - [Other tools](#other-tools) -- [What is the current state of the art?](#what-is-the-current-state-of-the-art) - - [Things are looking pretty good!](#things-are-looking-pretty-good) - - [End-to-end tool flow possible!](#end-to-end-tool-flow-possible) - - [Current open PDKs are "ginormous"](#current-open-pdks-are-ginormous) + - [Tooling](#tooling) + - [End-to-end runs take weeks or months](#end-to-end-runs-take-weeks-or-months) + - [Method to tape out](#method-to-tape-out) +- [Where are we now (in open source)?](#where-are-we-now-in-open-source) + - [Things are looking pretty good](#things-are-looking-pretty-good) + - [End-to-end tool flow possible](#end-to-end-tool-flow-possible) + - [Open PDKs](#open-pdks) + - [Available IP](#available-ip) + - [Standard cells](#standard-cells) + - [What about tooling?](#what-about-tooling) - [Hardware synthesis](#hardware-synthesis) - [High level languages](#high-level-languages) - [Floorplanning, Placement, Routing](#floorplanning-placement-routing) - [Power and Clock generation](#power-and-clock-generation) - [Verification](#verification) - - [Wide selection of existing chips](#wide-selection-of-existing-chips) - - [Large selection of existing IP](#large-selection-of-existing-ip) -- [Where are we going from here?](#where-are-we-going-from-here) - - [More open PDKs](#more-open-pdks) - - [Improved analogue IP](#improved-analogue-ip) - - [Better IP discoverability](#better-ip-discoverability) - - [Better integration](#better-integration) + - [What about taping out chips?](#what-about-taping-out-chips) +- [What can't we do today?](#what-cant-we-do-today) - [Memories are still hard](#memories-are-still-hard) - - [Flash is still hard](#flash-is-still-hard) - - [EEPROM is still hard](#eeprom-is-still-hard) - - [Exotic, non-digital IP is hard!](#exotic-non-digital-ip-is-hard) + - [Nonvolatile storage is still hard](#nonvolatile-storage-is-still-hard) + - [Current PDKs are large nodes](#current-pdks-are-large-nodes) + - [Analogue IP is still difficult](#analogue-ip-is-still-difficult) +- [Where are we going from here?](#where-are-we-going-from-here) + - [Improved languages](#improved-languages) + - [Improved memories](#improved-memories) + - [Better inference](#better-inference) + - [More analogue IP](#more-analogue-ip) - [Getting involved!](#getting-involved) - - [Siliwiz for raw tapeout](#siliwiz-for-raw-tapeout) - - [TinyTapeout](#tinytapeout) - - [](#) + +# The State of Open Silicon + +# Talk Outline + +- What does it mean to be "open"? +- What can we do today? +- What can't we do today? +- Where can we go from here? + +# About Me # What does it mean for silicon to be "Open"? +## Levels of "open" + +1. Manuals available +2. Source available +3. GDSII available + ## Parts of chip design -* Tooling -* PDKs -* IP +1. PDKs +2. IP +3. Tooling +4. Method to tape out -## Open tooling +## Process Design Kit -* Industry tools cost $1mm plus per seat -* Process design kits (PDKs) are closed and under NDA -* Tooling includes synthesis, placement, and routing -* Tooling also includes verification, clock generation, and power generation +- +- Process design kits (PDKs) are closed and under NDA +- Mostly just a blank canvas -## Manual design (In The Beginning) +## Intellectual Property / Libraries -* Rubylith -* Magic -* [Picture of Siliwiz] +- Memories +- IO blocks +- Standard cells -## Digital logic overview +## Digital design (In The Beginning) -* Boolean values +- [Picture of Z80 or 6502] +- Magic +- [Picture of Siliwiz] + +## Digital logic overview (Today) + +- Standard cells +- Basic boolean logic ## How can we use standard cells? -* Manual synthesis -* Automated synthesis +- Manual synthesis +- Automated synthesis Almost all code is automatically synthesized from source code! -## Digital design - -Source code can be in a Hardware Description Language. For example: - -* Verilog -* SystemVerilog -* VHDL - [Example of live generation of cells] -## Process Design Kits +## Tooling -* Very low-level logic -* AND -* NOR -* NOT -* Diode -* Tie +- Synthesis +- Power generation +- Clock tree +- Place and route +- Verification +- **Industry tools cost $1mm plus per seat** -Digital logic is, for the most part, a collection of these standard cells! +## End-to-end runs take weeks or months -[Image of standard cells] +- Specialized tooling requires specialized engineers +- Large separation between digital designers and tapeout -## What about blackboxes? +## Method to tape out -* Frequently called "IP" -* Blackboxes allow for more functionality, or higher performance - * Memories, RF, ADC, etc. -* Usually have Verilog models that are non-synthesizable. -* Place-and-route tool wires up the ports -* Blackboxes are how we get analogue! +- Shuttle runs +- Full wafer +- Turnaround time is in months -## Place and route +# Where are we now (in open source)? -The tool will automatically place cells, and will add wires between them! +## Things are looking pretty good -## Other tools +## End-to-end tool flow possible -* Clock generation -* Power generation -* Reset inserters -* Parasitic extraction -* Layout-vs-Schematic +- Open tooling, open PDK +- Chips have been produced using this flow +- Digital logic is very doable -# What is the current state of the art? +## Open PDKs -## Things are looking pretty good! +- Real PDKs + - SKY130 + - SKY90FD + - GF180MCU +- "Fake" PDKs + - FreePDK45 + - ASAP5 -## End-to-end tool flow possible! +## Available IP -* Open tooling, open PDK -* Chips have been produced using this flow -* Production is still an issue +- OpenMPW projects +- ADC, LDO, Bandgap, DAC, and more -## Current open PDKs are "ginormous" +## Standard cells -* 180nm and 130nm are peak-1999 technology - * Still can do interesting things at 180/130nm! -* "Fake" PDKs exist +- SKY130 +- GF180MCU +- OSU +- LibreSilicon + +## What about tooling? ## Hardware synthesis -* Yosys -* GHDL - -Ingests Verilog or VHDL and generates basic netlists +- Yosys (Verilog) + - VHDL + - SystemVerilog ## High level languages -* LiteX [Python] -* SpinalHDL [Scala] -* [Rust] +- LiteX [Python] +- SpinalHDL [Scala] +- Clash -These all geneate Verilog, and are fully open! +These all generate Verilog, and are fully open! ## Floorplanning, Placement, Routing -* OpenROAD is the current gold-standard -* Compatitive with closed tools +- OpenROAD is the current gold-standard +- Competitive with closed tools ## Power and Clock generation -* Setup and hold timing validation -* Basic power nets supported -* Straps are generated as expected +- Setup and hold timing validation +- Basic power nets supported +- Straps are generated as expected ## Verification -* Parasitic extraction works -* Layout-versus-Schematics -* Simulation of extracted netlist -* Design Rule Checking +- Parasitic extraction works +- Layout-versus-Schematics +- Simulation of extracted netlist +- Design Rule Checking -## Wide selection of existing chips +## What about taping out chips? -* Taped out -* Still being characterized +- Google OpenMPW shuttles +- MPW shuttle runs -## Large selection of existing IP - -* [Picture of MPW list] - -# Where are we going from here? - -## More open PDKs - -* GF180MCU is relatively new -* ??? PDKs - -## Improved analogue IP - -* Each run adds even more designs - -## Better IP discoverability - -* Indexes of IP cores - -## Better integration - -* Wishbone is standard in open source -* AXI4 is common in industry +# What can't we do today? ## Memories are still hard -## Flash is still hard +- Density is constantly improving +- Expect kilobytes of RAM on a chip + - Compare to megabytes of cache +- A ~4x increase is possible -## EEPROM is still hard +## Nonvolatile storage is still hard -## Exotic, non-digital IP is hard! +- No EEPROM or flash +- ReRAM is experimental on SKY130 + +## Current PDKs are large nodes + +- 180nm was cutting edge in 1999 + +## Analogue IP is still difficult + +- Some tapeouts exist, but documentation is scarce +- Need more integration examples + +# Where are we going from here? + +## Improved languages + +- Type-checking for timing? +- Bus integration +- Documentation generation + +## Improved memories + +- OpenRAM coming to more processes + +## Better inference + +## More analogue IP # Getting involved! -## Siliwiz for raw tapeout +- Siliwiz for raw tapeout +- TinyTapeout +- Write more blogposts +- Give it a try -## TinyTapeout - -## \ No newline at end of file +Thank you!