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Signed-off-by: Sean Cross <sean@xobs.io>
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Sean Cross
2023-04-08 12:44:03 +08:00
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<section>
<h2>Outline</h2>
<ol>
<li>What is Open Silicon?</li>
<li>What can we do now?</li>
<li>What's to come?</li>
<li>What does it mean to be "open"?</li>
<li>What can we do today?</li>
<li>What can't we do today?</li>
<li>Where can we go from here?</li>
</ol>
</section>
<section>
<h2>About Me</h2>
</section>
<section>
<section>
<h2>What is Open Silicon?</h2>
<h2>What does it mean to be "open"?</h2>
<ol>
<li>A process design kit that can be manufactured</li>
<li>An open set of tools to go from design to production</li>
<li>Easy access to a silicon foundary for small-volume production</li>
<li>Manuals available</li>
<li>Source available</li>
<li>Tooling available</li>
<li>GDSII available</li>
</ol>
</section>
<section>
<h2>Parts of chip design</h2>
<ul>
<li>Process Design Kit (PDK)</li>
<li>IP (libraries)</li>
<li>Tooling</li>
<li>Fabrication method</li>
</ul>
</section>
<section>
<h2>Process Design Kit</h2>
<ul>
<li>https://skywater-pdk.readthedocs.io/en/main/_images/metal_stack.svg</li>
<li>Process design kits (PDKs) are closed and under NDA</li>
<li>Mostly just a blank canvas</li>
</ul>
</section>
<section>
<h2>IP / Libraries</h2>
<ul>
<li>Memories</li>
<li>IO blocks</li>
<li>Standard cells</li>
</ul>
</section>
<section>
<h2>Digital design (In The Beginning)</h2>
<ul>
<li>[Picture of Z80 or 6502]</li>
<li>Magic</li>
<li>[Picture of Siliwiz]</li>
</ul>
</section>
<section>
<h2>Digital logic overview (Today)</h2>
<ul>
<li>Standard cells</li>
<li>Basic boolean logic</li>
</ul>
</section>
<section>
<h2>How can we use standard cells?</h2>
<ul>
<li>Manual synthesis</li>
<li>Automated synthesis</li>
</ul>
Almost all code is automatically synthesized from source code!
[Example of live generation of cells]
</section>
<section>
<h2>Tooling</h2>
<ul>
<li>Synthesis</li>
<li>Power generation</li>
<li>Clock tree</li>
<li>Place and route</li>
<li>Verification</li>
<li><strong>Industry tools cost $1mm plus per seat</strong></li>
</ul>
</section>
<section>
<h2>Method to tape out</h2>
<ul>
<li>Shuttle runs</li>
<li>Full wafer</li>
<li>Turnaround time is in months</li>
</ul>
</section>
</section>
<section>
<section>
<h2>The State of the Toolchin</h2>
<h2>Where are we now (in open source)?</h2>
</section>
<section>
<h2>Process Design Kits (PDKs)</h2>
<h2>Things are looking pretty good!</h2>
</section>
<section>
<h2>Open PDKs</h2>
<ul>
<li>Real PDKs</li>
<ul>
<li>SKY130</li>
<li>SKY90FD</li>
<li>GF180MCU </li>
</ul>
<li>"Fake" PDKs</li>
<ul>
<li>FreePDK45</li>
<li>ASAP5 </li>
</ul>
</ul>
</section>
<section>
<h2>Available IP</h2>
Projects that have been taped out
<ul>
<li>ADC</li>
<li>LDO</li>
<li>Bandgap</li>
<li>DAC</li>
<li>...more...</li>
</ul>
</section>
<section>
<h2>Standard cells</h2>
<ul>
<li>SKY130</li>
<li>GF180MCU</li>
<li><small>FreePDK</small></li>
<li>OSU</li>
<li>LibreSilicon</li>
</ul>
</section>
<section>
<h2>Simulation</h2>
<ul>
<li>GHDL</li>
<li>Icarus Verilog</li>
<li>Verilator</li>
<li>GTKWave</li>
</ul>
</section>
<section>
<h2>Design Synthesis</h2>
<ul>
<li>Verilog / VHDL -> Verilog</li>
</ul>
</section>
<section>
<h2>Place and Route</h2>
</section>
<section>
<h2>Direct Cell Design</h2>
<ul>
<li>Magic</li>
<li>KLayout</li>
</ul>
</section>
</section>
<section>
<section>
<h1>What can we do now?</h1>
</section>
<section>
<h2>Examples of 130 nm</h2>
<ul>
<li>Gamecube CPU "Gekko": 43 mm<sup>2</sup> (2001)</li>
</ul>
<h2>Examples of 180 nm</h2>
<ul>
<li>Playstation 2 "Emotion Engine"</li>
</ul>
</section>
</section>