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more standard cells!

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Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2023-04-14 11:20:30 +08:00
parent f48869ad20
commit a079aa8692
3 changed files with 81 additions and 8 deletions
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@ -117,6 +117,71 @@
<img data-src="img/gf180mcu_fd_sc_mcu7t5v0__latq_1.layout.png">
</div>
</section>
<section>
<h2>Boolean Logic</h2>
<table class="wikitable" style="margin:1em auto 1em auto; text-align:center;">
<tbody>
<tr>
<th><i>p</i></th>
<th><i>q</i></th>
<td></td>
<th>NOR</th>
<th>XOR</th>
<th>NAND</th>
<th>AND</th>
<th>XNOR</th>
<th>OR</th>
</tr>
<tr>
<th>T</th>
<th>T</th>
<td></td>
<td>F</td>
<td>F</td>
<td>F</td>
<td>T</td>
<td>T</td>
<td>T</td>
</tr>
<tr>
<th>T</th>
<th>F
</th>
<td></td>
<td>F</td>
<td>T</td>
<td>T</td>
<td>F</td>
<td>F</td>
<td>T</td>
</tr>
<tr>
<th>F</th>
<th>T</th>
<td></td>
<td>F</td>
<td>T</td>
<td>T</td>
<td>F</td>
<td>F</td>
<td>T</td>
</tr>
<tr>
<th>F</th>
<th>F</th>
<td></td>
<td>T</td>
<td>F</td>
<td>T</td>
<td>F</td>
<td>T</td>
<td>F</td>
</tr>
</tbody>
</table>
</section>
<section>
<h2>Digital design (In The Beginning)</h2>
<div class="r-vstack">
@ -131,23 +196,28 @@
<img data-src="img/GD32F103CBT6-zeptobars-annotated.jpg" class="fragment fade-in-then-out">
<!-- <img data-src="img/GD32F103CBT6-zeptobars.jpg" class="fragment fade-in-then-out"> -->
<img data-src="img/GD32F103CBT6-SC1-50.jpg" class="fragment fade-in-then-out">
<img data-src="img/GD32F103CBT6-SC1-50-tracks.jpg" class="fragment fade-in-then-out">
<img data-src="img/GD32F103CBT6-SC2-50.jpg" class="fragment fade-in-then-out">
</div>
<p>Image &copy; 2016 Zeptobars</p>
</section>
<section>
<h2>Digital Synthesis (Today)</h2>
<div class="r-hstack">
<pre data-id="code-animation"><code class="hljs verilog" data-trim data-line-numbers>
<div class="r-vstack">
<div class="r-hstack">
<pre data-id="code-animation"><code class="hljs verilog" data-trim data-line-numbers>
module and_four(input A, input B,
input C, input D,
output X);
assign X = A & B & C & D;
endmodule
</code></pre>
<div class="r-vstack">
<img data-src="img/boolean-4.png">
<img data-src="img/boolean-1.png">
</code></pre>&nbsp;&nbsp;
<div>Verilog: X is <code>1</code> if A, B, C, and D are all 1, otherwise X is <code>0</code>
</div>
</div>
<div class="r-hstack fragment">
<img data-src="img/boolean-4.png">&nbsp;&nbsp;
<img class="fragment" data-src="img/boolean-1.png">
</div>
</div>
</section>
@ -237,7 +307,10 @@
<section>
<h2>Available IP</h2>
<div class="r-hstack">
<img data-src="img/Riscduino_Soc.png" height="500">
<div>
<img data-src="img/Riscduino_Soc.png" height="500">
<div>Dinesh Annayya</div>
</div>
<ul>
<ul>
<li>CPU</li>
@ -405,8 +478,8 @@
<li>Tiny Tapeout -- tinytapeout.com</li>
<li>Siliwiz -- app.siliwiz.com</li>
</ul>
<h2 class="fragment">Thank you</h2>
<img class="fragment" data-src="img/j22-core.jpg">
<h2 class="fragment">Thank you</h2>
<h3 class="fragment">Questions?</h3>
</section>
</section>