p | +q | ++ | NOR | +XOR | +NAND | +AND | +XNOR | +OR | +
---|---|---|---|---|---|---|---|---|
T | +T | ++ | F | +F | +F | +T | +T | +T | +
T | +F + | ++ | F | +T | +T | + +F | +F | +T | +
F | +T | ++ | F | +T | +T | +F | +F | +T | +
F | +F | ++ | T | +F | + +T | +F | +T | +F | +
Image © 2016 Zeptobars
+
+
+
module and_four(input A, input B,
input C, input D,
output X);
assign X = A & B & C & D;
endmodule
-
-
-
-
+
+ Verilog: X is 1
if A, B, C, and D are all 1, otherwise X is 0
+
+
+
+
+
@@ -237,7 +307,10 @@
Available IP
-
+
+
+ Dinesh Annayya
+
- CPU
@@ -405,8 +478,8 @@
- Tiny Tapeout -- tinytapeout.com
- Siliwiz -- app.siliwiz.com
- Thank you
+ Thank you
Questions?