2012-10-21 01:14:50 +00:00
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<!doctype html>
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2022-08-12 06:19:15 +00:00
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<html lang="en">
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2023-04-05 11:41:22 +00:00
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<title>reveal.js</title>
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</head>
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<body>
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<div class="reveal">
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<div class="slides">
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<section>The State of Open Silicon</section>
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<section>
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<h2>Outline</h2>
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<ol>
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2023-04-08 04:44:03 +00:00
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<li>What does it mean to be "open"?</li>
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<li>What can we do today?</li>
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<li>What can't we do today?</li>
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<li>Where can we go from here?</li>
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2023-04-05 11:41:22 +00:00
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</ol>
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</section>
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2023-04-08 04:44:03 +00:00
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<section>
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<h2>About Me</h2>
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</section>
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2023-04-05 11:41:22 +00:00
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<section>
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<section>
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2023-04-08 04:44:03 +00:00
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<h2>What does it mean to be "open"?</h2>
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2023-04-05 11:41:22 +00:00
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<ol>
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2023-04-08 04:44:03 +00:00
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<li>Manuals available</li>
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<li>Source available</li>
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<li>Tooling available</li>
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<li>GDSII available</li>
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2023-04-05 11:41:22 +00:00
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</ol>
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</section>
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2023-04-08 04:44:03 +00:00
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<section>
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<h2>Parts of chip design</h2>
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<ul>
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<li>Process Design Kit (PDK)</li>
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<li>IP (libraries)</li>
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<li>Tooling</li>
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<li>Fabrication method</li>
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</ul>
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</section>
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<section>
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<h2>Process Design Kit</h2>
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<ul>
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<li>https://skywater-pdk.readthedocs.io/en/main/_images/metal_stack.svg</li>
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<li>Process design kits (PDKs) are closed and under NDA</li>
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<li>Mostly just a blank canvas</li>
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</ul>
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</section>
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<section>
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<h2>IP / Libraries</h2>
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<ul>
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<li>Memories</li>
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<li>IO blocks</li>
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<li>Standard cells</li>
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</ul>
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</section>
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<section>
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<h2>Digital design (In The Beginning)</h2>
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<ul>
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<li>[Picture of Z80 or 6502]</li>
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<li>Magic</li>
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<li>[Picture of Siliwiz]</li>
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</ul>
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</section>
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<section>
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<h2>Digital logic overview (Today)</h2>
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<ul>
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<li>Standard cells</li>
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<li>Basic boolean logic</li>
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</ul>
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</section>
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<section>
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<h2>How can we use standard cells?</h2>
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<ul>
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<li>Manual synthesis</li>
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<li>Automated synthesis</li>
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</ul>
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Almost all code is automatically synthesized from source code!
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[Example of live generation of cells]
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</section>
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<section>
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<h2>Tooling</h2>
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<ul>
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<li>Synthesis</li>
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<li>Power generation</li>
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<li>Clock tree</li>
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<li>Place and route</li>
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<li>Verification</li>
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<li><strong>Industry tools cost $1mm plus per seat</strong></li>
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</ul>
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</section>
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<section>
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<h2>Method to tape out</h2>
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<ul>
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<li>Shuttle runs</li>
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<li>Full wafer</li>
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<li>Turnaround time is in months</li>
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</ul>
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</section>
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2023-04-05 11:41:22 +00:00
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</section>
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<section>
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<section>
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2023-04-08 04:44:03 +00:00
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<h2>Where are we now (in open source)?</h2>
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</section>
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<section>
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<h2>Things are looking pretty good!</h2>
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</section>
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<section>
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<h2>Open PDKs</h2>
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<ul>
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<li>Real PDKs</li>
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<ul>
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<li>SKY130</li>
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<li>SKY90FD</li>
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<li>GF180MCU </li>
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</ul>
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<li>"Fake" PDKs</li>
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<ul>
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<li>FreePDK45</li>
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<li>ASAP5 </li>
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</ul>
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</ul>
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</section>
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<section>
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<h2>Available IP</h2>
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Projects that have been taped out
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<ul>
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<li>ADC</li>
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<li>LDO</li>
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<li>Bandgap</li>
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<li>DAC</li>
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<li>...more...</li>
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</ul>
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2023-04-05 11:41:22 +00:00
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</section>
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<section>
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2023-04-08 04:44:03 +00:00
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<h2>Standard cells</h2>
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2023-04-05 11:41:22 +00:00
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<ul>
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<li>SKY130</li>
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<li>GF180MCU</li>
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2023-04-08 04:44:03 +00:00
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<li>OSU</li>
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<li>LibreSilicon</li>
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</ul>
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</section>
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<section>
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<h2>Simulation</h2>
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<ul>
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<li>GHDL</li>
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<li>Icarus Verilog</li>
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<li>Verilator</li>
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<li>GTKWave</li>
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</ul>
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</section>
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<section>
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<h2>Design Synthesis</h2>
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<ul>
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<li>Verilog / VHDL -> Verilog</li>
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</ul>
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</section>
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<section>
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<h2>Place and Route</h2>
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</section>
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<section>
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<h2>Direct Cell Design</h2>
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<ul>
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<li>Magic</li>
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<li>KLayout</li>
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</ul>
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</section>
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</section>
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<section>
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<section>
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<h1>What can we do now?</h1>
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</section>
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<section>
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<h2>Examples of 130 nm</h2>
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<ul>
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<li>Gamecube CPU "Gekko": 43 mm<sup>2</sup> (2001)</li>
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</ul>
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<h2>Examples of 180 nm</h2>
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<ul>
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<li>Playstation 2 "Emotion Engine"</li>
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2023-04-05 11:41:22 +00:00
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</ul>
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</section>
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</section>
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2021-11-11 14:13:31 +00:00
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</div>
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2023-04-05 11:41:22 +00:00
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</body>
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2012-03-24 16:48:16 +00:00
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2012-08-04 04:33:27 +00:00
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