The State of Open Silicon

Outline

  1. What does it mean to be "open"?
  2. What can we do today?
  3. What can't we do today?
  4. Where can we go from here?

About Me

What does it mean to be "open"?

  1. Manuals available
  2. Source available
  3. Tooling available
  4. GDSII available

Parts of chip design

  • Process Design Kit (PDK)
  • IP (libraries)
  • Tooling
  • Fabrication method

Process Design Kit

  • https://skywater-pdk.readthedocs.io/en/main/_images/metal_stack.svg
  • Process design kits (PDKs) are closed and under NDA
  • Mostly just a blank canvas

IP / Libraries

  • Memories
  • IO blocks
  • Standard cells

Digital design (In The Beginning)

  • [Picture of Z80 or 6502]
  • Magic
  • [Picture of Siliwiz]

Digital logic overview (Today)

  • Standard cells
  • Basic boolean logic

How can we use standard cells?

  • Manual synthesis
  • Automated synthesis
Almost all code is automatically synthesized from source code! [Example of live generation of cells]

Tooling

  • Synthesis
  • Power generation
  • Clock tree
  • Place and route
  • Verification
  • Industry tools cost $1mm plus per seat

Method to tape out

  • Shuttle runs
  • Full wafer
  • Turnaround time is in months

Where are we now (in open source)?

Things are looking pretty good!

Open PDKs

  • Real PDKs
    • SKY130
    • SKY90FD
    • GF180MCU
  • "Fake" PDKs
    • FreePDK45
    • ASAP5

Available IP

Projects that have been taped out
  • ADC
  • LDO
  • Bandgap
  • DAC
  • ...more...

Standard cells

  • SKY130
  • GF180MCU
  • OSU
  • LibreSilicon

Simulation

  • GHDL
  • Icarus Verilog
  • Verilator
  • GTKWave

Design Synthesis

  • Verilog / VHDL -> Verilog

Place and Route

Direct Cell Design

  • Magic
  • KLayout

What can we do now?

Examples of 130 nm

  • Gamecube CPU "Gekko": 43 mm2 (2001)

Examples of 180 nm

  • Playstation 2 "Emotion Engine"