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Signed-off-by: Sean Cross <sean@xobs.io>
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Sean Cross 2019-08-19 15:26:38 +08:00
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@ -37,41 +37,41 @@
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@ -80,14 +80,18 @@
<!-- Start of main presentation --> <!-- Start of main presentation -->
<div class="reveal"> <div class="reveal">
<div class="footer"> <div class="footer">
<div class="url">Slides: <a href="https://p.xobs.io/camp19/">p.xobs.io/camp</a> &nbsp; Software: <a href="https://fomu.im/camp19">fomu.im/camp19</a></div> <div class="url">Slides: <a href="https://p.xobs.io/camp19/">p.xobs.io/camp19</a> &nbsp; Software: <a
href="https://fomu.im/camp19">fomu.im/camp19</a></div>
<span class="theme">CCC Camp 2019</span><span class="hashtag"> | #CCCamp</span><span class="twitter"> | <span class="theme">CCC Camp 2019</span><span class="hashtag"> | #CCCamp</span><span class="twitter"> |
@tomu_im</span> @tomu_im</span>
</div> </div>
<div class="slides"> <div class="slides">
<section> <section>
<p> <p>
Download Software from <a href="https://fomu.im/camp19">fomu.im/camp19</a> Software is available on the USB drive marked "Fomu Workshop"
</p>
<p>
Or, download software from <a href="https://fomu.im/camp19">fomu.im/camp19</a>
</p> </p>
</section> </section>
@ -95,7 +99,8 @@
<h1>Fomu: An FPGA in your USB Port</h1> <h1>Fomu: An FPGA in your USB Port</h1>
<h4>A whirlwind introduction to Fomu; a workshop in three levels</h4> <h4>A whirlwind introduction to Fomu; a workshop in three levels</h4>
<p align="right"> <p align="right">
<small>Sean Cross - <a href="https://xobs.io/">https://xobs.io/</a> - @xobs</small> <small>Sean "xobs" Cross - <a href="https://xobs.io/">https://xobs.io/</a> - @xobs</small>
<small>Tim "mithro" Ansell - <a href="https://github.com/timvideos/litex-buildenv/wiki/">https://github.com/timvideos/litex-buildenv/wiki/</a> - @mithro</small>
</p> </p>
</section> </section>
@ -109,6 +114,11 @@
<li>FPGA / HDL</li> <li>FPGA / HDL</li>
</ol> </ol>
</p> </p>
<aside class="notes">
The overarching idea behind Fomu is to take a top-down approach to hardware design. Start at
something familiar, such as Python, and keep drilling down until you are no longer interested in
going further.
</aside>
</section> </section>
<section> <section>
@ -118,6 +128,10 @@
<li>What is an FPGA, and what is Fomu?</li> <li>What is an FPGA, and what is Fomu?</li>
<li>Working with Fomu using Python, RISC-V, and HDL</li> <li>Working with Fomu using Python, RISC-V, and HDL</li>
</ol> </ol>
<aside class="notes">
Broadly, this workshop will cover three parts: What do you need to get started with Fomu, what is an
FPGA and why is Fomu special, and finally how to work with Fomu at three different levels.
</aside>
</section> </section>
<section> <section>
@ -130,6 +144,11 @@
<li>FPGA Toolchain</li> <li>FPGA Toolchain</li>
<li>Python 3</li> <li>Python 3</li>
</ol> </ol>
<aside class="notes">
You require all of the software on this list. This software is provided on the USB drive that's
provided, or you can get them from <a
href="https://github.com/im-tomu/fomu-toolchain/releases">https://github.com/im-tomu/fomu-toolchain/releases</a>.
</aside>
</section> </section>
</section> </section>
@ -137,135 +156,143 @@
<section> <section>
<h2>What is an FPGA?</h2> <h2>What is an FPGA?</h2>
<img data-src="img/ice40-lut.png" alt="SB_LUT4"> <img data-src="img/ice40-lut.png" alt="SB_LUT4">
<!-- <aside clas="notes">
<p> An FPGA is an array of gates that's field-programmable. A more useful definition might be "a
An FPGA is a chip that executes logic. chip you can reconfigure". Most chips are collections of transistors that take two inputs and
</p> have one output. FPGAs have collections of transistors that look like this -- they take multiple
<p> inputs and produce multiple outputs. On Fomu, the basic building block is a 4-input 1-output
FPGAs are measured in resources called LUTs or LCs. lookup table called an "LC4". These are so important to FPGAs that the part number usually
</p> contains how many LUTs there are. The Fomu has a UP5K, which has about 5000 LUTs. The NeTV had
--> an LX9, which had 9000 LUTs. The NeTV2 has an XC7A35T, which has 35000 LUTs.
</section> </aside>
</section>
<section> <section>
<h2>What is an FPGA?</h2> <h2>What is an FPGA?</h2>
<table style="transform: scale(.80) translate(-15%)"> <table style="transform: scale(.80) translate(-15%)">
<tr> <tr>
<th></th> <th></th>
<th>0</th> <th>0</th>
<th>1</th> <th>1</th>
<th>2</th> <th>2</th>
<th>3</th> <th>3</th>
<th>4</th> <th>4</th>
<th>5</th> <th>5</th>
<th>6</th> <th>6</th>
<th>7</th> <th>7</th>
<th>8</th> <th>8</th>
<th>9</th> <th>9</th>
<th>10</th> <th>10</th>
<th>11</th> <th>11</th>
<th>12</th> <th>12</th>
<th>13</th> <th>13</th>
<th>14</th> <th>14</th>
<th>15</th> <th>15</th>
</tr> </tr>
<tr> <tr>
<td>IO0</td> <td>IO0</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
</tr> </tr>
<tr> <tr>
<td>IO1</td> <td>IO1</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
</tr> </tr>
<tr> <tr>
<td>IO2</td> <td>IO2</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
<td>0</td> <td>0</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>1</td> <td>1</td>
</tr> </tr>
<tr> <tr>
<td>IO3</td> <td>IO3</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
<td>0</td> <td>0</td>
<td>1</td> <td>1</td>
</tr> </tr>
<tr> <tr>
<td>O</td> <td>O</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
<td>?</td> <td>?</td>
</tr> </tr>
</table> </table>
</section> <aside class="notes">
A LUT is a lookup table. The value of the output depends on the value of all the inputs. You can
make arbitrary boolean logic here. For example, we could make a LUT that performs the logical
AND of all the inputs, and set it so that it only outputs a "1" if all of the inputs are 1. Or
we can make a NAND gate by taking the inverse. Each one of those 5000 LUTs in Fomu has a truth
table like this that it evaluates in real time.
</aside>
</section>
<section> <section>
<h2>What is an FPGA?</h2> <h2>What is an FPGA?</h2>
@ -280,6 +307,11 @@
endmodule endmodule
</code></pre> </code></pre>
<img class="fragment" data-src="img/verilog-synthesis.png" alt="Verilog Synthesis"> <img class="fragment" data-src="img/verilog-synthesis.png" alt="Verilog Synthesis">
<aside class="notes">
It gets really tedious to be thinking about lookup tables all the time, so humans created programming languages to do it for them. This is an example of Verilog code. It makes a simple counter that outputs the xor of some values.
In order to turn this Verilog code into actual LUTs, we run it through a synthesizer. Much like how a compiler turns programming language into CPU opcodes, a synthesizer turns Verilog code into lookup tables
</aside>
</section> </section>
<section> <section>
@ -314,11 +346,11 @@
</section> </section>
<section> <section>
<h2>Fomu Block Design Diagram</h2> <h2>Fomu Block Design Diagram</h2>
<img data-src="img/fomu-block-diagram.png" alt="Fomu block diagram"> <img data-src="img/fomu-block-diagram.png" alt="Fomu block diagram">
</section> </section>
<section> <section>
<h2>What is this PCB?</h2> <h2>What is this PCB?</h2>
<img data-src="img/tomu-fpga-evt-1-small.jpg" alt="Fomu EVT1"> <img data-src="img/tomu-fpga-evt-1-small.jpg" alt="Fomu EVT1">
<h3>Fomu EVT1</h3> <h3>Fomu EVT1</h3>
@ -344,12 +376,12 @@
</p> --> </p> -->
</section> </section>
<section> <section>
<h2>Misleading Datasheets</h2> <h2>Misleading Datasheets</h2>
<img data-src="img/xtal-datasheet-icon.jpg" alt="Footprint from Crystal"> <img data-src="img/xtal-datasheet-icon.jpg" alt="Footprint from Crystal">
</section> </section>
<section> <section>
<h2>What modifications does it have?</h2> <h2>What modifications does it have?</h2>
<ul> <ul>
<li>Shorting out two zero-ohm resistors (R7, PU)</li> <li>Shorting out two zero-ohm resistors (R7, PU)</li>
@ -376,19 +408,19 @@
<section> <section>
<section> <section>
<h2>Working with Fomu</h2> <h2>Working with Fomu</h2>
</section> </section>
<section> <section>
<h2>FAT Bootloader</h2> <h2>FAT Bootloader</h2>
<ul> <ul>
<li>Presents itself as a USB disk</li> <li>Presents itself as a USB disk</li>
<li>Drag and drop files to program</li> <li>Drag and drop files to program</li>
<li>Multiple interpreter support</li> <li>Multiple interpreter support</li>
</ul> </ul>
<div> <div>
<img data-src="img/under-construction.gif" class="fragment"> <img data-src="img/under-construction.gif" class="fragment">
</div> </div>
</section> </section>
<section> <section>
<h2>"fail safe" bootloader</h2> <h2>"fail safe" bootloader</h2>
@ -448,28 +480,28 @@ $ dfu-util -D new-image.dfu # Load new program</code></pre>
>>> rgb.mode("error") >>> rgb.mode("error")
>>> >>>
</code></pre> </code></pre>
</section> </section>
<section> <section>
<h2>Read SPI ID</h2> <h2>Read SPI ID</h2>
<pre><code class="python" data-trim> <pre><code class="python" data-trim>
>>> spi = fomu.spi() >>> spi = fomu.spi()
>>> hex(spi.id()) >>> hex(spi.id())
'0xc2152815' '0xc2152815'
>>> >>>
</code></pre> </code></pre>
</section> </section>
<section> <section>
<h2>Memory-Mapped Registers</h2> <h2>Memory-Mapped Registers</h2>
<pre><code class="cpp">#define CSR_VERSION_MAJOR_ADDR 0xe0007000 <pre><code class="cpp">#define CSR_VERSION_MAJOR_ADDR 0xe0007000
#define CSR_VERSION_MINOR_ADDR 0xe0007004 #define CSR_VERSION_MINOR_ADDR 0xe0007004
#define CSR_VERSION_REVISION_ADDR 0xe0007008</code></pre> #define CSR_VERSION_REVISION_ADDR 0xe0007008</code></pre>
<pre class="fragment"><code class="python">>>> import machine <pre class="fragment"><code class="python">>>> import machine
>>> machine.mem32[0xe0007000] >>> machine.mem32[0xe0007000]
1 1
>>></code></pre> >>></code></pre>
</section> </section>
<section> <section>
<h2>RGB LED Driver reference</h2> <h2>RGB LED Driver reference</h2>
@ -533,7 +565,7 @@ $ dfu-util -D new-image.dfu # Load new program</code></pre>
#define CSR_VERSION_GITEXTRA_ADDR 0xe000701c #define CSR_VERSION_GITEXTRA_ADDR 0xe000701c
#define CSR_VERSION_GITEXTRA_SIZE 2 #define CSR_VERSION_GITEXTRA_SIZE 2
</code></pre> </code></pre>
Excerpt from <code>csr.h</code> Excerpt from <code>csr.h</code>
</section> </section>
<section> <section>
@ -566,9 +598,9 @@ $ wishbone-tool --pid 0x5bf0 0xe0006800 0xff</code></pre>
OBJCOPY riscv-blink.bin OBJCOPY riscv-blink.bin
IHEX riscv-blink.ihex IHEX riscv-blink.ihex
$ </code></pre> $ </code></pre>
<p> <p>
From <code>riscv-blink</code> directory in <code>teardown2019-workshop</code> From <code>riscv-blink</code> directory in <code>teardown2019-workshop</code>
</p> </p>
</section> </section>
<section> <section>
@ -583,12 +615,12 @@ $ </code></pre>
int i = 0; int i = 0;
while (1) { while (1) {
i++;</code></pre> i++;</code></pre>
</section> </section>
<section> <section>
<h2>Other RISC-V Programs</h2> <h2>Other RISC-V Programs</h2>
riscv-usb-cdcacm: echo characters back after adding 1 riscv-usb-cdcacm: echo characters back after adding 1
</section> </section>
</section> </section>
<section> <section>
@ -597,18 +629,18 @@ $ </code></pre>
</section> </section>
<section> <section>
<h2>Yosys and NextPNR</h2> <h2>Yosys and NextPNR</h2>
<ul> <ul>
<li>Timing Driven!</li> <li>Timing Driven!</li>
</ul> </ul>
<pre><code>Max frequency for clock 'clk12': 24.63 MHz (PASS at 12.00 MHz) <pre><code>Max frequency for clock 'clk12': 24.63 MHz (PASS at 12.00 MHz)
Max frequency for clock 'clk48_1': 60.66 MHz (PASS at 48.00 MHz) Max frequency for clock 'clk48_1': 60.66 MHz (PASS at 48.00 MHz)
Max frequency for clock 'clkraw': 228.05 MHz (PASS at 48.00 MHz)</code></pre> Max frequency for clock 'clkraw': 228.05 MHz (PASS at 48.00 MHz)</code></pre>
</section> </section>
<section> <section>
<h2>Blinking an LED</h2> <h2>Blinking an LED</h2>
<pre><code>$ make FOMU_REV=evt <pre><code>$ make FOMU_REV=evt
... ...
20 warnings, 0 errors 20 warnings, 0 errors
PACK blink.bin PACK blink.bin
@ -617,72 +649,72 @@ $ dfu-util -D blink.bin</code></pre>
</section> </section>
<section> <section>
<h2>LiteX and MiGen</h2> <h2>LiteX and MiGen</h2>
<ol> <ol>
<li>Define hardware in Python</li> <li>Define hardware in Python</li>
<li>Evaluate Python to produce netlist</li> <li>Evaluate Python to produce netlist</li>
<li>Synthesize netlist to FPGA</li> <li>Synthesize netlist to FPGA</li>
</ol> </ol>
</section> </section>
<section> <section>
<h2>lxbuildenv.py</h2> <h2>lxbuildenv.py</h2>
<ol> <ol>
<li>Python environment using native interpreter</li> <li>Python environment using native interpreter</li>
<li>Very stable, good for hardware projects</li> <li>Very stable, good for hardware projects</li>
<li>Should work with system Python</li> <li>Should work with system Python</li>
<li>Runs on Linux, Windows, Raspberry Pi</li> <li>Runs on Linux, Windows, Raspberry Pi</li>
</ol> </ol>
</section> </section>
<section> <section>
<h2>Why do we need a CPU?</h2> <h2>Why do we need a CPU?</h2>
<img data-src="img/litex-design.png" alt="LiteX Design"> <img data-src="img/litex-design.png" alt="LiteX Design">
</section> </section>
<section> <section>
<h2>What if we remove the CPU?</h2> <h2>What if we remove the CPU?</h2>
<ul> <ul>
<li>Workshop project has no CPU</li> <li>Workshop project has no CPU</li>
<li>DummyUsb module automatically enumerates</li> <li>DummyUsb module automatically enumerates</li>
<li>Wishbone Debug Bridge still accessible</li> <li>Wishbone Debug Bridge still accessible</li>
</ul> </ul>
</section> </section>
<section> <section>
<h2>Build Workshop Module</h2> <h2>Build Workshop Module</h2>
<pre><code>$ python3 workshop.py --placer heap <pre><code>$ python3 workshop.py --placer heap
... ...
5 warnings, 0 errors 5 warnings, 0 errors
$ </code></pre> $ </code></pre>
</section> </section>
<section> <section>
<h2>Load onto Fomu</h2> <h2>Load onto Fomu</h2>
<pre><code>$ dfu-util -D build/gateware/top.bin <pre><code>$ dfu-util -D build/gateware/top.bin
Download [=========================] 100% 104090 bytes Download [=========================] 100% 104090 bytes
Download done. Download done.
$ </code></pre> $ </code></pre>
</section> </section>
<section> <section>
<h2>Write a value to RAM</h2> <h2>Write a value to RAM</h2>
<pre><code>$ wishbone-tool --pid 0x5bf0 0x10000000 <pre><code>$ wishbone-tool --pid 0x5bf0 0x10000000
Value at 10000000: 0baf801e Value at 10000000: 0baf801e
$ wishbone-tool --pid 0x5bf0 0x10000000 0x12345678 $ wishbone-tool --pid 0x5bf0 0x10000000 0x12345678
$ wishbone-tool --pid 0x5bf0 0x10000000 $ wishbone-tool --pid 0x5bf0 0x10000000
Value at 10000000: 12345678 Value at 10000000: 12345678
$ </code></pre> $ </code></pre>
</section> </section>
<section> <section>
<h2>Adding Hardware</h2> <h2>Adding Hardware</h2>
<img data-src="img/ice40-rgb.jpg" alt="Schematic of RGB block"> <img data-src="img/ice40-rgb.jpg" alt="Schematic of RGB block">
</section> </section>
<section> <section>
<h2>Technology Library Reference</h2> <h2>Technology Library Reference</h2>
<pre><code class="verilog">// Verilog Instantiation <pre><code class="verilog">// Verilog Instantiation
SB_RGBA_DRV RGBA_DRIVER ( SB_RGBA_DRV RGBA_DRIVER (
.CURREN(ENABLE_CURR), .CURREN(ENABLE_CURR),
.RGBLEDEN(ENABLE_RGBDRV), .RGBLEDEN(ENABLE_RGBDRV),
@ -697,11 +729,11 @@ defparam RGBA_DRIVER.CURRENT_MODE = "0b0";
defparam RGBA_DRIVER.RGB0_CURRENT = "0b111111"; defparam RGBA_DRIVER.RGB0_CURRENT = "0b111111";
defparam RGBA_DRIVER.RGB1_CURRENT = "0b111111" ; defparam RGBA_DRIVER.RGB1_CURRENT = "0b111111" ;
defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";</code></pre> defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";</code></pre>
<p>SBTICETechnologyLibrary201504.pdf page 147</p> <p>SBTICETechnologyLibrary201504.pdf page 147</p>
</section> </section>
<section> <section>
<h2>RGB Block</h2> <h2>RGB Block</h2>
<pre><code class="python" style="font-size: 18px; line-height: 22px">class FomuRGB(Module, AutoCSR): <pre><code class="python" style="font-size: 18px; line-height: 22px">class FomuRGB(Module, AutoCSR):
def __init__(self, pads): def __init__(self, pads):
self.output = CSRStorage(3) self.output = CSRStorage(3)
self.specials += Instance("SB_RGBA_DRV", self.specials += Instance("SB_RGBA_DRV",
@ -718,11 +750,11 @@ defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";</code></pre>
p_RGB1_CURRENT = "0b000011", p_RGB1_CURRENT = "0b000011",
p_RGB2_CURRENT = "0b000011", p_RGB2_CURRENT = "0b000011",
)</code></pre> )</code></pre>
</section> </section>
<section> <section>
<h2>Instantiating FomuRGB</h2> <h2>Instantiating FomuRGB</h2>
<pre><code class="diff">@@ -55,6 +75,10 @@ class BaseSoC(SoCCore): <pre><code class="diff">@@ -55,6 +75,10 @@ class BaseSoC(SoCCore):
with_ctrl=False, with_ctrl=False,
**kwargs) **kwargs)
@ -733,23 +765,23 @@ defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";</code></pre>
# UP5K has single port RAM.... # UP5K has single port RAM....
# Use this as CPU RAM. # Use this as CPU RAM.
spram_size = 128*1024</code></pre> spram_size = 128*1024</code></pre>
</section> </section>
<section> <section>
<h2>Interacting with the CSR</h2> <h2>Interacting with the CSR</h2>
<pre><code>csr_register,rgb_output,0xe0006800,1,rw</code></pre> <pre><code>csr_register,rgb_output,0xe0006800,1,rw</code></pre>
<p>From <code>test/csr.csv</code></p> <p>From <code>test/csr.csv</code></p>
</section> </section>
<section> <section>
<h2>VexRiscv</h2> <h2>VexRiscv</h2>
</section> </section>
</section> </section>
<section> <section>
<h2>Thank you</h2> <h2>Thank you</h2>
<h2>Lunch Time!</h2> <h2>Lunch Time!</h2>
</section> </section>
</div> </div>
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