index: add some notes
Signed-off-by: Sean Cross <sean@xobs.io>
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index.html
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@ -37,41 +37,41 @@
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/*********************************************
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* ZOOM REVERSE TRANSITION (i.e. zoom out)
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*********************************************/
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.reveal .slides section[data-transition=zoomrev],
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transition-timing-function: ease;
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.reveal .slides section[data-transition=zoomrev],
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transition-timing-function: ease;
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.reveal .slides > section[data-transition=zoomrev].past,
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visibility: hidden;
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-webkit-transform: scale(0.2);
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transform: scale(0.2);
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transform: scale(0.2);
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.reveal .slides > section[data-transition=zoomrev].future,
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visibility: hidden;
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-webkit-transform: scale(16);
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transform: scale(16);
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transform: translate(0, 150%);
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.reveal .slides>section>section[data-transition=zoomrev].past,
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-webkit-transform: translate(0, 150%);
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transform: translate(0, 150%);
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}
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.reveal .slides > section > section[data-transition~=zoomrev-in].future,
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-webkit-transform: translate(0, -150%);
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transform: translate(0, -150%);
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</style>
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.reveal .slides>section>section[data-transition=zoomrev].future,
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.reveal .slides>section>section[data-transition~=zoomrev-in].future,
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transform: translate(0, -150%);
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}
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</style>
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</head>
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@ -80,14 +80,18 @@
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<!-- Start of main presentation -->
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<div class="reveal">
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<div class="footer">
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<div class="url">Slides: <a href="https://p.xobs.io/camp19/">p.xobs.io/camp</a> Software: <a href="https://fomu.im/camp19">fomu.im/camp19</a></div>
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<div class="url">Slides: <a href="https://p.xobs.io/camp19/">p.xobs.io/camp19</a> Software: <a
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href="https://fomu.im/camp19">fomu.im/camp19</a></div>
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<span class="theme">CCC Camp 2019</span><span class="hashtag"> | #CCCamp</span><span class="twitter"> |
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@tomu_im</span>
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</div>
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<div class="slides">
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<section>
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<p>
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Download Software from <a href="https://fomu.im/camp19">fomu.im/camp19</a>
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Software is available on the USB drive marked "Fomu Workshop"
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</p>
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<p>
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Or, download software from <a href="https://fomu.im/camp19">fomu.im/camp19</a>
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</p>
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</section>
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@ -95,7 +99,8 @@
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<h1>Fomu: An FPGA in your USB Port</h1>
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<h4>A whirlwind introduction to Fomu; a workshop in three levels</h4>
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<p align="right">
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<small>Sean Cross - <a href="https://xobs.io/">https://xobs.io/</a> - @xobs</small>
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<small>Sean "xobs" Cross - <a href="https://xobs.io/">https://xobs.io/</a> - @xobs</small>
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<small>Tim "mithro" Ansell - <a href="https://github.com/timvideos/litex-buildenv/wiki/">https://github.com/timvideos/litex-buildenv/wiki/</a> - @mithro</small>
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</p>
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</section>
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@ -109,6 +114,11 @@
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<li>FPGA / HDL</li>
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</ol>
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</p>
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<aside class="notes">
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The overarching idea behind Fomu is to take a top-down approach to hardware design. Start at
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something familiar, such as Python, and keep drilling down until you are no longer interested in
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going further.
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</aside>
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</section>
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<section>
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@ -118,6 +128,10 @@
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<li>What is an FPGA, and what is Fomu?</li>
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<li>Working with Fomu using Python, RISC-V, and HDL</li>
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</ol>
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<aside class="notes">
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Broadly, this workshop will cover three parts: What do you need to get started with Fomu, what is an
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FPGA and why is Fomu special, and finally how to work with Fomu at three different levels.
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</aside>
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</section>
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<section>
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@ -130,6 +144,11 @@
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<li>FPGA Toolchain</li>
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<li>Python 3</li>
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</ol>
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<aside class="notes">
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You require all of the software on this list. This software is provided on the USB drive that's
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provided, or you can get them from <a
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href="https://github.com/im-tomu/fomu-toolchain/releases">https://github.com/im-tomu/fomu-toolchain/releases</a>.
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</aside>
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</section>
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</section>
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@ -137,135 +156,143 @@
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<section>
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<h2>What is an FPGA?</h2>
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<img data-src="img/ice40-lut.png" alt="SB_LUT4">
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<!--
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<p>
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An FPGA is a chip that executes logic.
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</p>
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<p>
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FPGAs are measured in resources called LUTs or LCs.
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</p>
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-->
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</section>
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<section>
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<h2>What is an FPGA?</h2>
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<table style="transform: scale(.80) translate(-15%)">
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<tr>
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<th></th>
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<th>0</th>
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<th>1</th>
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<th>2</th>
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<th>3</th>
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<th>4</th>
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<th>5</th>
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<th>6</th>
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<th>7</th>
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<th>8</th>
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<th>9</th>
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<th>10</th>
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<th>11</th>
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<th>12</th>
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<th>13</th>
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<th>14</th>
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<th>15</th>
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</tr>
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<tr>
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<td>IO0</td>
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<td>0</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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</tr>
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<tr>
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<td>IO1</td>
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<td>0</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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</tr>
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<tr>
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<td>IO2</td>
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<td>0</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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</tr>
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<tr>
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<td>IO3</td>
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<td>0</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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</tr>
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<tr>
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<td>O</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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</tr>
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</table>
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</section>
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<aside clas="notes">
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An FPGA is an array of gates that's field-programmable. A more useful definition might be "a
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chip you can reconfigure". Most chips are collections of transistors that take two inputs and
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have one output. FPGAs have collections of transistors that look like this -- they take multiple
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inputs and produce multiple outputs. On Fomu, the basic building block is a 4-input 1-output
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lookup table called an "LC4". These are so important to FPGAs that the part number usually
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contains how many LUTs there are. The Fomu has a UP5K, which has about 5000 LUTs. The NeTV had
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an LX9, which had 9000 LUTs. The NeTV2 has an XC7A35T, which has 35000 LUTs.
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</aside>
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</section>
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<section>
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<h2>What is an FPGA?</h2>
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<table style="transform: scale(.80) translate(-15%)">
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<tr>
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<th></th>
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<th>0</th>
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<th>1</th>
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<th>2</th>
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<th>3</th>
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<th>4</th>
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<th>5</th>
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<th>6</th>
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<th>7</th>
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<th>8</th>
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<th>9</th>
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<th>10</th>
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<th>11</th>
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<th>12</th>
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<th>13</th>
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<th>14</th>
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<th>15</th>
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</tr>
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<tr>
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<td>IO0</td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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</tr>
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<tr>
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<td>IO1</td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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</tr>
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<tr>
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<td>IO2</td>
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<td>0</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>1</td>
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<td>1</td>
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</tr>
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<tr>
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<td>IO3</td>
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<td>0</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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<td>0</td>
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<td>1</td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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<td>0</td>
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<td>1</td>
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</tr>
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<tr>
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<td>O</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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<td>?</td>
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</tr>
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</table>
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<aside class="notes">
|
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A LUT is a lookup table. The value of the output depends on the value of all the inputs. You can
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make arbitrary boolean logic here. For example, we could make a LUT that performs the logical
|
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AND of all the inputs, and set it so that it only outputs a "1" if all of the inputs are 1. Or
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we can make a NAND gate by taking the inverse. Each one of those 5000 LUTs in Fomu has a truth
|
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table like this that it evaluates in real time.
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</aside>
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</section>
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<section>
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<h2>What is an FPGA?</h2>
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@ -280,6 +307,11 @@
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endmodule
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</code></pre>
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<img class="fragment" data-src="img/verilog-synthesis.png" alt="Verilog Synthesis">
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<aside class="notes">
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It gets really tedious to be thinking about lookup tables all the time, so humans created programming languages to do it for them. This is an example of Verilog code. It makes a simple counter that outputs the xor of some values.
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In order to turn this Verilog code into actual LUTs, we run it through a synthesizer. Much like how a compiler turns programming language into CPU opcodes, a synthesizer turns Verilog code into lookup tables
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</aside>
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</section>
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<section>
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@ -295,7 +327,7 @@
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<li class="fragment highlight-blue">Open toolchain</li>
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</ol>
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</section>
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<section>
|
||||
<h2>What is Fomu?</h2>
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||||
<ul>
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@ -314,11 +346,11 @@
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</section>
|
||||
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<section>
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<h2>Fomu Block Design Diagram</h2>
|
||||
<img data-src="img/fomu-block-diagram.png" alt="Fomu block diagram">
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</section>
|
||||
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<section>
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<h2>Fomu Block Design Diagram</h2>
|
||||
<img data-src="img/fomu-block-diagram.png" alt="Fomu block diagram">
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</section>
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<section>
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<h2>What is this PCB?</h2>
|
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<img data-src="img/tomu-fpga-evt-1-small.jpg" alt="Fomu EVT1">
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<h3>Fomu EVT1</h3>
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@ -344,12 +376,12 @@
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</p> -->
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</section>
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<section>
|
||||
<h2>Misleading Datasheets</h2>
|
||||
<img data-src="img/xtal-datasheet-icon.jpg" alt="Footprint from Crystal">
|
||||
</section>
|
||||
<section>
|
||||
<h2>Misleading Datasheets</h2>
|
||||
<img data-src="img/xtal-datasheet-icon.jpg" alt="Footprint from Crystal">
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<section>
|
||||
<h2>What modifications does it have?</h2>
|
||||
<ul>
|
||||
<li>Shorting out two zero-ohm resistors (R7, PU)</li>
|
||||
|
|
@ -370,25 +402,25 @@
|
|||
<li>Interpreters</li>
|
||||
<li>Updates</li>
|
||||
</ol> -->
|
||||
</section>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<section>
|
||||
<h2>Working with Fomu</h2>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>FAT Bootloader</h2>
|
||||
<ul>
|
||||
<li>Presents itself as a USB disk</li>
|
||||
<li>Drag and drop files to program</li>
|
||||
<li>Multiple interpreter support</li>
|
||||
</ul>
|
||||
<div>
|
||||
<img data-src="img/under-construction.gif" class="fragment">
|
||||
</div>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>FAT Bootloader</h2>
|
||||
<ul>
|
||||
<li>Presents itself as a USB disk</li>
|
||||
<li>Drag and drop files to program</li>
|
||||
<li>Multiple interpreter support</li>
|
||||
</ul>
|
||||
<div>
|
||||
<img data-src="img/under-construction.gif" class="fragment">
|
||||
</div>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>"fail safe" bootloader</h2>
|
||||
|
|
@ -448,28 +480,28 @@ $ dfu-util -D new-image.dfu # Load new program</code></pre>
|
|||
>>> rgb.mode("error")
|
||||
>>>
|
||||
</code></pre>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Read SPI ID</h2>
|
||||
<pre><code class="python" data-trim>
|
||||
<section>
|
||||
<h2>Read SPI ID</h2>
|
||||
<pre><code class="python" data-trim>
|
||||
>>> spi = fomu.spi()
|
||||
>>> hex(spi.id())
|
||||
'0xc2152815'
|
||||
>>>
|
||||
</code></pre>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Memory-Mapped Registers</h2>
|
||||
<pre><code class="cpp">#define CSR_VERSION_MAJOR_ADDR 0xe0007000
|
||||
<section>
|
||||
<h2>Memory-Mapped Registers</h2>
|
||||
<pre><code class="cpp">#define CSR_VERSION_MAJOR_ADDR 0xe0007000
|
||||
#define CSR_VERSION_MINOR_ADDR 0xe0007004
|
||||
#define CSR_VERSION_REVISION_ADDR 0xe0007008</code></pre>
|
||||
<pre class="fragment"><code class="python">>>> import machine
|
||||
<pre class="fragment"><code class="python">>>> import machine
|
||||
>>> machine.mem32[0xe0007000]
|
||||
1
|
||||
>>></code></pre>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>RGB LED Driver reference</h2>
|
||||
|
|
@ -533,7 +565,7 @@ $ dfu-util -D new-image.dfu # Load new program</code></pre>
|
|||
#define CSR_VERSION_GITEXTRA_ADDR 0xe000701c
|
||||
#define CSR_VERSION_GITEXTRA_SIZE 2
|
||||
</code></pre>
|
||||
Excerpt from <code>csr.h</code>
|
||||
Excerpt from <code>csr.h</code>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
|
|
@ -566,9 +598,9 @@ $ wishbone-tool --pid 0x5bf0 0xe0006800 0xff</code></pre>
|
|||
OBJCOPY riscv-blink.bin
|
||||
IHEX riscv-blink.ihex
|
||||
$ </code></pre>
|
||||
<p>
|
||||
From <code>riscv-blink</code> directory in <code>teardown2019-workshop</code>
|
||||
</p>
|
||||
<p>
|
||||
From <code>riscv-blink</code> directory in <code>teardown2019-workshop</code>
|
||||
</p>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
|
|
@ -583,12 +615,12 @@ $ </code></pre>
|
|||
int i = 0;
|
||||
while (1) {
|
||||
i++;</code></pre>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Other RISC-V Programs</h2>
|
||||
riscv-usb-cdcacm: echo characters back after adding 1
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Other RISC-V Programs</h2>
|
||||
riscv-usb-cdcacm: echo characters back after adding 1
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
|
|
@ -597,18 +629,18 @@ $ </code></pre>
|
|||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Yosys and NextPNR</h2>
|
||||
<ul>
|
||||
<li>Timing Driven!</li>
|
||||
</ul>
|
||||
<pre><code>Max frequency for clock 'clk12': 24.63 MHz (PASS at 12.00 MHz)
|
||||
<h2>Yosys and NextPNR</h2>
|
||||
<ul>
|
||||
<li>Timing Driven!</li>
|
||||
</ul>
|
||||
<pre><code>Max frequency for clock 'clk12': 24.63 MHz (PASS at 12.00 MHz)
|
||||
Max frequency for clock 'clk48_1': 60.66 MHz (PASS at 48.00 MHz)
|
||||
Max frequency for clock 'clkraw': 228.05 MHz (PASS at 48.00 MHz)</code></pre>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Blinking an LED</h2>
|
||||
<pre><code>$ make FOMU_REV=evt
|
||||
<h2>Blinking an LED</h2>
|
||||
<pre><code>$ make FOMU_REV=evt
|
||||
...
|
||||
20 warnings, 0 errors
|
||||
PACK blink.bin
|
||||
|
|
@ -617,72 +649,72 @@ $ dfu-util -D blink.bin</code></pre>
|
|||
</section>
|
||||
|
||||
<section>
|
||||
<h2>LiteX and MiGen</h2>
|
||||
<ol>
|
||||
<li>Define hardware in Python</li>
|
||||
<li>Evaluate Python to produce netlist</li>
|
||||
<li>Synthesize netlist to FPGA</li>
|
||||
</ol>
|
||||
<h2>LiteX and MiGen</h2>
|
||||
<ol>
|
||||
<li>Define hardware in Python</li>
|
||||
<li>Evaluate Python to produce netlist</li>
|
||||
<li>Synthesize netlist to FPGA</li>
|
||||
</ol>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>lxbuildenv.py</h2>
|
||||
<ol>
|
||||
<li>Python environment using native interpreter</li>
|
||||
<li>Very stable, good for hardware projects</li>
|
||||
<li>Should work with system Python</li>
|
||||
<li>Runs on Linux, Windows, Raspberry Pi</li>
|
||||
</ol>
|
||||
</section>
|
||||
<section>
|
||||
<h2>lxbuildenv.py</h2>
|
||||
<ol>
|
||||
<li>Python environment using native interpreter</li>
|
||||
<li>Very stable, good for hardware projects</li>
|
||||
<li>Should work with system Python</li>
|
||||
<li>Runs on Linux, Windows, Raspberry Pi</li>
|
||||
</ol>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Why do we need a CPU?</h2>
|
||||
<section>
|
||||
<h2>Why do we need a CPU?</h2>
|
||||
<img data-src="img/litex-design.png" alt="LiteX Design">
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>What if we remove the CPU?</h2>
|
||||
<ul>
|
||||
<li>Workshop project has no CPU</li>
|
||||
<li>DummyUsb module automatically enumerates</li>
|
||||
<li>Wishbone Debug Bridge still accessible</li>
|
||||
</ul>
|
||||
</section>
|
||||
<section>
|
||||
<h2>What if we remove the CPU?</h2>
|
||||
<ul>
|
||||
<li>Workshop project has no CPU</li>
|
||||
<li>DummyUsb module automatically enumerates</li>
|
||||
<li>Wishbone Debug Bridge still accessible</li>
|
||||
</ul>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Build Workshop Module</h2>
|
||||
<pre><code>$ python3 workshop.py --placer heap
|
||||
<section>
|
||||
<h2>Build Workshop Module</h2>
|
||||
<pre><code>$ python3 workshop.py --placer heap
|
||||
...
|
||||
5 warnings, 0 errors
|
||||
$ </code></pre>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Load onto Fomu</h2>
|
||||
<pre><code>$ dfu-util -D build/gateware/top.bin
|
||||
<section>
|
||||
<h2>Load onto Fomu</h2>
|
||||
<pre><code>$ dfu-util -D build/gateware/top.bin
|
||||
Download [=========================] 100% 104090 bytes
|
||||
Download done.
|
||||
$ </code></pre>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Write a value to RAM</h2>
|
||||
<pre><code>$ wishbone-tool --pid 0x5bf0 0x10000000
|
||||
<section>
|
||||
<h2>Write a value to RAM</h2>
|
||||
<pre><code>$ wishbone-tool --pid 0x5bf0 0x10000000
|
||||
Value at 10000000: 0baf801e
|
||||
$ wishbone-tool --pid 0x5bf0 0x10000000 0x12345678
|
||||
$ wishbone-tool --pid 0x5bf0 0x10000000
|
||||
Value at 10000000: 12345678
|
||||
$ </code></pre>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Adding Hardware</h2>
|
||||
<img data-src="img/ice40-rgb.jpg" alt="Schematic of RGB block">
|
||||
</section>
|
||||
<section>
|
||||
<h2>Adding Hardware</h2>
|
||||
<img data-src="img/ice40-rgb.jpg" alt="Schematic of RGB block">
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Technology Library Reference</h2>
|
||||
<pre><code class="verilog">// Verilog Instantiation
|
||||
<section>
|
||||
<h2>Technology Library Reference</h2>
|
||||
<pre><code class="verilog">// Verilog Instantiation
|
||||
SB_RGBA_DRV RGBA_DRIVER (
|
||||
.CURREN(ENABLE_CURR),
|
||||
.RGBLEDEN(ENABLE_RGBDRV),
|
||||
|
|
@ -697,11 +729,11 @@ defparam RGBA_DRIVER.CURRENT_MODE = "0b0";
|
|||
defparam RGBA_DRIVER.RGB0_CURRENT = "0b111111";
|
||||
defparam RGBA_DRIVER.RGB1_CURRENT = "0b111111" ;
|
||||
defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";</code></pre>
|
||||
<p>SBTICETechnologyLibrary201504.pdf page 147</p>
|
||||
</section>
|
||||
<section>
|
||||
<h2>RGB Block</h2>
|
||||
<pre><code class="python" style="font-size: 18px; line-height: 22px">class FomuRGB(Module, AutoCSR):
|
||||
<p>SBTICETechnologyLibrary201504.pdf page 147</p>
|
||||
</section>
|
||||
<section>
|
||||
<h2>RGB Block</h2>
|
||||
<pre><code class="python" style="font-size: 18px; line-height: 22px">class FomuRGB(Module, AutoCSR):
|
||||
def __init__(self, pads):
|
||||
self.output = CSRStorage(3)
|
||||
self.specials += Instance("SB_RGBA_DRV",
|
||||
|
|
@ -718,11 +750,11 @@ defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";</code></pre>
|
|||
p_RGB1_CURRENT = "0b000011",
|
||||
p_RGB2_CURRENT = "0b000011",
|
||||
)</code></pre>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Instantiating FomuRGB</h2>
|
||||
<pre><code class="diff">@@ -55,6 +75,10 @@ class BaseSoC(SoCCore):
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Instantiating FomuRGB</h2>
|
||||
<pre><code class="diff">@@ -55,6 +75,10 @@ class BaseSoC(SoCCore):
|
||||
with_ctrl=False,
|
||||
**kwargs)
|
||||
|
||||
|
|
@ -733,23 +765,23 @@ defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";</code></pre>
|
|||
# UP5K has single port RAM....
|
||||
# Use this as CPU RAM.
|
||||
spram_size = 128*1024</code></pre>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Interacting with the CSR</h2>
|
||||
<pre><code>csr_register,rgb_output,0xe0006800,1,rw</code></pre>
|
||||
<p>From <code>test/csr.csv</code></p>
|
||||
</section>
|
||||
<section>
|
||||
<h2>Interacting with the CSR</h2>
|
||||
<pre><code>csr_register,rgb_output,0xe0006800,1,rw</code></pre>
|
||||
<p>From <code>test/csr.csv</code></p>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<section>
|
||||
<h2>VexRiscv</h2>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Thank you</h2>
|
||||
<h2>Lunch Time!</h2>
|
||||
</section>
|
||||
</section>
|
||||
|
||||
<section>
|
||||
<h2>Thank you</h2>
|
||||
<h2>Lunch Time!</h2>
|
||||
</section>
|
||||
</div>
|
||||
</div> <!-- class="reveal" -->
|
||||
<!-- End of main presentation -->
|
||||
|
|
|
|||
Loading…
Reference in New Issue