From 40f22ea04ed6e9625e49487e09e98009adb69ea2 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Mon, 19 Aug 2019 15:26:38 +0800 Subject: [PATCH] index: add some notes Signed-off-by: Sean Cross --- index.html | 598 ++++++++++++++++++++++++++++------------------------- 1 file changed, 315 insertions(+), 283 deletions(-) diff --git a/index.html b/index.html index 550876a..da75dcd 100644 --- a/index.html +++ b/index.html @@ -37,41 +37,41 @@ /********************************************* * ZOOM REVERSE TRANSITION (i.e. zoom out) *********************************************/ - .reveal .slides section[data-transition=zoomrev], - .reveal.zoomrev .slides section:not([data-transition]) { - transition-timing-function: ease; - } + .reveal .slides section[data-transition=zoomrev], + .reveal.zoomrev .slides section:not([data-transition]) { + transition-timing-function: ease; + } - .reveal .slides > section[data-transition=zoomrev].past, - .reveal .slides > section[data-transition~=zoomrev-out].past, - .reveal.zoomrev .slides > section:not([data-transition]).past { - visibility: hidden; - -webkit-transform: scale(0.2); - transform: scale(0.2); - } + .reveal .slides>section[data-transition=zoomrev].past, + .reveal .slides>section[data-transition~=zoomrev-out].past, + .reveal.zoomrev .slides>section:not([data-transition]).past { + visibility: hidden; + -webkit-transform: scale(0.2); + transform: scale(0.2); + } - .reveal .slides > section[data-transition=zoomrev].future, - .reveal .slides > section[data-transition~=zoomrev-in].future, - .reveal.zoomrev .slides > section:not([data-transition]).future { - visibility: hidden; - -webkit-transform: scale(16); - transform: scale(16); - } + .reveal .slides>section[data-transition=zoomrev].future, + .reveal .slides>section[data-transition~=zoomrev-in].future, + .reveal.zoomrev .slides>section:not([data-transition]).future { + visibility: hidden; + -webkit-transform: scale(16); + transform: scale(16); + } - .reveal .slides > section > section[data-transition=zoomrev].past, - .reveal .slides > section > section[data-transition~=zoomrev-out].past, - .reveal.zoomrev .slides > section > section:not([data-transition]).past { - -webkit-transform: translate(0, 150%); - transform: translate(0, 150%); - } + .reveal .slides>section>section[data-transition=zoomrev].past, + .reveal .slides>section>section[data-transition~=zoomrev-out].past, + .reveal.zoomrev .slides>section>section:not([data-transition]).past { + -webkit-transform: translate(0, 150%); + transform: translate(0, 150%); + } - .reveal .slides > section > section[data-transition=zoomrev].future, - .reveal .slides > section > section[data-transition~=zoomrev-in].future, - .reveal.zoomrev .slides > section > section:not([data-transition]).future { - -webkit-transform: translate(0, -150%); - transform: translate(0, -150%); - } - + .reveal .slides>section>section[data-transition=zoomrev].future, + .reveal .slides>section>section[data-transition~=zoomrev-in].future, + .reveal.zoomrev .slides>section>section:not([data-transition]).future { + -webkit-transform: translate(0, -150%); + transform: translate(0, -150%); + } + @@ -80,14 +80,18 @@

- Download Software from fomu.im/camp19 + Software is available on the USB drive marked "Fomu Workshop" +

+

+ Or, download software from fomu.im/camp19

@@ -95,7 +99,8 @@

Fomu: An FPGA in your USB Port

A whirlwind introduction to Fomu; a workshop in three levels

- Sean Cross - https://xobs.io/ - @xobs + Sean "xobs" Cross - https://xobs.io/ - @xobs + Tim "mithro" Ansell - https://github.com/timvideos/litex-buildenv/wiki/ - @mithro

@@ -109,6 +114,11 @@
  • FPGA / HDL
  • +
    @@ -118,6 +128,10 @@
  • What is an FPGA, and what is Fomu?
  • Working with Fomu using Python, RISC-V, and HDL
  • +
    @@ -130,6 +144,11 @@
  • FPGA Toolchain
  • Python 3
  • +
    @@ -137,135 +156,143 @@

    What is an FPGA?

    SB_LUT4 - -
    - -
    -

    What is an FPGA?

    - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
    0123456789101112131415
    IO00000000011111111
    IO10000111100001111
    IO20011001100110011
    IO30101010101010101
    O????????????????
    -
    + + + +
    +

    What is an FPGA?

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    0123456789101112131415
    IO00000000011111111
    IO10000111100001111
    IO20011001100110011
    IO30101010101010101
    O????????????????
    + +

    What is an FPGA?

    @@ -280,6 +307,11 @@ endmodule Verilog Synthesis +
    @@ -295,7 +327,7 @@
  • Open toolchain
  • - +

    What is Fomu?

      @@ -314,11 +346,11 @@
    -

    Fomu Block Design Diagram

    - Fomu block diagram -
    - -
    +

    Fomu Block Design Diagram

    + Fomu block diagram +
    + +

    What is this PCB?

    Fomu EVT1

    Fomu EVT1

    @@ -344,12 +376,12 @@

    -->
    -
    -

    Misleading Datasheets

    - Footprint from Crystal -
    +
    +

    Misleading Datasheets

    + Footprint from Crystal +
    -
    +

    What modifications does it have?

    • Shorting out two zero-ohm resistors (R7, PU)
    • @@ -370,25 +402,25 @@
    • Interpreters
    • Updates
    • --> -
    +

    Working with Fomu

    -
    - -
    -

    FAT Bootloader

    -
      -
    • Presents itself as a USB disk
    • -
    • Drag and drop files to program
    • -
    • Multiple interpreter support
    • -
    -
    - -
    -
    +
    + +
    +

    FAT Bootloader

    +
      +
    • Presents itself as a USB disk
    • +
    • Drag and drop files to program
    • +
    • Multiple interpreter support
    • +
    +
    + +
    +

    "fail safe" bootloader

    @@ -448,28 +480,28 @@ $ dfu-util -D new-image.dfu # Load new program >>> rgb.mode("error") >>> -
    + -
    -

    Read SPI ID

    -
    
    +				
    +

    Read SPI ID

    +
    
                                     >>> spi = fomu.spi()
                                     >>> hex(spi.id())
                                     '0xc2152815'
                                     >>>
                             
    -
    +
    -
    -

    Memory-Mapped Registers

    -
    #define CSR_VERSION_MAJOR_ADDR 0xe0007000
    +				
    +

    Memory-Mapped Registers

    +
    #define CSR_VERSION_MAJOR_ADDR 0xe0007000
     #define CSR_VERSION_MINOR_ADDR 0xe0007004
     #define CSR_VERSION_REVISION_ADDR 0xe0007008
    -
    >>> import machine
    +					
    >>> import machine
     >>> machine.mem32[0xe0007000]
     1
     >>>
    -
    +

    RGB LED Driver reference

    @@ -533,7 +565,7 @@ $ dfu-util -D new-image.dfu # Load new program
    #define CSR_VERSION_GITEXTRA_ADDR 0xe000701c #define CSR_VERSION_GITEXTRA_SIZE 2
    -Excerpt from csr.h + Excerpt from csr.h
    @@ -566,9 +598,9 @@ $ wishbone-tool --pid 0x5bf0 0xe0006800 0xff OBJCOPY riscv-blink.bin IHEX riscv-blink.ihex $ -

    - From riscv-blink directory in teardown2019-workshop -

    +

    + From riscv-blink directory in teardown2019-workshop +

    @@ -583,12 +615,12 @@ $ int i = 0; while (1) { i++; -
    - -
    -

    Other RISC-V Programs

    - riscv-usb-cdcacm: echo characters back after adding 1 -
    + + +
    +

    Other RISC-V Programs

    + riscv-usb-cdcacm: echo characters back after adding 1 +
    @@ -597,18 +629,18 @@ $
    -

    Yosys and NextPNR

    -
      -
    • Timing Driven!
    • -
    -
    Max frequency for clock 'clk12':   24.63 MHz (PASS at 12.00 MHz)
    +					

    Yosys and NextPNR

    +
      +
    • Timing Driven!
    • +
    +
    Max frequency for clock 'clk12':   24.63 MHz (PASS at 12.00 MHz)
     Max frequency for clock 'clk48_1': 60.66 MHz (PASS at 48.00 MHz)
     Max frequency for clock 'clkraw': 228.05 MHz (PASS at 48.00 MHz)
    -

    Blinking an LED

    -
    $ make FOMU_REV=evt
    +					

    Blinking an LED

    +
    $ make FOMU_REV=evt
     ...
     20 warnings, 0 errors
      PACK     blink.bin
    @@ -617,72 +649,72 @@ $ dfu-util -D blink.bin
    -

    LiteX and MiGen

    -
      -
    1. Define hardware in Python
    2. -
    3. Evaluate Python to produce netlist
    4. -
    5. Synthesize netlist to FPGA
    6. -
    +

    LiteX and MiGen

    +
      +
    1. Define hardware in Python
    2. +
    3. Evaluate Python to produce netlist
    4. +
    5. Synthesize netlist to FPGA
    6. +
    -
    -

    lxbuildenv.py

    -
      -
    1. Python environment using native interpreter
    2. -
    3. Very stable, good for hardware projects
    4. -
    5. Should work with system Python
    6. -
    7. Runs on Linux, Windows, Raspberry Pi
    8. -
    -
    +
    +

    lxbuildenv.py

    +
      +
    1. Python environment using native interpreter
    2. +
    3. Very stable, good for hardware projects
    4. +
    5. Should work with system Python
    6. +
    7. Runs on Linux, Windows, Raspberry Pi
    8. +
    +
    -
    -

    Why do we need a CPU?

    +
    +

    Why do we need a CPU?

    LiteX Design -
    +
    -
    -

    What if we remove the CPU?

    -
      -
    • Workshop project has no CPU
    • -
    • DummyUsb module automatically enumerates
    • -
    • Wishbone Debug Bridge still accessible
    • -
    -
    +
    +

    What if we remove the CPU?

    +
      +
    • Workshop project has no CPU
    • +
    • DummyUsb module automatically enumerates
    • +
    • Wishbone Debug Bridge still accessible
    • +
    +
    -
    -

    Build Workshop Module

    -
    $ python3 workshop.py --placer heap
    +				
    +

    Build Workshop Module

    +
    $ python3 workshop.py --placer heap
     ...
     5 warnings, 0 errors
     $ 
    -
    +
    -
    -

    Load onto Fomu

    -
    $ dfu-util -D build/gateware/top.bin
    +				
    +

    Load onto Fomu

    +
    $ dfu-util -D build/gateware/top.bin
     Download      [=========================] 100%    104090 bytes
     Download done.
     $ 
    -
    +
    -
    -

    Write a value to RAM

    -
    $ wishbone-tool --pid 0x5bf0 0x10000000
    +				
    +

    Write a value to RAM

    +
    $ wishbone-tool --pid 0x5bf0 0x10000000
     Value at 10000000: 0baf801e
     $ wishbone-tool --pid 0x5bf0 0x10000000 0x12345678
     $ wishbone-tool --pid 0x5bf0 0x10000000
     Value at 10000000: 12345678
     $ 
    -
    +
    -
    -

    Adding Hardware

    - Schematic of RGB block -
    +
    +

    Adding Hardware

    + Schematic of RGB block +
    -
    -

    Technology Library Reference

    -
    // Verilog Instantiation
    +				
    +

    Technology Library Reference

    +
    // Verilog Instantiation
     SB_RGBA_DRV RGBA_DRIVER (
     .CURREN(ENABLE_CURR),
     .RGBLEDEN(ENABLE_RGBDRV),
    @@ -697,11 +729,11 @@ defparam RGBA_DRIVER.CURRENT_MODE = "0b0";
     defparam RGBA_DRIVER.RGB0_CURRENT = "0b111111";
     defparam RGBA_DRIVER.RGB1_CURRENT = "0b111111" ;
     defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";
    -

    SBTICETechnologyLibrary201504.pdf page 147

    -
    -
    -

    RGB Block

    -
    class FomuRGB(Module, AutoCSR):
    +					

    SBTICETechnologyLibrary201504.pdf page 147

    +
    +
    +

    RGB Block

    +
    class FomuRGB(Module, AutoCSR):
         def __init__(self, pads):
             self.output = CSRStorage(3)
             self.specials += Instance("SB_RGBA_DRV",
    @@ -718,11 +750,11 @@ defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";
    p_RGB1_CURRENT = "0b000011", p_RGB2_CURRENT = "0b000011", )
    -
    - -
    -

    Instantiating FomuRGB

    -
    @@ -55,6 +75,10 @@ class BaseSoC(SoCCore):
    +				
    + +
    +

    Instantiating FomuRGB

    +
    @@ -55,6 +75,10 @@ class BaseSoC(SoCCore):
                      with_ctrl=False,
                      **kwargs)
     
    @@ -733,23 +765,23 @@ defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";
    # UP5K has single port RAM.... # Use this as CPU RAM. spram_size = 128*1024
    -
    + -
    -

    Interacting with the CSR

    -
    csr_register,rgb_output,0xe0006800,1,rw
    -

    From test/csr.csv

    -
    +
    +

    Interacting with the CSR

    +
    csr_register,rgb_output,0xe0006800,1,rw
    +

    From test/csr.csv

    +
    -
    +

    VexRiscv

    -
    - -
    -

    Thank you

    -

    Lunch Time!

    -
    + + +
    +

    Thank you

    +

    Lunch Time!

    +