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< title > Fomu: An FPGA in your USB Port< / title >
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< meta name = "author" content = "Sean "xobs" Cross" >
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< div class = "url" > Slides: < a href = "https://p.xobs.io/td19/" > p.xobs.io/td19< / a > Software: < a href = "https://fomu.im/td19" > fomu.im/td19< / a > < / div >
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< span class = "theme" > Teardown 2019< / span > < span class = "hashtag" > | #teardown< / span > < span class = "twitter" > |
@crowd_supply< / span >
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< / div >
< div class = "slides" >
< section >
< h2 > Fomu: an FPGA in your USB Port< / h2 >
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< img src = "img/fomu-hacker-top-1.jpg" >
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< p >
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Pre-order now on Crowd Supply! < a href = "https://t.xobs.io/fomu" > t.xobs.io/fomu< / a >
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< / p >
< / section >
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< section data-background-image = "css/theme/teardown2019-title-bg-transparent.svg" >
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< h1 > Fomu: An FPGA in your USB Port< / h1 >
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< h4 > A whirlwind introduction to Fomu; a workshop in three levels< / h4 >
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< p align = "right" >
< small > Sean Cross - < a href = "https://xobs.io/" > https://xobs.io/< / a > - @xobs< / small >
< / p >
< / section >
< section >
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< h2 > Levels of Fomu< / h2 >
< p >
Fomu aims to be accessable on three levels:
< ol >
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< li > Python / Interpreter< / li >
< li > RISC-V / C< / li >
< li > FPGA / HDL< / li >
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< / ol >
< / p >
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< / section >
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< section >
< h2 > Workshop Outline< / h2 >
< ol >
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< li > What do I need to get started?< / li >
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< li > What is an FPGA, and what is Fomu?< / li >
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< li > Working with Fomu using Python, RISC-V, and HDL< / li >
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< / ol >
< / section >
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< section >
< section >
< h2 > What do I need to get started?< / h2 >
< ol >
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< li > DFU utilities< / li >
< li > Serial console< / li >
< li > RISC-V toolchain< / li >
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< li > FPGA Toolchain< / li >
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< li > Python 3< / li >
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< / ol >
< / section >
< / section >
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< section >
< section >
< h2 > What is an FPGA?< / h2 >
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< img data-src = "img/ice40-lut.png" alt = "SB_LUT4" >
<!--
< p >
An FPGA is a chip that executes logic.
< / p >
< p >
FPGAs are measured in resources called LUTs or LCs.
< / p >
-->
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< / section >
< section >
< h2 > What is an FPGA?< / h2 >
< table style = "transform: scale(.80) translate(-15%)" >
< tr >
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< / section >
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< section >
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< h2 > What is an FPGA?< / h2 >
< pre > < code class = "verilog" data-trim >
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module example (output reg [0:5] Q, input C);
reg [0:8] counter;
always @(posedge C)
begin
counter < = counter + 1'b1;
Q = counter[7] ^ counter[5] | counter< < 2 ;
end
endmodule
< / code > < / pre >
< img class = "fragment" data-src = "img/verilog-synthesis.png" alt = "Verilog Synthesis" >
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< / section >
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< section >
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< h2 > About the ICE40UP5K< / h2 >
< ol >
< li > 5280 4-input LUTs (LC)< / li >
< li > 16 kilobytes BRAM< / li >
< li class = "fragment highlight-blue" > 128 kilobytes "SPRAM"< / li >
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< li > Current-limited 3-channel LED driver< / li >
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< li > 2x I2C and 2x SPI< / li >
< li > 8 16-bit DSP units< / li >
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< li class = "fragment highlight-blue" > Warmboot capability< / li >
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< li class = "fragment highlight-blue" > Open toolchain< / li >
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< / ol >
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< / section >
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< section >
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< h2 > What is Fomu?< / h2 >
< ul >
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< li > ICE40UP5K< / li >
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< li > 2MB QSPI flash memory< / li >
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< li > Four edge-plated pads< / li >
< li > ESD protection< / li >
< li > USB implemented in HDL< / li >
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< li class = "fragment highlight-blue" > Fits in your USB port< / li >
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< / ul >
<!-- <p>
Fomu is an FPGA that fits in your USB port. It has foru buttons, 2 MB of SPI flash, an RGB LED, and an ICE40UP5K with 5280 LCs. It also has 128 kB of dedicated RAM, not counting the block RAM.
Unlike many other PCBs, Fomu does not have a separate USB controller chip. This means that any projects that want to use the USB port must include a USB softcore.
< / p > -->
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< / section >
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< section >
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< h2 > Fomu Block Design Diagram< / h2 >
< img data-src = "img/fomu-block-diagram.png" alt = "Fomu block diagram" >
< / section >
< section >
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< h2 > What is this PCB?< / h2 >
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< img data-src = "img/tomu-fpga-evt-1-small.jpg" alt = "Fomu EVT1" >
< h3 > Fomu EVT1< / h3 >
<!-- <p>
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This is Fomu EVT1. This is the original stretch prototype of Fomu. The schematics are the same, but much has changed:
* Name changed from Tomu-FPGA to Fomu
* Package changed from SG48 to WLCSP32
Additionally, some patches were needed to get this PCB working:
* SO-8 for SPI flash was too small
* Crystal footprint was upside-down
These are yours to take home with you!
Differences between EVT1 and EVT3:
* Silkscreen on Raspberry Pi header
* Populate Raspberry Pi header
* Add PMOD pins to touchpads
* Swap PMODa pins for I3C
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< / p > -->
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< / section >
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< section >
< h2 > Misleading Datasheets< / h2 >
< img data-src = "img/xtal-datasheet-icon.jpg" alt = "Footprint from Crystal" >
< / section >
< section >
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< h2 > What modifications does it have?< / h2 >
< ul >
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< li > Shorting out two zero-ohm resistors (R7, PU)< / li >
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< li > Programming SPI flash< / li >
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< li > Bending SPI flash pins inward (U4)< / li >
< li > Mounting crystal on its side (U7)< / li >
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< li > Attaching power to crystal< / li >
< / ul >
< / section >
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< section >
< h2 > Fomu SPI Flash Layout< / h2 >
< img data-src = "img/fomu-memory-layout.png" alt = "Fomu memory layout" >
<!-- <ol>
< li > Bootloader< / li >
< li > Recovery< / li >
< li > Magic constants< / li >
< li > Interpreters< / li >
< li > Updates< / li >
< / ol > -->
< / section >
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< / section >
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< section >
< section >
< h2 > Working with Fomu< / h2 >
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< / section >
< section >
< h2 > FAT Bootloader< / h2 >
< ul >
< li > Presents itself as a USB disk< / li >
< li > Drag and drop files to program< / li >
< li > Multiple interpreter support< / li >
< / ul >
< div >
< img data-src = "img/under-construction.gif" class = "fragment" >
< / div >
< / section >
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< section >
< h2 > "fail safe" bootloader< / h2 >
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Device Firmware Update - < strong > DFU< / strong >
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< / section >
< section >
< h2 > Updating Fomu< / h2 >
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< pre > < code > $ dfu-util -l
Found DFU: [1209:5bf0] name="Fomu DFU Bootloader v1.7.2"
$ dfu-util -D evt-installable.dfu
Download [========= ] 36% 38912 bytes
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Download done.
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$ dfu-util -l
Found DFU: [1209:5bf0] name="Fomu DFU Bootloader v1.8.1"
$< / code > < / pre >
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< / section >
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< / section >
< section >
< section >
< h2 > Python / Interpreted< / h2 >
< ol >
< li > < strong > Goal:< / strong > Multiple interpreters, auto-reload, USB disk interface< / li >
< li > < strong > Now:< / strong > MicroPython binary< / li >
< / ol >
< / section >
< section >
< h2 > Loading Programs onto Fomu< / h2 >
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< pre > < code >
$ dfu-util -l
Found DFU: [1209:5bf0] name="Fomu DFU Bootloader v1.8.1"
$ dfu-util -e # Boot current program
$ dfu-util -D new-image.dfu # Load new program< / code > < / pre >
< h3 class = "fragment" > u< code > 5b f0< / code > mu< / h3 >
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< / section >
< section >
< h2 > Loading MicroPython< / h2 >
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< pre > < code > $ dfu-util -D micropython-fomu.dfu< / code > < / pre >
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< / section >
< section >
< h2 > Connecting via serial< / h2 >
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< pre class = "fragment" > < code > screen /dev/cu.usbserial*< / code > < / pre >
< pre class = "fragment" > < code > screen /dev/ttyACM*< / code > < / pre >
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< pre class = "fragment" > < code > Tera Term< / code > < / pre >
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< pre class = "fragment" > < code > MicroPython v1.10-296-g0a5a77a on 2019-06-18; fomu with vexriscv
>>>< / code > < / pre >
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< / section >
< section >
< h2 > Interacting with Fomu< / h2 >
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< pre > < code class = "python" data-trim >
>>> import fomu
>>> rgb = fomu.rgb()
>>> rgb.mode("error")
>>>
< / code > < / pre >
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< / section >
< section >
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< h2 > Read SPI ID< / h2 >
< pre > < code class = "python" data-trim >
>>> spi = fomu.spi()
>>> hex(spi.id())
'0xc2152815'
>>>
< / code > < / pre >
< / section >
< section >
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< h2 > Memory-Mapped Registers< / h2 >
< pre > < code class = "cpp" > #define CSR_VERSION_MAJOR_ADDR 0xe0007000
#define CSR_VERSION_MINOR_ADDR 0xe0007004
#define CSR_VERSION_REVISION_ADDR 0xe0007008< / code > < / pre >
< pre class = "fragment" > < code class = "python" > >>> import machine
>>> machine.mem32[0xe0007000]
1
>>>< / code > < / pre >
< / section >
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< section >
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< h2 > RGB LED Driver reference< / h2 >
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< img data-src = "img/ice40-ledd.png" alt = "ICE40 LEDD registers" >
< pre class = "fragment" > < code class = "python" data-trim > >>> rgb.write_raw(0b0001, 255)
>>> rgb.write_raw(0b1010, 14)
>>> rgb.write_raw(0b1011, 1)
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>>> < / code > < / pre >
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< / section >
< section >
< h2 > Future Work< / h2 >
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< ul >
< li > CircuitPython< / li >
< li > eLua< / li >
< li > Espurino?< / li >
< / ul >
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< / section >
< / section >
< section >
< section >
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< h2 > RISC-V< / h2 >
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< / section >
< section >
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< h2 > LiteX Model< / h2 >
< img data-src = "img/litex-design.png" alt = "LiteX Design" >
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< / section >
< section >
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< h2 > Wishbone Bridge< / h2 >
< img data-src = "img/wishbone-usb-debug-bridge.png" alt = "Wishbone bridge" >
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< / section >
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< section >
< h2 > CPU is Optional< / h2 >
< ul >
< li > Multiple CPUs available< / li >
< li >
< ul >
< li > VexRiscv< / li >
< li > picorv32< / li >
< li > lm32< / li >
< li > ...< / li >
< / ul >
< / li >
< li > Also works just fine with no CPU< / li >
< / ul >
< / section >
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< section >
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< h2 > CSR Access< / h2 >
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< pre > < code class = "cpp" > #define CSR_VERSION_MAJOR_ADDR 0xe0007000
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#define CSR_VERSION_MAJOR_SIZE 1
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#define CSR_VERSION_MINOR_ADDR 0xe0007004
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#define CSR_VERSION_MINOR_SIZE 1
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#define CSR_VERSION_REVISION_ADDR 0xe0007008
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#define CSR_VERSION_REVISION_SIZE 1
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#define CSR_VERSION_GITREV_ADDR 0xe000700c
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#define CSR_VERSION_GITREV_SIZE 4
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#define CSR_VERSION_GITEXTRA_ADDR 0xe000701c
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#define CSR_VERSION_GITEXTRA_SIZE 2
< / code > < / pre >
Excerpt from < code > csr.h< / code >
< / section >
< section >
< h2 > Reading CPU Version< / h2 >
< pre > < code class = "sh" > $ wishbone-tool --pid 0x5bf0 0xe0007000
Value at e0007000: 00000001
$ wishbone-tool --pid 0x5bf0 0xe0007004
Value at e0007004: 00000008
$ wishbone-tool --pid 0x5bf0 0xe0007008
Value at e0007008: 00000001< / code > < / pre >
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< / section >
< section >
< h2 > Interacting with LEDD directly< / h2 >
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< img data-src = "img/ice40-ledd.png" alt = "ICE40 LEDD registers" >
< pre class = "fragment" > < code class = "cpp" > #define CSR_RGB_DAT_ADDR 0xe0006800L
#define CSR_RGB_ADDR_ADDR 0xe0006804L< / code > < / pre >
< pre class = "fragment" > < code > $ wishbone-tool --pid 0x5bf0 0xe0006804 1
$ wishbone-tool --pid 0x5bf0 0xe0006800 0xff< / code > < / pre >
2019-06-18 17:11:09 +00:00
< / section >
< section >
< h2 > Writing RISC-V Code< / h2 >
2019-06-20 02:36:17 +00:00
< pre > < code > $ make
CC ./src/main.c main.o
CC ./src/rgb.c rgb.o
CC ./src/time.c time.o
AS ./src/crt0-vexriscv.S crt0-vexriscv.o
LD riscv-blink.elf
OBJCOPY riscv-blink.bin
IHEX riscv-blink.ihex
$ < / code > < / pre >
2019-06-23 00:46:19 +00:00
< p >
From < code > riscv-blink< / code > directory in < code > teardown2019-workshop< / code >
< / p >
2019-06-18 17:11:09 +00:00
< / section >
2019-06-20 02:36:17 +00:00
< section >
< h2 > Modifying RISC-V Code< / h2 >
< pre > < code class = "diff" > --- a/riscv-blink/src/main.c
+++ b/riscv-blink/src/main.c
@@ -38,6 +38,7 @@ void isr(void) {
void main(void) {
rgb_init();
irq_setie(0);
+ rgb_write((100000/64000)-1, LEDDBR);
int i = 0;
while (1) {
i++;< / code > < / pre >
< / section >
< section >
< h2 > Other RISC-V Programs< / h2 >
riscv-usb-cdcacm: echo characters back after adding 1
< / section >
2019-06-18 17:11:09 +00:00
< / section >
< section >
< section >
< h2 > Hardware Description Language< / h2 >
< / section >
< section >
2019-06-20 02:36:17 +00:00
< h2 > Yosys and NextPNR< / h2 >
< ul >
< li > Timing Driven!< / li >
< / ul >
< pre > < code > Max frequency for clock 'clk12': 24.63 MHz (PASS at 12.00 MHz)
Max frequency for clock 'clk48_1': 60.66 MHz (PASS at 48.00 MHz)
Max frequency for clock 'clkraw': 228.05 MHz (PASS at 48.00 MHz)< / code > < / pre >
2019-06-18 17:11:09 +00:00
< / section >
< section >
2019-06-20 02:36:17 +00:00
< h2 > Blinking an LED< / h2 >
< pre > < code > $ make FOMU_REV=evt
...
20 warnings, 0 errors
PACK blink.bin
Built 'blink' for Fomu evt1
$ dfu-util -D blink.bin< / code > < / pre >
2019-06-18 17:11:09 +00:00
< / section >
< section >
2019-06-20 02:36:17 +00:00
< h2 > LiteX and MiGen< / h2 >
< ol >
< li > Define hardware in Python< / li >
< li > Evaluate Python to produce netlist< / li >
< li > Synthesize netlist to FPGA< / li >
< / ol >
2019-06-18 17:11:09 +00:00
< / section >
2019-06-20 02:36:17 +00:00
< section >
< h2 > lxbuildenv.py< / h2 >
< ol >
< li > Python environment using native interpreter< / li >
< li > Very stable, good for hardware projects< / li >
< li > Should work with system Python< / li >
< li > Runs on Linux, Windows, Raspberry Pi< / li >
< / ol >
< / section >
< section >
< h2 > Why do we need a CPU?< / h2 >
< img data-src = "img/litex-design.png" alt = "LiteX Design" >
< / section >
< section >
< h2 > What if we remove the CPU?< / h2 >
< ul >
< li > Workshop project has no CPU< / li >
< li > DummyUsb module automatically enumerates< / li >
< li > Wishbone Debug Bridge still accessible< / li >
< / ul >
< / section >
< section >
< h2 > Build Workshop Module< / h2 >
< pre > < code > $ python3 workshop.py --placer heap
...
5 warnings, 0 errors
$ < / code > < / pre >
< / section >
< section >
< h2 > Load onto Fomu< / h2 >
< pre > < code > $ dfu-util -D build/gateware/top.bin
Download [=========================] 100% 104090 bytes
Download done.
$ < / code > < / pre >
< / section >
< section >
< h2 > Write a value to RAM< / h2 >
< pre > < code > $ wishbone-tool --pid 0x5bf0 0x10000000
Value at 10000000: 0baf801e
$ wishbone-tool --pid 0x5bf0 0x10000000 0x12345678
$ wishbone-tool --pid 0x5bf0 0x10000000
Value at 10000000: 12345678
$ < / code > < / pre >
< / section >
2019-06-20 18:24:00 +00:00
< section >
< h2 > Adding Hardware< / h2 >
< img data-src = "img/ice40-rgb.jpg" alt = "Schematic of RGB block" >
< / section >
< section >
< h2 > Technology Library Reference< / h2 >
< pre > < code class = "verilog" > // Verilog Instantiation
SB_RGBA_DRV RGBA_DRIVER (
.CURREN(ENABLE_CURR),
.RGBLEDEN(ENABLE_RGBDRV),
.RGB0PWM(RGB0),
.RGB1PWM(RGB1),
.RGB2PWM(RGB2),
.RGB0(LED0),
.RGB1(LED1),
.RGB2(LED2)
);
defparam RGBA_DRIVER.CURRENT_MODE = "0b0";
defparam RGBA_DRIVER.RGB0_CURRENT = "0b111111";
defparam RGBA_DRIVER.RGB1_CURRENT = "0b111111" ;
defparam RGBA_DRIVER.RGB2_CURRENT = "0b111111";< / code > < / pre >
< p > SBTICETechnologyLibrary201504.pdf page 147< / p >
< / section >
< section >
< h2 > RGB Block< / h2 >
< pre > < code class = "python" style = "font-size: 18px; line-height: 22px" > class FomuRGB(Module, AutoCSR):
def __init__(self, pads):
self.output = CSRStorage(3)
self.specials += Instance("SB_RGBA_DRV",
i_CURREN = 0b1,
i_RGBLEDEN = 0b1,
i_RGB0PWM = self.output.storage[0],
i_RGB1PWM = self.output.storage[1],
i_RGB2PWM = self.output.storage[2],
o_RGB0 = pads.r,
o_RGB1 = pads.g,
o_RGB2 = pads.b,
p_CURRENT_MODE = "0b1",
p_RGB0_CURRENT = "0b000011",
p_RGB1_CURRENT = "0b000011",
p_RGB2_CURRENT = "0b000011",
)< / code > < / pre >
< / section >
2019-06-20 02:36:17 +00:00
2019-06-20 18:24:00 +00:00
< section >
< h2 > Instantiating FomuRGB< / h2 >
< pre > < code class = "diff" > @@ -55,6 +75,10 @@ class BaseSoC(SoCCore):
with_ctrl=False,
**kwargs)
+ # Add the LED driver block
+ led_pads = platform.request("rgb_led")
+ self.submodules.rgb = FomuRGB(led_pads)
+
# UP5K has single port RAM....
# Use this as CPU RAM.
spram_size = 128*1024< / code > < / pre >
< / section >
< section >
< h2 > Interacting with the CSR< / h2 >
< pre > < code > csr_register,rgb_output,0xe0006800,1,rw< / code > < / pre >
< p > From < code > test/csr.csv< / code > < / p >
< / section >
2019-06-20 02:36:17 +00:00
< section >
2019-06-18 17:11:09 +00:00
< h2 > VexRiscv< / h2 >
2019-06-16 17:48:01 +00:00
< / section >
2019-06-21 16:53:37 +00:00
< / section >
< section >
< h2 > Thank you< / h2 >
< h2 > Lunch Time!< / h2 >
< / section >
2019-06-16 15:39:06 +00:00
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