index: more rough outline

Signed-off-by: Sean Cross <sean@xobs.io>

index.html

@@ -118,15 +118,28 @@
 					<li>Blinkenlights</li>
 				</ol>
 			</section>
+
 			<section>
 				<h2>Workshop Outline</h2>
 				<ol>
+					<li>What do I need to get started?</li>
 					<li>What is Fomu, and what is an FPGA?</li>
 					<li>What can I do with Fomu?</li>
 					<li>What makes Fomu special?</li>
 				</ol>
 			</section>
 
+			<section>
+				<section>
+					<h2>What do I need to get started?</h2>
+					<ol>
+						<li>Synthesis</li>
+						<li>Place-and-Route</li>
+						<li>Packer</li>
+					</ol>
+				</section>
+			</section>
+
 			<section>
 				<section>
 					<h2>What is an FPGA?</h2>
@@ -137,6 +150,7 @@
 						FPGAs are measured in resources called LUTs or LCs.
 					</p>
 				</section>
+
 				<section>
 					<h2>What is Fomu?</h2>
 					<p>
@@ -145,6 +159,15 @@
 						Unlike many other PCBs, Fomu does not have a separate USB controller chip.  This means that any projects that want to use the USB port must include a USB softcore.
 					</p>
 				</section>
+
+				<section>
+					<h2>Fomu Block Design Diagram</h2>
+				</section>
+
+				<section>
+					<h2>ICE40 Features</h2>
+				</section>
+
 				<section>
 					<h2>What is this PCB?</h2>
 					<p>
@@ -168,16 +191,113 @@
 						* Swap PMODa pins for I3C
 					</p>
 				</section>
+
 				<section>
-					<h2>Levels of Fomu</h2>
-					<p>
-						Fomu aims to be accessable on three levels:
-						<ol>
-							<li>Python / Interpreted</li>
-							<li>RISC-V</li>
-							<li>Verilog / FPGA</li>
-						</ol>
-					</p>
+					<h2>What modifications does it have?</h2>
+					<ul>
+						<li>Shorting out two zero-ohm resistors</li>
+						<li>Programming SPI flash</li>
+						<li>Bending SPI flash pins inward</li>
+						<li>Mounting crystal on its side</li>
+						<li>Attaching power to crystal</li>
+					</ul>
+				</section>
+
+			</section>
+
+			<section>
+				<h2>Levels of Fomu</h2>
+				<p>
+					Fomu aims to be accessable on three levels:
+					<ol>
+						<li>Python / Interpreted</li>
+						<li>RISC-V</li>
+						<li>Verilog / FPGA</li>
+					</ol>
+				</p>
+			</section>
+			<section>
+				<section>
+					<h2>Python / Interpreted</h2>
+					<ol>
+						<li><strong>Goal:</strong> Multiple interpreters, auto-reload, USB disk interface</li>
+						<li><strong>Now:</strong> MicroPython binary</li>
+					</ol>
+				</section>
+
+				<section>
+					<h2>Loading Programs onto Fomu</h2>
+					<code>dfu-util -l</code>
+					<code>dfu-util -D update.bin</code>
+				</section>
+
+				<section>
+					<h2>Loading MicroPython</h2>
+					<code>dfu-util -D micropython.dfu</code>
+				</section>
+
+				<section>
+					<h2>Connecting via serial</h2>
+				</section>
+
+				<section>
+					<h2>Interacting with Fomu</h2>
+				</section>
+
+				<section>
+					<h2>RGB LEDD reference</h2>
+				</section>
+
+				<section>
+					<h2>Future Work</h2>
+					CircuitPython, etc.
+				</section>
+			</section>
+			<section>
+				<section>
+					<h2>RISC-V code</h2>
+				</section>
+
+				<section>
+					<h2>LiteX Machine Model</h2>
+				</section>
+
+				<section>
+					<h2>Wishbone Interface</h2>
+				</section>
+
+				<section>
+					<h2>Wishbone Bridge</h2>
+				</section>
+
+				<section>
+					<h2>Interacting with LEDD directly</h2>
+				</section>
+
+				<section>
+					<h2>Writing RISC-V Code</h2>
+				</section>
+			</section>
+
+			<section>
+				<section>
+					<h2>Hardware Description Language</h2>
+				</section>
+
+				<section>
+					<h2>Yosys and NextPNR</h2>
+				</section>
+
+				<section>
+					<h2>Blinking an LED</h2>
+				</section>
+
+				<section>
+					<h2>LiteX and MiGen</h2>
+				</section>
+
+				<section>
+					<h2>VexRiscv</h2>
 				</section>
 			</section>
 		</div>