Having a full regulator on VCCPLL causes the ESD network in the ICE40 to
freak out, dumping VCCPLL into GND and trying very hard to burn out the
regulator.
Replace it with a simple RC filter network, which is less clean but
results in a happier ESD network.
Signed-off-by: Sean Cross <sean@xobs.io>
Previously, we would end up shorting power to ground all the time
because the diodes were right on the marginal edge.
Signed-off-by: Sean Cross <sean@xobs.io>
Somehow, KiCad added these strings to the parts libraries, which
resulted in referencing a file that didn't exist.
Remove them.
Signed-off-by: Sean Cross <sean@xobs.io>
We probably don't need 10nF, because this won't do any very-high-speed
(>100 MHz) operations. We can think about putting them back in later,
space permitting.
Additionally, remove an extra bank of caps for one of the IO pads.
We'll double-up on capacitors there, which should be alright given the
close proximity and the fact that the only thing on that IO bank is
captouch.
Signed-off-by: Sean Cross <sean@xobs.io>
FPGAs are great, because if there's an alternate method that's easier to
route -- go for it! This modifies some of the connections to ease
routing constraints.
Signed-off-by: Sean Cross <sean@xobs.io>
This is the first cut of a schematic layout of DVT1.
It includes all the decoupling caps still. We'll need to see if they're
kept around.
Signed-off-by: Sean Cross <sean@xobs.io>
This removes much of the support debugging stuff from evt1. Still to
do:
- Assign footprints
- Figure out which PU resistor to include (if any)
- Figure out if we need to keep the USB buffering
- Remove extra decoupling caps
Signed-off-by: Sean Cross <sean@xobs.io>
Add a crystal, so we can test to make sure it works.
Also add a second regulator dedicated to VCCPLL in an effort to
cost-down the capacitor and large components that shouldn't be
necessary.
Signed-off-by: Sean Cross <sean@xobs.io>
