The VCCPLL line is extraordinarily sensitive to voltage rise times, and
appears to cause the FPGA to go into latchup very very easily.
As a result, the VCCPLL regulator burns all 250 mA of its budget
constantly, as the FPGA shunts VCCPLL to GND. This would be ideal
during an ESD event, but not ideal during normal operations.
Indicate the VCCPLL Regulator approach is DNP, and that the VCCPLL
Filter Network is preferred. Mostly because the regulator doesn't work
at all.
Signed-off-by: Sean Cross <sean@xobs.io>
For some reason, this pin was listed as a `power output`, which does not
appear to be the case. Due to this error, the DRC would fail when using
a regulator directly connected to the pin.
Mark this pin as a `power input` to fix this, since it's really where
power goes into the chip.
Signed-off-by: Sean Cross <sean@xobs.io>
