30b7610996
pcb: hook up more debug wires
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We have spare pins, so run more debug wires.
Many of these will probably get cut when doing the PCB layout.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-31 10:45:27 +08:00
7bbaa24233
hardware: update name of SPI Flash
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Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-31 10:36:52 +08:00
4fe5f8f629
hardware: sch: use raspberry pi header, rework signaling
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Rework the signaling to send everything to a Raspberry Pi header.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-31 10:36:01 +08:00
eb93c70f01
hardware: sch: restructure SPI Flash symbol
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It's much cleaner if we put power pins on one side and signal pins on
the other. This removes the ratsnest that was building up.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-31 10:35:19 +08:00
d99d091d95
pcb: schematic-cache: add Raspberry Pi, new SPI Flash
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This reworks the SPI Flash layout and adds the Raspberry Pi header.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-31 10:34:33 +08:00
6283435874
reference: evt1: publish final-final-final schematic
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It's final this time! I mean it!
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-31 10:33:49 +08:00
b7bcfc595b
reference: update evt1 schematic pdf
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This adds the `SPI Header`.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 23:47:17 +08:00
0973972464
hardware: pcb: add SPI debug header
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This will be used to program SPI during board bringup.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 22:28:08 +08:00
9cb4ba9a3d
reference: regenerate evt1 pdf
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Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 19:21:59 +08:00
78bb283bc6
hardware: sch: populate SPI, /RESET pullups
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It turns out these resistors are important.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 19:21:01 +08:00
ddb9948232
reference: add another fpga doc, xtal doc
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Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 19:16:30 +08:00
0c017aeb96
reference: update evt1 schematic
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This schematic reflects more options, including two crystals now and
more decoupling capacitors.
It also adds an option to power VCCPLL from a second 1.2V regulator.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 19:15:28 +08:00
f06ef4a7d5
hardware: sch: add crystal, VCCPLL regulator
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Add a crystal, so we can test to make sure it works.
Also add a second regulator dedicated to VCCPLL in an effort to
cost-down the capacitor and large components that shouldn't be
necessary.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 19:14:33 +08:00
76f7bf2548
pcb: sch: make ICE40 VCCPLL a power input
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For some reason, this pin was listed as a `power output`, which does not
appear to be the case. Due to this error, the DRC would fail when using
a regulator directly connected to the pin.
Mark this pin as a `power input` to fix this, since it's really where
power goes into the chip.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 19:13:32 +08:00
ab18c90450
hardware: sch: specify spinor part
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SPINOR parts are largely interchangeable. Pick one.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 17:09:11 +08:00
fd421b88ba
reference: re-re-export plot file
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The numbering may have changed things. Maybe.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 17:07:19 +08:00
c7bfc248af
pcb: sch: renumber schematic
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Renumber the schematic again, as things have shifted around a bit.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 17:06:04 +08:00
ab33b4a0a1
hardware: rename tomu-fpga to pcb
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This more closely reflects what it actually is.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 17:05:02 +08:00
6136a66e8e
reference: evt1: minor reworking of label positions
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Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 17:03:15 +08:00
b940b19cc6
reference: add datasheet for mems oscillator
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Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 17:02:41 +08:00
3e009d6f8b
hardware: pcb: add manufacturer and part numbers
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Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 16:57:17 +08:00
72df05fe68
README: convert from asciidoc to markdown
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The link mechanism for asciidoc is weird, and isn't working right now.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 16:40:21 +08:00
d256c39c83
LICENSE: add BSD 3-clause license
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It doesn't really make sense for PCBs, which will end up licensed under
a different scheme, but it will work for the source code that will end
up here.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 16:08:52 +08:00
270d90a21d
README: add file
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Add a simple README file describing the project.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 16:08:23 +08:00
bd65526f52
hardware: rename directory from pcb
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Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 16:08:06 +08:00
8a38ba4791
gitignore: ignore bak, bck, sym-lib-table
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Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 16:06:28 +08:00
a61337a472
pcb: sch: add tomu-fpga-cache.lib
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This file appears to be a local version of the schematic symbols used in
the .sch file, so add it.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 16:05:08 +08:00
8476a9b7f8
pcb: add tomu-fpga project file
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This has changed slightly, so add the updated version.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 16:04:36 +08:00
177fe7196f
reference: evt1: add schematic
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Add a schematic for EVT1, based on the most recent design.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 16:03:48 +08:00
7c83be8dd9
pcb: sch: finish evt1 schematic
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This should be a feature-complete schematic. Now to start on PCB
layout.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 16:02:55 +08:00
2cd2b204c2
reference: add more ICE40 documentation
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Add more reference docs for ICE40 parts.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 16:02:06 +08:00
b5152b0628
pcb: sch: initial beta draft
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This is the first feature-complete version of the schematic.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 13:25:22 +08:00
0213e5d7f7
reference: initial commit
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Add an initial commit of reference documentation.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 12:36:55 +08:00
7f378b02c0
initial commit
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Add work-in-progress files for Tomu ICE40 FPGA.
Signed-off-by: Sean Cross <sean@xobs.io >
2018-10-30 12:36:17 +08:00
