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tomu-fpga/hardware/pcb/tomu-fpga.kicad_pcb

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hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(kicad_pcb (version 20171130) (host pcbnew "(5.0.0)")
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(general
(thickness 2.4)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(drawings 55)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(tracks 1005)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(zones 0)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(modules 61)
(nets 70)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(48 B.Fab user hide)
(49 F.Fab user hide)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
(setup
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(last_trace_width 0.1524)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(user_trace_width 0.2)
(user_trace_width 0.3)
(user_trace_width 0.5)
(user_trace_width 0.8)
(user_trace_width 1)
(user_trace_width 2)
(user_trace_width 3)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(trace_clearance 0.1524)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(zone_clearance 0.154)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(zone_45_only yes)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(trace_min 0.1524)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6858)
(via_drill 0.3302)
(via_min_size 0.508)
(via_min_drill 0.254)
(uvia_size 0.6858)
(uvia_drill 0.3302)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.0508)
hardware: pcb: repour and connect wire in kicad The `VCCPLL` line was listed as "Not Connected" in KiCad. Reconnect it, even though it was already connected. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 03:33:41 +00:00
(solder_mask_min_width 0.25)
hardware: pcb: update drill offset, add mfg notes Add a note indicating the PCB thickness and color. Also, move the drill origin to the lower-left corner, to aid in machine assembly. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 05:48:45 +00:00
(aux_axis_origin 25 80)
pcb: remove usb silk, add more 5V vias Add more 5V vias near the 1.2V regulator, and replace a manual trace with a copper pour. This will increase the amount of copper going to both the 3.3V and 1.2V regulators, which should improve stability. While we're at it, remove an errant silk artifact on the USB connector. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 06:03:27 +00:00
(visible_elements 7FFFFFFF)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(pcbplotparams
hardware: pcb: update drill offset, add mfg notes Add a note indicating the PCB thickness and color. Also, move the drill origin to the lower-left corner, to aid in machine assembly. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 05:48:45 +00:00
(layerselection 0x012fc_ffffffff)
(usegerberextensions true)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
hardware: pcb: update drill offset, add mfg notes Add a note indicating the PCB thickness and color. Also, move the drill origin to the lower-left corner, to aid in machine assembly. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 05:48:45 +00:00
(drillshape 0)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(scaleselection 1)
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(outputdirectory "../releases/evt2/"))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
(net 0 "")
(net 1 +5V)
(net 2 GND)
(net 3 +3V3)
(net 4 +1V2)
(net 5 +2V5)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(net 6 "Net-(D1-Pad1)")
(net 7 /SPI_MOSI)
(net 8 /SPI_IO2)
(net 9 "Net-(J1-Pad17)")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 10 /DBG_1)
(net 11 /CRESET)
(net 12 /DBG_4)
(net 13 /CDONE)
(net 14 /UART_RX)
(net 15 /UART_TX)
(net 16 "Net-(J1-Pad1)")
(net 17 /SPI_CS)
(net 18 /OSC_IN)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(net 19 /ICE_USBN)
(net 20 /ICE_USBP)
(net 21 /SPI_MISO)
(net 22 /SPI_CLK)
(net 23 /SPI_IO3)
(net 24 "Net-(U1-Pad4)")
(net 25 "Net-(U2-Pad4)")
(net 26 "Net-(U3-Pad4)")
(net 27 "Net-(U8-Pad4)")
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 28 "Net-(J1-Pad36)")
(net 29 /VCCPLL)
(net 30 "Net-(SW3-Pad1)")
(net 31 "Net-(SW4-Pad1)")
(net 32 /LED_R)
(net 33 /LED_G)
(net 34 /LED_B)
(net 35 "Net-(U5-Pad43)")
(net 36 "Net-(U5-Pad32)")
(net 37 "Net-(J1-Pad38)")
(net 38 "Net-(J1-Pad35)")
(net 39 "Net-(J1-Pad33)")
(net 40 "Net-(J1-Pad32)")
(net 41 "Net-(J1-Pad31)")
(net 42 "Net-(J1-Pad29)")
(net 43 "Net-(J1-Pad28)")
(net 44 "Net-(J1-Pad27)")
(net 45 "Net-(U5-Pad31)")
(net 46 "Net-(J1-Pad40)")
(net 47 "Net-(J1-Pad37)")
(net 48 /PU_CTRL_USBP)
(net 49 /PU_CTRL_USBN)
(net 50 "Net-(U5-Pad2)")
(net 51 "Net-(U5-Pad3)")
(net 52 "Net-(U5-Pad4)")
(net 53 "Net-(U5-Pad6)")
(net 54 "Net-(J1-Pad16)")
(net 55 /PMOD_4)
(net 56 /PMOD_2)
(net 57 /PMOD_3)
(net 58 /PMOD_1)
(net 59 "Net-(U7-Pad1)")
(net 60 "Net-(D8-Pad1)")
(net 61 "Net-(D7-Pad1)")
(net 62 "Net-(D5-Pad1)")
(net 63 "Net-(D4-Pad1)")
(net 64 "Net-(D3-Pad1)")
(net 65 "Net-(D2-Pad1)")
(net 66 /DBG_2)
(net 67 /DBG_3)
(net 68 /DBG_5)
(net 69 /DBG_6)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net_class Default "This is the default net class."
(clearance 0.1524)
(trace_width 0.1524)
(via_dia 0.6858)
(via_drill 0.3302)
(uvia_dia 0.6858)
(uvia_drill 0.3302)
(diff_pair_gap 0.0254)
(diff_pair_width 0.1524)
(add_net +1V2)
(add_net +2V5)
(add_net +3V3)
(add_net +5V)
(add_net /CDONE)
(add_net /CRESET)
(add_net /DBG_1)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(add_net /DBG_2)
(add_net /DBG_3)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(add_net /DBG_4)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(add_net /DBG_5)
(add_net /DBG_6)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(add_net /ICE_USBN)
(add_net /ICE_USBP)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(add_net /LED_B)
(add_net /LED_G)
(add_net /LED_R)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(add_net /OSC_IN)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(add_net /PMOD_1)
(add_net /PMOD_2)
(add_net /PMOD_3)
(add_net /PMOD_4)
(add_net /PU_CTRL_USBN)
(add_net /PU_CTRL_USBP)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(add_net /SPI_CLK)
(add_net /SPI_CS)
(add_net /SPI_IO2)
(add_net /SPI_IO3)
(add_net /SPI_MISO)
(add_net /SPI_MOSI)
(add_net /UART_RX)
(add_net /UART_TX)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(add_net /VCCPLL)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(add_net GND)
(add_net "Net-(D1-Pad1)")
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(add_net "Net-(D2-Pad1)")
(add_net "Net-(D3-Pad1)")
(add_net "Net-(D4-Pad1)")
(add_net "Net-(D5-Pad1)")
(add_net "Net-(D7-Pad1)")
(add_net "Net-(D8-Pad1)")
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(add_net "Net-(J1-Pad1)")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(add_net "Net-(J1-Pad16)")
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(add_net "Net-(J1-Pad17)")
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(add_net "Net-(J1-Pad27)")
(add_net "Net-(J1-Pad28)")
(add_net "Net-(J1-Pad29)")
(add_net "Net-(J1-Pad31)")
(add_net "Net-(J1-Pad32)")
(add_net "Net-(J1-Pad33)")
(add_net "Net-(J1-Pad35)")
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(add_net "Net-(J1-Pad36)")
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(add_net "Net-(J1-Pad37)")
(add_net "Net-(J1-Pad38)")
(add_net "Net-(J1-Pad40)")
(add_net "Net-(SW3-Pad1)")
(add_net "Net-(SW4-Pad1)")
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(add_net "Net-(U1-Pad4)")
(add_net "Net-(U2-Pad4)")
(add_net "Net-(U3-Pad4)")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(add_net "Net-(U5-Pad2)")
(add_net "Net-(U5-Pad3)")
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(add_net "Net-(U5-Pad31)")
(add_net "Net-(U5-Pad32)")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(add_net "Net-(U5-Pad4)")
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(add_net "Net-(U5-Pad43)")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(add_net "Net-(U5-Pad6)")
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(add_net "Net-(U7-Pad1)")
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(add_net "Net-(U8-Pad4)")
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(module tomu-fpga:TVM-12V (layer F.Cu) (tedit 5BF411C5) (tstamp 5C01E6FD)
(at 97 38.75 135)
(path /5C191C29)
(fp_text reference D6 (at 2.474874 0 225) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.15)))
)
(fp_text value D_Small (at 0 -1.5 135) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.9 0.8) (end -1.9 -0.8) (layer F.CrtYd) (width 0.15))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(fp_line (start 1.9 0.8) (end -1.9 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start 1.9 -0.8) (end 1.9 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start -1.9 -0.8) (end 1.9 -0.8) (layer F.CrtYd) (width 0.15))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 2 smd roundrect (at 1.05 0 135) (size 1.2 1.2) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(pad 1 smd roundrect (at -1.05 0 135) (size 1.2 1.2) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 1 +5V))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(model ${KISYS3DMOD}/Diode_SMD.3dshapes/D_SMB.step
(at (xyz 0 0 0))
(scale (xyz 0.7 0.5 0.5))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(module tomu-fpga:TVM-5V (layer F.Cu) (tedit 5BF7B758) (tstamp 5C02FE4A)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(at 103 45 315)
(path /5C19202D)
(fp_text reference D8 (at 2.12132 0 45) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.15)))
)
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(fp_text value D_Small (at 0.300001 -1.7 315) (layer F.Fab)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.5 -0.8) (end 1.5 -0.8) (layer F.CrtYd) (width 0.15))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(fp_line (start 1.5 -0.8) (end 1.5 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start 1.5 0.8) (end -1.5 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start -1.5 0.8) (end -1.5 -0.8) (layer F.CrtYd) (width 0.15))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 1 smd roundrect (at -1 0 315) (size 0.7 1.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 60 "Net-(D8-Pad1)"))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(pad 2 smd roundrect (at 1 0 315) (size 0.7 1.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Diode_SMD.3dshapes/D_0805_2012Metric.step
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
)
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(module tomu-fpga:TVM-5V (layer F.Cu) (tedit 5BF7B758) (tstamp 5C01B685)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(at 45 48 180)
(path /5C0A0D6F)
(fp_text reference D2 (at 3.25 0 180) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.15)))
)
(fp_text value D_Small (at 0.3 -1.7 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.5 -0.8) (end 1.5 -0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start 1.5 -0.8) (end 1.5 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start 1.5 0.8) (end -1.5 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start -1.5 0.8) (end -1.5 -0.8) (layer F.CrtYd) (width 0.15))
(pad 1 smd roundrect (at -1 0 180) (size 0.7 1.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 65 "Net-(D2-Pad1)"))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 2 smd roundrect (at 1 0 180) (size 0.7 1.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(model ${KISYS3DMOD}/Diode_SMD.3dshapes/D_0805_2012Metric.step
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
)
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(module tomu-fpga:TVM-5V (layer F.Cu) (tedit 5BF7B758) (tstamp 5C01B67B)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(at 44.75 45.75 180)
(path /5C0A1030)
(fp_text reference D3 (at 3 0 180) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.15)))
)
(fp_text value D_Small (at 0.3 -1.7 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.5 -0.8) (end 1.5 -0.8) (layer F.CrtYd) (width 0.15))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(fp_line (start 1.5 -0.8) (end 1.5 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start 1.5 0.8) (end -1.5 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start -1.5 0.8) (end -1.5 -0.8) (layer F.CrtYd) (width 0.15))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 1 smd roundrect (at -1 0 180) (size 0.7 1.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 64 "Net-(D3-Pad1)"))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(pad 2 smd roundrect (at 1 0 180) (size 0.7 1.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Diode_SMD.3dshapes/D_0805_2012Metric.step
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
)
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(module tomu-fpga:TVM-5V (layer F.Cu) (tedit 5BF7B758) (tstamp 5C01EEBE)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(at 49.5 44.75 180)
(path /5C0A10BA)
(fp_text reference D4 (at 0 -1.75 180) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.15)))
)
(fp_text value D_Small (at 0.3 -1.7 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.5 -0.8) (end 1.5 -0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start 1.5 -0.8) (end 1.5 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start 1.5 0.8) (end -1.5 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start -1.5 0.8) (end -1.5 -0.8) (layer F.CrtYd) (width 0.15))
(pad 1 smd roundrect (at -1 0 180) (size 0.7 1.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 63 "Net-(D4-Pad1)"))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 2 smd roundrect (at 1 0 180) (size 0.7 1.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(model ${KISYS3DMOD}/Diode_SMD.3dshapes/D_0805_2012Metric.step
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
)
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(module tomu-fpga:TVM-5V (layer F.Cu) (tedit 5BF7B758) (tstamp 5C01B667)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(at 55.25 45.25)
(path /5C0A1146)
(fp_text reference D5 (at 0 1.7) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.15)))
)
(fp_text value D_Small (at 0.3 -1.7) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.5 -0.8) (end 1.5 -0.8) (layer F.CrtYd) (width 0.15))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(fp_line (start 1.5 -0.8) (end 1.5 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start 1.5 0.8) (end -1.5 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start -1.5 0.8) (end -1.5 -0.8) (layer F.CrtYd) (width 0.15))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 1 smd roundrect (at -1 0) (size 0.7 1.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 62 "Net-(D5-Pad1)"))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(pad 2 smd roundrect (at 1 0) (size 0.7 1.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Diode_SMD.3dshapes/D_0805_2012Metric.step
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
)
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(module tomu-fpga:TVM-5V (layer F.Cu) (tedit 5BF7B758) (tstamp 5C01B65D)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(at 100.5 42.5 315)
(path /5C191F91)
(fp_text reference D7 (at -2.12132 0 225) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.15)))
)
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(fp_text value D_Small (at 0.300001 -1.7 315) (layer F.Fab)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.5 -0.8) (end 1.5 -0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start 1.5 -0.8) (end 1.5 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start 1.5 0.8) (end -1.5 0.8) (layer F.CrtYd) (width 0.15))
(fp_line (start -1.5 0.8) (end -1.5 -0.8) (layer F.CrtYd) (width 0.15))
(pad 1 smd roundrect (at -1 0 315) (size 0.7 1.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 61 "Net-(D7-Pad1)"))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 2 smd roundrect (at 1 0 315) (size 0.7 1.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(model ${KISYS3DMOD}/Diode_SMD.3dshapes/D_0805_2012Metric.step
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
)
(module tomu-fpga:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951E7) (tstamp 5BF35D28)
(at 38.75 60.82 270)
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor handsolder")
(path /5BFD305D)
hardware: pcb: fix `virtual` and `smd` designation Some components were getting added to the BOM that shouldn't have been, and some were missing from the pick-and-place file. Update the `Placement Type` to be accurate according to assembly. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 03:32:32 +00:00
(attr smd)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_text reference R13 (at -2.62 -3.05) (layer F.SilkS)
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_text value "0805, 10k, 1/16W (DNP)" (at 0 1.65 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 1.025 0 270) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 17 /SPI_CS))
(pad 1 smd roundrect (at -1.025 0 270) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 2 GND))
(model ${KIPRJMOD}/tomu-fpga.pretty/R_0805_HandSoldering.wrl
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(at (xyz 0 0 0))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(scale (xyz 1 1 1))
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(rotate (xyz 0 0 0))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(module tomu-fpga:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951E7) (tstamp 5BF35C98)
(at 41.75 60.8 90)
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor handsolder")
(path /5C493DB2)
(attr smd)
(fp_text reference R3 (at 2.5 -2.95 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "0805, 10k, 1/16W" (at 0 1.65 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 2 smd roundrect (at 1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 3 +3V3))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(pad 1 smd roundrect (at -1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 17 /SPI_CS))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/R_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(module tomu-fpga:XTAL-2520 (layer F.Cu) (tedit 5BF9B13B) (tstamp 5BF28B82)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(at 74 52.4 180)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5C0E8D0F)
hardware: pcb: replace "text" with "value" for buttons Previously, we used text to display the "5" and "6" designators for the physical buttons. Replace this with a value of "5" and "6", and remove the extra text. Additionally, display "SW??" under the switch, to make hand-assembly easier. Do the same thing for the "Reset" button. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:12:13 +00:00
(attr smd)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_text reference U7 (at -1 1.8 180) (layer F.SilkS)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(effects (font (size 0.5 0.5) (thickness 0.1)))
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_text value "Crystal Oscillator" (at 0 1.7 180) (layer F.Fab)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(effects (font (size 0.2 0.2) (thickness 0.05)))
)
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(fp_line (start -1.5 -1.3) (end 1.5 -1.3) (layer F.CrtYd) (width 0.03))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_line (start 1.5 -1.3) (end 1.5 1.3) (layer F.CrtYd) (width 0.03))
(fp_line (start 1.5 1.3) (end -1.5 1.3) (layer F.CrtYd) (width 0.03))
(fp_line (start -1.5 1.3) (end -1.5 -1.3) (layer F.CrtYd) (width 0.03))
(fp_circle (center -1.825 1.25) (end -1.683579 1.25) (layer F.SilkS) (width 0.3))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(pad 2 smd rect (at 0.925 0.725) (size 0.9 0.8) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 3 smd rect (at 0.925 -0.725) (size 0.9 0.8) (layers F.Cu F.Paste F.Mask)
(net 18 /OSC_IN))
(pad 4 smd rect (at -0.925 -0.725) (size 0.9 0.8) (layers F.Cu F.Paste F.Mask)
(net 3 +3V3))
(pad 1 smd rect (at -0.925 0.725) (size 0.9 0.8) (layers F.Cu F.Paste F.Mask)
(net 59 "Net-(U7-Pad1)"))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/Oscillator_SMD_TCXO_G158.wrl
(at (xyz 0 0 0))
(scale (xyz 0.1 0.2 0.1))
(rotate (xyz 0 0 0))
)
)
(module tomu-fpga:SPST-NO-Button (layer F.Cu) (tedit 5BF2D514) (tstamp 5BED8C7C)
(at 32 60 270)
(path /5D126443)
(attr smd)
(fp_text reference SW1 (at -0.2 -0.1 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(fp_text value Reset (at 0 4 90) (layer F.SilkS)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(effects (font (size 1.5 1.5) (thickness 0.2)))
)
(fp_line (start -4.6 3) (end -4.6 -3.1) (layer F.CrtYd) (width 0.2))
(fp_line (start 4.6 3) (end -4.6 3) (layer F.CrtYd) (width 0.2))
(fp_line (start 4.6 -3.1) (end 4.6 3) (layer F.CrtYd) (width 0.2))
(fp_line (start -4.6 -3.1) (end 4.6 -3.1) (layer F.CrtYd) (width 0.2))
(fp_line (start -1 -2.8) (end 0.7 -2.8) (layer F.SilkS) (width 0.2))
(fp_line (start 4.3 1) (end 4.3 -1.1) (layer F.SilkS) (width 0.2))
(fp_line (start -1 2.7) (end 0.7 2.7) (layer F.SilkS) (width 0.2))
(fp_line (start -4.3 1) (end -4.3 -1.1) (layer F.SilkS) (width 0.2))
(pad 1 smd rect (at -3.2 -1.9 270) (size 1.6 1) (layers F.Cu F.Paste F.Mask)
(net 11 /CRESET) (solder_mask_margin 0.07))
(pad 3 smd rect (at -3.2 1.9 270) (size 1.6 1) (layers F.Cu F.Paste F.Mask)
(net 2 GND) (solder_mask_margin 0.07))
(pad 2 smd rect (at 3.2 -1.9 270) (size 1.6 1) (layers F.Cu F.Paste F.Mask)
(net 11 /CRESET) (solder_mask_margin 0.07))
(pad 4 smd rect (at 3.2 1.9 270) (size 1.6 1) (layers F.Cu F.Paste F.Mask)
(net 2 GND) (solder_mask_margin 0.07))
(model ${KIPRJMOD}/tomu-fpga.pretty/SW_SPST_PTS645.wrl
(at (xyz 0 0 0))
(scale (xyz 0.8 0.8 0.2))
(rotate (xyz 0 0 0))
)
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(module tomu-fpga:SOIC-8 (layer F.Cu) (tedit 5BF9B116) (tstamp 5BED8CFA)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(at 43 67 270)
(path /5C1645BF)
(attr smd)
(fp_text reference U4 (at 3.75 0) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "SPI Flash" (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_circle (center -1.95 5.45) (end -1.825 5.425) (layer F.SilkS) (width 0.4))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_line (start -1.905 2.6) (end -2.705 1.8) (layer F.SilkS) (width 0.15))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_line (start -2.7 1.8) (end -2.7 -2.7) (layer F.SilkS) (width 0.15))
(fp_line (start -2.705 -2.7) (end 2.7 -2.7) (layer F.SilkS) (width 0.15))
(fp_line (start 2.7 -2.7) (end 2.7 2.6) (layer F.SilkS) (width 0.15))
(fp_line (start 2.7 2.6) (end -1.905 2.6) (layer F.SilkS) (width 0.15))
(fp_line (start -2.9 -3.9) (end 2.9 -3.9) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.9 -3.9) (end 2.9 4) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.9 4) (end -2.9 4) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.9 4) (end -2.9 -3.9) (layer F.CrtYd) (width 0.05))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 8 smd rect (at -1.905 -3.6 270) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 3 +3V3))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 1 smd rect (at -1.905 3.5 270) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 17 /SPI_CS))
(pad 7 smd rect (at -0.635 -3.6 270) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 23 /SPI_IO3))
(pad 2 smd rect (at -0.635 3.5 270) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 21 /SPI_MISO))
(pad 6 smd rect (at 0.6 -3.6 270) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 22 /SPI_CLK))
(pad 3 smd rect (at 0.635 3.5 270) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 8 /SPI_IO2))
(pad 5 smd rect (at 1.9 -3.6 270) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 7 /SPI_MOSI))
(pad 4 smd rect (at 1.9 3.5 270) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/SOIC-8-1EP_3.9x4.9mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1.3 1 1))
(rotate (xyz 0 0 -90))
)
)
(module tomu-fpga:SPST-NO-Button (layer F.Cu) (tedit 5BF2D514) (tstamp 5BED8C6C)
(at 88 37 180)
(path /5C1DD9BA)
(attr smd)
(fp_text reference SW3 (at -0.25 -0.25 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 6 (at 0 -6 180) (layer F.SilkS)
(effects (font (size 2 2) (thickness 0.25)))
)
(fp_line (start -4.6 3) (end -4.6 -3.1) (layer F.CrtYd) (width 0.2))
(fp_line (start 4.6 3) (end -4.6 3) (layer F.CrtYd) (width 0.2))
(fp_line (start 4.6 -3.1) (end 4.6 3) (layer F.CrtYd) (width 0.2))
(fp_line (start -4.6 -3.1) (end 4.6 -3.1) (layer F.CrtYd) (width 0.2))
(fp_line (start -1 -2.8) (end 0.7 -2.8) (layer F.SilkS) (width 0.2))
(fp_line (start 4.3 1) (end 4.3 -1.1) (layer F.SilkS) (width 0.2))
(fp_line (start -1 2.7) (end 0.7 2.7) (layer F.SilkS) (width 0.2))
(fp_line (start -4.3 1) (end -4.3 -1.1) (layer F.SilkS) (width 0.2))
(pad 1 smd rect (at -3.2 -1.9 180) (size 1.6 1) (layers F.Cu F.Paste F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 30 "Net-(SW3-Pad1)") (solder_mask_margin 0.07))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 3 smd rect (at -3.2 1.9 180) (size 1.6 1) (layers F.Cu F.Paste F.Mask)
(net 2 GND) (solder_mask_margin 0.07))
(pad 2 smd rect (at 3.2 -1.9 180) (size 1.6 1) (layers F.Cu F.Paste F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 30 "Net-(SW3-Pad1)") (solder_mask_margin 0.07))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 4 smd rect (at 3.2 1.9 180) (size 1.6 1) (layers F.Cu F.Paste F.Mask)
(net 2 GND) (solder_mask_margin 0.07))
(model ${KIPRJMOD}/tomu-fpga.pretty/SW_SPST_PTS645.wrl
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(at (xyz 0 0 0))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(scale (xyz 0.8 0.8 0.2))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(rotate (xyz 0 0 0))
)
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(module tomu-fpga:LED-RGB-5DS-UHD1110-FKA (layer F.Cu) (tedit 5BEA352D) (tstamp 5BED8E9C)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(at 76.6 53 180)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(path /5BD90F18)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_text reference U10 (at -0.1 0.8 180) (layer F.SilkS)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(effects (font (size 0.2 0.2) (thickness 0.05)))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_text value RGB-LED (at 0.1 -0.7 180) (layer F.Fab)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(effects (font (size 0.2 0.2) (thickness 0.05)))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_circle (center -0.8 -0.3) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.6 0.6) (end -0.6 -0.6) (layer F.CrtYd) (width 0.03))
(fp_line (start 0.6 0.6) (end -0.6 0.6) (layer F.CrtYd) (width 0.03))
(fp_line (start 0.6 -0.6) (end 0.6 0.6) (layer F.CrtYd) (width 0.03))
(fp_line (start -0.6 -0.6) (end 0.6 -0.6) (layer F.CrtYd) (width 0.03))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 4 smd rect (at 0.3 0.3 180) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(net 3 +3V3))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 3 smd rect (at -0.3 0.3 180) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 32 /LED_R))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 2 smd rect (at 0.3 -0.3 180) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 33 /LED_G))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 1 smd rect (at -0.3 -0.3 180) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 34 /LED_B))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(model ${KISYS3DMOD}/LEDs.3dshapes/LED_WS2812B-PLCC4.wrl
(offset (xyz 0 0 -0.03))
(scale (xyz 0.07000000000000001 0.07000000000000001 0.05))
(rotate (xyz 0 0 0))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
)
(module tomu-fpga:MEMS-20005625B (layer F.Cu) (tedit 5BEA34F1) (tstamp 5BED8E7B)
(at 71.6 52 270)
(path /5BDD6B36)
(fp_text reference U6 (at 0.2 1.1 270) (layer F.SilkS)
(effects (font (size 0.5 0.5) (thickness 0.1)))
)
(fp_text value "MEMS Oscillator (DNP)" (at 0.3 2.2 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.25)))
)
(fp_circle (center -1.1 0.4) (end -1.1 0.3) (layer F.SilkS) (width 0.15))
(fp_line (start -0.9 0.7) (end -0.9 -0.7) (layer F.CrtYd) (width 0.03))
(fp_line (start 1 0.7) (end -0.9 0.7) (layer F.CrtYd) (width 0.03))
(fp_line (start 1 -0.7) (end 1 0.7) (layer F.CrtYd) (width 0.03))
(fp_line (start -0.9 -0.7) (end 1 -0.7) (layer F.CrtYd) (width 0.03))
(pad 1 smd rect (at -0.705 0.31 270) (size 0.13 0.37) (layers F.Cu F.Paste F.Mask)
(net 3 +3V3))
(pad 1 smd trapezoid (at -0.641 0.56 90) (size 0.13 0.13) (rect_delta 0 0.129 ) (layers F.Cu F.Paste F.Mask)
(net 3 +3V3))
(pad 4 smd rect (at -0.6 -0.375 270) (size 0.35 0.5) (layers F.Cu F.Paste F.Mask)
(net 3 +3V3))
(pad 3 smd rect (at 0.6 -0.375 270) (size 0.35 0.5) (layers F.Cu F.Paste F.Mask)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(net 18 /OSC_IN))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 2 smd rect (at 0.6 0.375 270) (size 0.35 0.5) (layers F.Cu F.Paste F.Mask)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd rect (at -0.49 0.375 270) (size 0.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 3 +3V3))
(model ${KISYS3DMOD}/Oscillators.3dshapes/Oscillator_SMD_TCXO_G158.wrl
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(at (xyz 0 0 0))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(scale (xyz 0.06 0.1 0.05))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(rotate (xyz 0 0 0))
)
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(module tomu-fpga:LED_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BEA3470) (tstamp 5BED8E8F)
(at 83 77 180)
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "LED handsolder")
(path /5D1C64EF)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_text reference D1 (at 2.9 -0.1 180) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_text value "Power LED" (at 0 1.65 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_circle (center -2.2 0) (end -2.2 -0.1) (layer F.SilkS) (width 0.15))
(fp_text user %R (at 0 0 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start -1.86 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.86 -0.96) (end -1.86 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.86 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 5 +2V5))
(pad 1 smd roundrect (at -1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 6 "Net-(D1-Pad1)"))
(model ${KIPRJMOD}/tomu-fpga.pretty/LED_0805.wrl
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(module tomu-fpga:Pin_Header_Straight_1x06_Pitch2.54mm (layer F.Cu) (tedit 5BEA3925) (tstamp 5C05D444)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(at 95.56 77.7 90)
(descr "Through hole straight pin header, 1x06, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x06 2.54mm single row")
(path /5EC9746F)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_text reference J3 (at 0 -2.33 90) (layer F.SilkS) hide
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_text value PMOD (at 0 15.03 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_text user %R (at 0 6.35 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 14.5) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 14.5) (end 1.8 14.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 14.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 14.03) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 14.03) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 14.03) (end 1.33 14.03) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 13.97) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 13.97) (end -1.27 13.97) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 13.97) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 3 +3V3))
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 2 GND))
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 55 /PMOD_4))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 57 /PMOD_3))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 56 /PMOD_2))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 58 /PMOD_1))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
)
(module tomu-fpga:USB-B (layer F.Cu) (tedit 5BDC3E7B) (tstamp 5BED8C50)
(at 105.605887 39.294365 135)
(path /5BD8B24F)
(solder_mask_margin 0.000001)
(solder_paste_margin 0.000001)
(clearance 0.000001)
(fp_text reference U9 (at 3 2 135) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value USB-B (at -2 2 135) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -5.8 8) (end 5.8 8) (layer F.CrtYd) (width 0.3))
(fp_line (start 5.8 8) (end 5.8 -3.8) (layer F.CrtYd) (width 0.3))
(fp_line (start 5.8 -3.8) (end -5.8 -3.8) (layer F.CrtYd) (width 0.3))
(fp_line (start -5.8 -3.8) (end -5.8 8) (layer F.CrtYd) (width 0.3))
(pad 1 smd trapezoid (at 3.5 6.7 315) (size 1.375 1.3) (rect_delta 0 1.374 ) (layers F.Cu F.Mask)
(net 1 +5V) (solder_mask_margin 0.000001) (solder_paste_margin 0.000001) (clearance 0.000001) (zone_connect 2) (thermal_width 0.000001) (thermal_gap 0.000001))
(pad 1 smd rect (at 2.8 6.699999 315) (size 1.375 1.3) (layers F.Cu F.Mask)
(net 1 +5V) (solder_mask_margin 0.000001) (solder_paste_margin 0.000001) (clearance 0.000001) (zone_connect 2) (thermal_width 0.000001) (thermal_gap 0.000001))
(pad 4 smd rect (at -2.81 6.699999 315) (size 1.375 1.3) (layers F.Cu F.Mask)
(net 2 GND) (solder_mask_margin 0.000001) (solder_paste_margin 0.000001) (clearance 0.000001) (zone_connect 2) (thermal_width 0.000001) (thermal_gap 0.000001))
(pad 4 smd trapezoid (at -3.5 6.7 315) (size 1.375 1.3) (rect_delta 0 1.374 ) (layers F.Cu F.Mask)
(net 2 GND) (solder_mask_margin 0.000001) (solder_paste_margin 0.000001) (clearance 0.000001) (zone_connect 2) (thermal_width 0.000001) (thermal_gap 0.000001))
(pad 3 smd rect (at -1 3 315) (size 1.75 6.41) (layers F.Cu F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 60 "Net-(D8-Pad1)") (solder_mask_margin 0.000001) (solder_paste_margin 0.000001) (clearance 0.000001))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 2 smd rect (at 1 3 315) (size 1.75 6.41) (layers F.Cu F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 61 "Net-(D7-Pad1)") (solder_mask_margin 0.000001) (solder_paste_margin 0.000001) (clearance 0.000001))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd rect (at 3.5 1.3 315) (size 2.75 9.5) (layers F.Cu F.Mask)
(net 1 +5V) (solder_mask_margin 0.000001) (solder_paste_margin 0.000001) (clearance 0.000001))
(pad 4 smd rect (at -3.5 1.3 315) (size 2.75 9.5) (layers F.Cu F.Mask)
(net 2 GND) (solder_mask_margin 0.000001) (solder_paste_margin 0.000001) (clearance 0.000001) (zone_connect 2) (thermal_width 0.000001) (thermal_gap 0.000001))
)
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED9067)
(at 79 67)
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
(path /5BECECF0)
(attr smd)
(fp_text reference C27 (at 3.5 0) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "0805, 10nF, 10V, X5R, 20%" (at 0 1.65) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 2 GND))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 1 smd roundrect (at -1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 5 +2V5))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED9056)
(at 84 51)
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
(path /5C7EE944)
(attr smd)
(fp_text reference C26 (at 3.5 0) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "0805, 10nF, 10V, X5R, 20%" (at 0 1.65) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 2 GND))
(pad 1 smd roundrect (at -1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 3 +3V3))
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED9045)
(at 79 69)
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
(path /5BECED7C)
(attr smd)
(fp_text reference C25 (at 3.5 0) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "0805, 1uF, 10V, X5R, 20%" (at 0 1.65) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 5 +2V5))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED9034)
(at 84 49)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5C7EE93E)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C24 (at 3.5 0) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 1uF, 10V, X5R, 20%" (at 0 1.65) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 1 smd roundrect (at -1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 3 +3V3))
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED9023)
(at 87 62 270)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BE5ACB9)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C23 (at -3.5 0 270) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(fp_text value "0805, 100nF, 10V, X5R, 20%" (at 0 1.65 270) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 270) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0 270) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 29 /VCCPLL))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED9012)
(at 89 62.025 90)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BE5AF99)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C22 (at 3.525 0 90) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(fp_text value "0805, 10uF, 10V, X5R, 20%" (at 0 1.65 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 29 /VCCPLL))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 1 smd roundrect (at -1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED9001)
(at 79 71)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5C52D560)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C21 (at 3.5 0) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "0805, 100nF, 10V, X5R, 20%" (at 0 1.65) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 5 +2V5))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BFE670D)
(at 64 61.6 90)
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
(path /5C5E5A07)
(attr smd)
(fp_text reference C20 (at -3.4 0 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "0805, 100nF, 10V, X5R, 20%" (at 0 1.65 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 1 smd roundrect (at -1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 4 +1V2))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED8FDF)
(at 91 62.025 270)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BDC7C63)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C19 (at -3.525 0 270) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(fp_text value "0805, 1uF, 10V, X5R, 20% (DNP)" (at 0 1.65 270) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 270) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0 270) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 29 /VCCPLL))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED8FCE)
(at 62 61.6 90)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5C64A04D)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C18 (at -3.4 0 90) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 10nF, 10V, X5R, 20%" (at 0 1.65 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 1 smd roundrect (at -1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 4 +1V2))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BFE6E5D)
(at 60 61.6 90)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5C64A110)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C17 (at -3.4 0 90) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(fp_text value "0805, 1uF, 10V, X5R, 20%" (at 0 1.65 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(pad 2 smd roundrect (at 1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 4 +1V2))
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED9A67)
(at 91 66 90)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BDC7CFF)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C16 (at -3.5 0 90) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(fp_text value "0805, 1uF, 10V, X5R, 20% (DNP)" (at 0 1.65 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 1 smd roundrect (at -1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 1 +5V))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BEDA165)
(at 65 55 90)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5C71BAD4)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C14 (at 3.5 0 90) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 10nF, 10V, X5R, 20%" (at 0 1.65 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 3 +3V3))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED8F8A)
(at 67 55 90)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
(path /5C71BB44)
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C15 (at 3.5 0 90) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 100nF, 10V, X5R, 20%" (at 0 1.65 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 1 smd roundrect (at -1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 3 +3V3))
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BFE7834)
(at 63 55 90)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5C71BA4C)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C13 (at 3.5 0 90) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(fp_text value "0805, 1uF, 10V, X5R, 20%" (at 0 1.65 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(pad 2 smd roundrect (at 1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 3 +3V3))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED8F68)
(at 72.4 49.2 270)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5C1F1DFB)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_text reference C11 (at 0 1.7 270) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 100nF, 10V, X5R, 20%" (at 0 1.65 270) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 1.025 0 270) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 3 +3V3))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(pad 1 smd roundrect (at -1.025 0 270) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 2 GND))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED9EFE)
(at 84.95 75)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BD6F643)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C10 (at -3.45 0) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 1uF, 10V, X5R, 20%" (at 0 1.65) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 5 +2V5))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BFE6BD8)
(at 61 55 90)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BD6FE8F)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C9 (at -2.5 0 180) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(fp_text value "0805, 1uF, 10V, X5R, 20%" (at 0 1.65 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(pad 2 smd roundrect (at 1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(pad 1 smd roundrect (at -1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 3 +3V3))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BFE77F2)
(at 55.4 61.625 90)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BD700C8)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C8 (at -2.875 0.1 180) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 1uF, 10V, X5R, 20%" (at 0 1.65 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 4 +1V2))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED8F24)
(at 74.25 71.75 180)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5C8902B6)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C7 (at 3 0 180) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 100nF, 10V, X5R, 20%" (at 0 1.65 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 1 smd roundrect (at -1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 3 +3V3))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED8F13)
(at 74.25 69.75 180)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5C8902B0)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C6 (at 3 0 180) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 10nF, 10V, X5R, 20%" (at 0 1.65 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 3 +3V3))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED8F02)
(at 74.25 67.75 180)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5C8902AA)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C5 (at 3 0 180) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 1uF, 10V, X5R, 20%" (at 0 1.65 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 2 GND))
(pad 1 smd roundrect (at -1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 3 +3V3))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED9E88)
(at 45 63 180)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BE02A6F)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C4 (at -3 0 180) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 100nF, 10V, X5R, 20%" (at 0 1.65 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 3 +3V3))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED8EE0)
(at 88.975 75 180)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BD7909F)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C3 (at -3.025 0 180) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 1uF, 10V, X5R, 20%" (at 0 1.65 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 1 smd roundrect (at -1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 1 +5V))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BEDAB71)
(at 61 51 270)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BD861AF)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C2 (at -2.5 0) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 1uF, 10V, X5R, 20%" (at 0 1.65 270) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 270) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0 270) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 1 +5V))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED8EBE)
(at 55.4 57.575 270)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BD80E21)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C1 (at -2.575 0) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 1uF, 10V, X5R, 20%" (at 0 1.65 270) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(pad 2 smd roundrect (at 1.025 0 270) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(pad 1 smd roundrect (at -1.025 0 270) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 1 +5V))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:C_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951B1) (tstamp 5BED8EAD)
(at 84 53)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor handsolder")
(path /5C7EE94A)
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference C28 (at 3.5 0) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 100nF, 10V, X5R, 20%" (at 0 1.65) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 3 +3V3))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/C_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(module tomu-fpga:PinHeader_2x20_P2.54mm_Vertical (layer F.Cu) (tedit 5BEA3907) (tstamp 5BED8E6C)
(at 75 75 270)
(descr "Through hole straight pin header, 2x20, 2.54mm pitch, double rows")
(tags "Through hole pin header THT 2x20 2.54mm double row")
(path /5C14D2BF)
(fp_text reference J1 (at 1.27 -2.33 270) (layer F.SilkS) hide
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_text value Raspberry_Pi_2_3 (at 1.27 50.59 270) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_text user %R (at 1.27 24.13) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_line (start 4.35 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 4.35 50.05) (end 4.35 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 50.05) (end 4.35 50.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 50.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.33) (end 3.87 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 1.27) (end 1.27 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 3.87 -1.33) (end 3.87 49.59) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 49.59) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 49.59) (end 3.87 49.59) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 0) (end 0 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 49.53) (end -1.27 0) (layer F.Fab) (width 0.1))
(fp_line (start 3.81 49.53) (end -1.27 49.53) (layer F.Fab) (width 0.1))
(fp_line (start 3.81 -1.27) (end 3.81 49.53) (layer F.Fab) (width 0.1))
(fp_line (start 0 -1.27) (end 3.81 -1.27) (layer F.Fab) (width 0.1))
(pad 40 thru_hole oval (at 2.54 48.26 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 46 "Net-(J1-Pad40)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 39 thru_hole oval (at 0 48.26 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 38 thru_hole oval (at 2.54 45.72 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 37 "Net-(J1-Pad38)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 37 thru_hole oval (at 0 45.72 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 47 "Net-(J1-Pad37)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 36 thru_hole oval (at 2.54 43.18 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 28 "Net-(J1-Pad36)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 35 thru_hole oval (at 0 43.18 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 38 "Net-(J1-Pad35)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 34 thru_hole oval (at 2.54 40.64 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 33 thru_hole oval (at 0 40.64 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 39 "Net-(J1-Pad33)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 32 thru_hole oval (at 2.54 38.1 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 40 "Net-(J1-Pad32)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 31 thru_hole oval (at 0 38.1 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 41 "Net-(J1-Pad31)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 30 thru_hole oval (at 2.54 35.56 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 29 thru_hole oval (at 0 35.56 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 42 "Net-(J1-Pad29)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 28 thru_hole oval (at 2.54 33.02 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 43 "Net-(J1-Pad28)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 27 thru_hole oval (at 0 33.02 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 44 "Net-(J1-Pad27)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 26 thru_hole oval (at 2.54 30.48 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 69 /DBG_6))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 25 thru_hole oval (at 0 30.48 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 24 thru_hole oval (at 2.54 27.94 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 17 /SPI_CS))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 23 thru_hole oval (at 0 27.94 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(net 22 /SPI_CLK))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 22 thru_hole oval (at 2.54 25.4 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(net 23 /SPI_IO3))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 21 thru_hole oval (at 0 25.4 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(net 21 /SPI_MISO))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 20 thru_hole oval (at 2.54 22.86 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 19 thru_hole oval (at 0 22.86 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 7 /SPI_MOSI))
(pad 18 thru_hole oval (at 2.54 20.32 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 8 /SPI_IO2))
(pad 17 thru_hole oval (at 0 20.32 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 9 "Net-(J1-Pad17)"))
(pad 16 thru_hole oval (at 2.54 17.78 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 54 "Net-(J1-Pad16)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 15 thru_hole oval (at 0 17.78 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 68 /DBG_5))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 14 thru_hole oval (at 2.54 15.24 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 13 thru_hole oval (at 0 15.24 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 11 /CRESET))
(pad 12 thru_hole oval (at 2.54 12.7 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 12 /DBG_4))
(pad 11 thru_hole oval (at 0 12.7 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 13 /CDONE))
(pad 10 thru_hole oval (at 2.54 10.16 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 14 /UART_RX))
(pad 9 thru_hole oval (at 0 10.16 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 8 thru_hole oval (at 2.54 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 15 /UART_TX))
(pad 7 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 67 /DBG_3))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 6 thru_hole oval (at 2.54 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 5 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 66 /DBG_2))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 4 thru_hole oval (at 2.54 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 +5V))
(pad 3 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 10 /DBG_1))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 2 thru_hole oval (at 2.54 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 +5V))
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 16 "Net-(J1-Pad1)"))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(module tomu-fpga:QFN-48-1EP_7x7mm_P0.5mm_EP5.6x5.6mm (layer F.Cu) (tedit 5BF9B0F3) (tstamp 5BED8E2E)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(at 74 60)
(descr "QFN, 48 Pin (http://www.st.com/resource/en/datasheet/stm32f042k6.pdf (Page 94)), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py")
(tags "QFN DFN_QFN")
(path /5C122971)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference U5 (at 3.3 4.9) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value ICE40UP5K-SG48I (at 0 4.82) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_circle (center -4.625 -2.775) (end -4.513197 -2.775) (layer F.SilkS) (width 0.4))
(fp_line (start 3.135 -3.61) (end 3.61 -3.61) (layer F.SilkS) (width 0.12))
(fp_line (start 3.61 -3.61) (end 3.61 -3.135) (layer F.SilkS) (width 0.12))
(fp_line (start -3.135 3.61) (end -3.61 3.61) (layer F.SilkS) (width 0.12))
(fp_line (start -3.61 3.61) (end -3.61 3.135) (layer F.SilkS) (width 0.12))
(fp_line (start 3.135 3.61) (end 3.61 3.61) (layer F.SilkS) (width 0.12))
(fp_line (start 3.61 3.61) (end 3.61 3.135) (layer F.SilkS) (width 0.12))
(fp_line (start -3.135 -3.61) (end -3.61 -3.61) (layer F.SilkS) (width 0.12))
(fp_line (start -2.5 -3.5) (end 3.5 -3.5) (layer F.Fab) (width 0.1))
(fp_line (start 3.5 -3.5) (end 3.5 3.5) (layer F.Fab) (width 0.1))
(fp_line (start 3.5 3.5) (end -3.5 3.5) (layer F.Fab) (width 0.1))
(fp_line (start -3.5 3.5) (end -3.5 -2.5) (layer F.Fab) (width 0.1))
(fp_line (start -3.5 -2.5) (end -2.5 -3.5) (layer F.Fab) (width 0.1))
(fp_line (start -4.12 -4.12) (end -4.12 4.12) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.12 4.12) (end 4.12 4.12) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.12 4.12) (end 4.12 -4.12) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.12 -4.12) (end -4.12 -4.12) (layer F.CrtYd) (width 0.05))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 49 smd roundrect (at 0 0) (size 5.6 5.6) (layers F.Cu F.Mask) (roundrect_rratio 0.044643)
(net 2 GND))
(pad "" smd roundrect (at -2.1 -2.1) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at -2.1 -0.7) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at -2.1 0.7) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at -2.1 2.1) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at -0.7 -2.1) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at -0.7 -0.7) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at -0.7 0.7) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at -0.7 2.1) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at 0.7 -2.1) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at 0.7 -0.7) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at 0.7 0.7) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at 0.7 2.1) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at 2.1 -2.1) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at 2.1 -0.7) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at 2.1 0.7) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad "" smd roundrect (at 2.1 2.1) (size 1.13 1.13) (layers F.Paste) (roundrect_rratio 0.221239))
(pad 1 smd roundrect (at -3.4375 -2.75) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 3 +3V3))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 2 smd roundrect (at -3.4375 -2.25) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 50 "Net-(U5-Pad2)"))
(pad 3 smd roundrect (at -3.4375 -1.75) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 51 "Net-(U5-Pad3)"))
(pad 4 smd roundrect (at -3.4375 -1.25) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 52 "Net-(U5-Pad4)"))
(pad 5 smd roundrect (at -3.4375 -0.75) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(net 4 +1V2))
(pad 6 smd roundrect (at -3.4375 -0.25) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 53 "Net-(U5-Pad6)"))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 7 smd roundrect (at -3.4375 0.25) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 13 /CDONE))
(pad 8 smd roundrect (at -3.4375 0.75) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 11 /CRESET))
(pad 9 smd roundrect (at -3.4375 1.25) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 69 /DBG_6))
(pad 10 smd roundrect (at -3.4375 1.75) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 68 /DBG_5))
(pad 11 smd roundrect (at -3.4375 2.25) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 67 /DBG_3))
(pad 12 smd roundrect (at -3.4375 2.75) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 66 /DBG_2))
(pad 13 smd roundrect (at -2.75 3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 14 /UART_RX))
(pad 14 smd roundrect (at -2.25 3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 7 /SPI_MOSI))
(pad 15 smd roundrect (at -1.75 3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 22 /SPI_CLK))
(pad 16 smd roundrect (at -1.25 3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 17 /SPI_CS))
(pad 17 smd roundrect (at -0.75 3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 21 /SPI_MISO))
(pad 18 smd roundrect (at -0.25 3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 8 /SPI_IO2))
(pad 19 smd roundrect (at 0.25 3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 23 /SPI_IO3))
(pad 20 smd roundrect (at 0.75 3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 10 /DBG_1))
(pad 21 smd roundrect (at 1.25 3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 15 /UART_TX))
(pad 22 smd roundrect (at 1.75 3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 3 +3V3))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 23 smd roundrect (at 2.25 3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 12 /DBG_4))
(pad 24 smd roundrect (at 2.75 3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 5 +2V5))
(pad 25 smd roundrect (at 3.4375 2.75) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 58 /PMOD_1))
(pad 26 smd roundrect (at 3.4375 2.25) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 56 /PMOD_2))
(pad 27 smd roundrect (at 3.4375 1.75) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 57 /PMOD_3))
(pad 28 smd roundrect (at 3.4375 1.25) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 55 /PMOD_4))
(pad 29 smd roundrect (at 3.4375 0.75) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 29 /VCCPLL))
(pad 30 smd roundrect (at 3.4375 0.25) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +1V2))
(pad 31 smd roundrect (at 3.4375 -0.25) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 45 "Net-(U5-Pad31)"))
(pad 32 smd roundrect (at 3.4375 -0.75) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 36 "Net-(U5-Pad32)"))
(pad 33 smd roundrect (at 3.4375 -1.25) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 +3V3))
(pad 34 smd roundrect (at 3.4375 -1.75) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 20 /ICE_USBP))
(pad 35 smd roundrect (at 3.4375 -2.25) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 48 /PU_CTRL_USBP))
(pad 36 smd roundrect (at 3.4375 -2.75) (size 0.875 0.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 49 /PU_CTRL_USBN))
(pad 37 smd roundrect (at 2.75 -3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 19 /ICE_USBN))
(pad 38 smd roundrect (at 2.25 -3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 30 "Net-(SW3-Pad1)"))
(pad 39 smd roundrect (at 1.75 -3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 32 /LED_R))
(pad 40 smd roundrect (at 1.25 -3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 34 /LED_B))
(pad 41 smd roundrect (at 0.75 -3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 33 /LED_G))
(pad 42 smd roundrect (at 0.25 -3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 31 "Net-(SW4-Pad1)"))
(pad 43 smd roundrect (at -0.25 -3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 35 "Net-(U5-Pad43)"))
(pad 44 smd roundrect (at -0.75 -3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 18 /OSC_IN))
(pad 45 smd roundrect (at -1.25 -3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 62 "Net-(D5-Pad1)"))
(pad 46 smd roundrect (at -1.75 -3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 63 "Net-(D4-Pad1)"))
(pad 47 smd roundrect (at -2.25 -3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 64 "Net-(D3-Pad1)"))
(pad 48 smd roundrect (at -2.75 -3.4375) (size 0.25 0.875) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 65 "Net-(D2-Pad1)"))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/QFN-48-1EP_7x7mm_Pitch0.5mm.wrl
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951E7) (tstamp 5BED8D93)
(at 85 60 90)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BF5243E)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference R10 (at 3.5 0 90) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(fp_text value "0805, 100ohm, 1/16W, 1%" (at 0 1.65 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 4 +1V2))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0 90) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 29 /VCCPLL))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/R_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951E7) (tstamp 5BED8D71)
(at 35.225 50.5)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor handsolder")
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(path /5C41A61D)
(attr smd)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_text reference R4 (at 3.275 0) (layer F.SilkS)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "0805, 10k, 1/16W (DNP)" (at 0 1.65) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 13 /CDONE))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 3 +3V3))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/R_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(module tomu-fpga:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951E7) (tstamp 5C01E6D4)
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(at 98.275216 44.724784 45)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor handsolder")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5C39F47B)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference R8 (at -3.14632 0 45) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 1.5k, 1/16W, 1%" (at 0 1.65 45) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 45) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(pad 2 smd roundrect (at 1.025 0 45) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 61 "Net-(D7-Pad1)"))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(pad 1 smd roundrect (at -1.025 0 45) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 49 /PU_CTRL_USBN))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/R_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(module tomu-fpga:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951E7) (tstamp 5C05BEFB)
(at 96.824784 43.275216 45)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor handsolder")
(path /5BDB01D9)
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference R11 (at -3.499873 0 45) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 22ohm, 1/16W, 1%" (at 0 1.65 45) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 45) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(pad 2 smd roundrect (at 1.025 0 45) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 61 "Net-(D7-Pad1)"))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(pad 1 smd roundrect (at -1.025 0 45) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(net 19 /ICE_USBN))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/R_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(module tomu-fpga:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951E7) (tstamp 5C05BF8D)
(at 101.2 47.6 45)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor handsolder")
(path /5BDB00B1)
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference R12 (at -3.571195 0 45) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_text value "0805, 22ohm, 1/16W, 1%" (at 0 2.757716 45) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 45) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(pad 2 smd roundrect (at 1.025 0 45) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 60 "Net-(D8-Pad1)"))
hardware: pcb: commit evt2 version of pcb Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:25:39 +00:00
(pad 1 smd roundrect (at -1.025 0 45) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(net 20 /ICE_USBP))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/R_0805_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951E7) (tstamp 5BED8D2D)
(at 35.25 52.5)
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor handsolder")
(path /5C0F3302)
(attr smd)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_text reference R1 (at 2.75 0) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 10k, 1/16W" (at 0 1.65) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 2 smd roundrect (at 1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 3 +3V3))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd roundrect (at -1.025 0) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 11 /CRESET))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/R_0805_HandSoldering.wrl
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(at (xyz 0 0 0))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(scale (xyz 1 1 1))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951E7) (tstamp 5BED8D1C)
(at 87.025 77 180)
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor handsolder")
(path /5D1C6F06)
(attr smd)
(fp_text reference R2 (at -2.875 -0.1 180) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 1.5k, 1/16W, 1%" (at 0 1.65 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 6 "Net-(D1-Pad1)"))
(pad 1 smd roundrect (at -1.025 0 180) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
(net 2 GND))
(model ${KIPRJMOD}/tomu-fpga.pretty/R_0805_HandSoldering.wrl
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(at (xyz 0 0 0))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(scale (xyz 1 1 1))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(rotate (xyz 0 0 0))
)
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(module tomu-fpga:R_0805_2012Metric_Pad1.15x1.40mm_HandSolder (layer F.Cu) (tedit 5BD951E7) (tstamp 5BF9D25C)
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(at 99.8 46.2 45)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "resistor handsolder")
(path /5BDC6632)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference R9 (at -3.217641 0 45) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "0805, 1.5k, 1/16W, 1%" (at 0 1.65 45) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 45) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start 1.85 0.95) (end -1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.85 -0.95) (end 1.85 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.95) (end 1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.95) (end -1.85 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.261252 0.71) (end 0.261252 0.71) (layer F.SilkS) (width 0.12))
(fp_line (start -0.261252 -0.71) (end 0.261252 -0.71) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end -1 -0.6) (layer F.Fab) (width 0.1))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 2 smd roundrect (at 1.024999 0 45) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 60 "Net-(D8-Pad1)"))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 1 smd roundrect (at -1.024999 0 45) (size 1.15 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.217391)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 48 /PU_CTRL_USBP))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/R_0805_HandSoldering.wrl
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(module tomu-fpga:SOT-23-5_HandSoldering (layer F.Cu) (tedit 5BF9B0D0) (tstamp 5C00269A)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(at 94 64 90)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "5-pin SOT23 package")
(tags "SOT-23-5 hand-soldering")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BDB73B2)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference U8 (at -0.1 2.8 180) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(fp_text value "LDO-SOT23-1.2V (DNP)" (at 0 2.9 90) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_circle (center -2.775 -0.925) (end -2.671922 -0.925) (layer F.SilkS) (width 0.2))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.075)))
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_line (start -0.9 1.61) (end 0.9 1.61) (layer F.SilkS) (width 0.12))
(fp_line (start 0.9 -1.61) (end -1.55 -1.61) (layer F.SilkS) (width 0.12))
(fp_line (start -0.9 -0.9) (end -0.25 -1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 -1.55) (end -0.25 -1.55) (layer F.Fab) (width 0.1))
(fp_line (start -0.9 -0.9) (end -0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 1.55) (end -0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 -1.55) (end 0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start -2.38 -1.8) (end 2.38 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.38 -1.8) (end -2.38 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.38 1.8) (end 2.38 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.38 1.8) (end -2.38 1.8) (layer F.CrtYd) (width 0.05))
(pad 1 smd rect (at -1.35 -0.95 90) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 1 +5V))
(pad 2 smd rect (at -1.35 0 90) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 3 smd rect (at -1.35 0.95 90) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 1 +5V))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 4 smd rect (at 1.35 0.95 90) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 27 "Net-(U8-Pad4)"))
(pad 5 smd rect (at 1.35 -0.95 90) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 29 /VCCPLL))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/SOT-23-5.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(module tomu-fpga:SOT-23-5_HandSoldering (layer F.Cu) (tedit 5BF9B0D0) (tstamp 5BED8CCE)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(at 52.35 59.95 270)
(descr "5-pin SOT23 package")
(tags "SOT-23-5 hand-soldering")
(path /5BD6EF0E)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference U1 (at 3.05 0.1) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value LDO-SOT23-1.2V (at 0 2.9 270) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_circle (center -2.775 -0.925) (end -2.671922 -0.925) (layer F.SilkS) (width 0.2))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.075)))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_line (start -0.9 1.61) (end 0.9 1.61) (layer F.SilkS) (width 0.12))
(fp_line (start 0.9 -1.61) (end -1.55 -1.61) (layer F.SilkS) (width 0.12))
(fp_line (start -0.9 -0.9) (end -0.25 -1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 -1.55) (end -0.25 -1.55) (layer F.Fab) (width 0.1))
(fp_line (start -0.9 -0.9) (end -0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 1.55) (end -0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 -1.55) (end 0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start -2.38 -1.8) (end 2.38 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.38 -1.8) (end -2.38 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.38 1.8) (end 2.38 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.38 1.8) (end -2.38 1.8) (layer F.CrtYd) (width 0.05))
(pad 1 smd rect (at -1.35 -0.95 270) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 1 +5V))
(pad 2 smd rect (at -1.35 0 270) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 2 GND))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 3 smd rect (at -1.35 0.95 270) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 1 +5V))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 4 smd rect (at 1.35 0.95 270) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 24 "Net-(U1-Pad4)"))
(pad 5 smd rect (at 1.35 -0.95 270) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 4 +1V2))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/SOT-23-5.wrl
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(at (xyz 0 0 0))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(scale (xyz 1 1 1))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(rotate (xyz 0 0 0))
)
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(module tomu-fpga:SOT-23-5_HandSoldering (layer F.Cu) (tedit 5BF9B0D0) (tstamp 5BFE9971)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(at 58 53 270)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(descr "5-pin SOT23 package")
(tags "SOT-23-5 hand-soldering")
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(path /5BD6EE82)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(attr smd)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text reference U2 (at 3.25 0) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value LDO-SOT23-3.3V (at 0 2.9 270) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_circle (center -2.775 -0.925) (end -2.671922 -0.925) (layer F.SilkS) (width 0.2))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 0.5 0.5) (thickness 0.075)))
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_line (start -0.9 1.61) (end 0.9 1.61) (layer F.SilkS) (width 0.12))
(fp_line (start 0.9 -1.61) (end -1.55 -1.61) (layer F.SilkS) (width 0.12))
(fp_line (start -0.9 -0.9) (end -0.25 -1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 -1.55) (end -0.25 -1.55) (layer F.Fab) (width 0.1))
(fp_line (start -0.9 -0.9) (end -0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 1.55) (end -0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 -1.55) (end 0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start -2.38 -1.8) (end 2.38 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.38 -1.8) (end -2.38 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.38 1.8) (end 2.38 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.38 1.8) (end -2.38 1.8) (layer F.CrtYd) (width 0.05))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 1 smd rect (at -1.35 -0.95 270) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(net 1 +5V))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 2 smd rect (at -1.35 0 270) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(pad 3 smd rect (at -1.35 0.95 270) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 4 +1V2))
(pad 4 smd rect (at 1.35 0.95 270) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 25 "Net-(U2-Pad4)"))
(pad 5 smd rect (at 1.35 -0.95 270) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 3 +3V3))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/SOT-23-5.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(module tomu-fpga:SOT-23-5_HandSoldering (layer F.Cu) (tedit 5BF9B0D0) (tstamp 5BED8CA2)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(at 87 72 180)
(descr "5-pin SOT23 package")
(tags "SOT-23-5 hand-soldering")
(path /5BD6EEEA)
(attr smd)
(fp_text reference U3 (at 0 3 180) (layer F.SilkS)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value LDO-SOT23-2.5V (at 0 2.9 180) (layer F.Fab)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_circle (center -2.775 -0.925) (end -2.671922 -0.925) (layer F.SilkS) (width 0.2))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.075)))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(fp_line (start -0.9 1.61) (end 0.9 1.61) (layer F.SilkS) (width 0.12))
(fp_line (start 0.9 -1.61) (end -1.55 -1.61) (layer F.SilkS) (width 0.12))
(fp_line (start -0.9 -0.9) (end -0.25 -1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 -1.55) (end -0.25 -1.55) (layer F.Fab) (width 0.1))
(fp_line (start -0.9 -0.9) (end -0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 1.55) (end -0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start 0.9 -1.55) (end 0.9 1.55) (layer F.Fab) (width 0.1))
(fp_line (start -2.38 -1.8) (end 2.38 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.38 -1.8) (end -2.38 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.38 1.8) (end 2.38 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.38 1.8) (end -2.38 1.8) (layer F.CrtYd) (width 0.05))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd rect (at -1.35 -0.95 180) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 1 +5V))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(pad 2 smd rect (at -1.35 0 180) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(pad 3 smd rect (at -1.35 0.95 180) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 3 +3V3))
(pad 4 smd rect (at 1.35 0.95 180) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 26 "Net-(U3-Pad4)"))
(pad 5 smd rect (at 1.35 -0.95 180) (size 1.56 0.65) (layers F.Cu F.Paste F.Mask)
(net 5 +2V5))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/SOT-23-5.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
(rotate (xyz 0 0 0))
)
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(module tomu-fpga:SPST-NO-Button (layer F.Cu) (tedit 5BF2D514) (tstamp 5BED8C8C)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(at 78 37 180)
(path /5C1DDAF6)
hardware: pcb: fix `virtual` and `smd` designation Some components were getting added to the BOM that shouldn't have been, and some were missing from the pick-and-place file. Update the `Placement Type` to be accurate according to assembly. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 03:32:32 +00:00
(attr smd)
hardware: pcb: replace "text" with "value" for buttons Previously, we used text to display the "5" and "6" designators for the physical buttons. Replace this with a value of "5" and "6", and remove the extra text. Additionally, display "SW??" under the switch, to make hand-assembly easier. Do the same thing for the "Reset" button. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:12:13 +00:00
(fp_text reference SW4 (at -0.25 0 180) (layer F.SilkS)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: replace "text" with "value" for buttons Previously, we used text to display the "5" and "6" designators for the physical buttons. Replace this with a value of "5" and "6", and remove the extra text. Additionally, display "SW??" under the switch, to make hand-assembly easier. Do the same thing for the "Reset" button. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:12:13 +00:00
(fp_text value 5 (at -0.25 -6.25 180) (layer F.SilkS)
(effects (font (size 2 2) (thickness 0.25)))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_line (start -4.6 3) (end -4.6 -3.1) (layer F.CrtYd) (width 0.2))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_line (start 4.6 3) (end -4.6 3) (layer F.CrtYd) (width 0.2))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(fp_line (start 4.6 -3.1) (end 4.6 3) (layer F.CrtYd) (width 0.2))
(fp_line (start -4.6 -3.1) (end 4.6 -3.1) (layer F.CrtYd) (width 0.2))
(fp_line (start -1 -2.8) (end 0.7 -2.8) (layer F.SilkS) (width 0.2))
(fp_line (start 4.3 1) (end 4.3 -1.1) (layer F.SilkS) (width 0.2))
(fp_line (start -1 2.7) (end 0.7 2.7) (layer F.SilkS) (width 0.2))
(fp_line (start -4.3 1) (end -4.3 -1.1) (layer F.SilkS) (width 0.2))
(pad 1 smd rect (at -3.2 -1.9 180) (size 1.6 1) (layers F.Cu F.Paste F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 31 "Net-(SW4-Pad1)") (solder_mask_margin 0.07))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 3 smd rect (at -3.2 1.9 180) (size 1.6 1) (layers F.Cu F.Paste F.Mask)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 2 GND) (solder_mask_margin 0.07))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 2 smd rect (at 3.2 -1.9 180) (size 1.6 1) (layers F.Cu F.Paste F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 31 "Net-(SW4-Pad1)") (solder_mask_margin 0.07))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(pad 4 smd rect (at 3.2 1.9 180) (size 1.6 1) (layers F.Cu F.Paste F.Mask)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(net 2 GND) (solder_mask_margin 0.07))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(model ${KIPRJMOD}/tomu-fpga.pretty/SW_SPST_PTS645.wrl
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(at (xyz 0 0 0))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(scale (xyz 0.8 0.8 0.2))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(rotate (xyz 0 0 0))
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(module tomu-fpga:Touchpads (layer F.Cu) (tedit 5BD9311D) (tstamp 5BED8C5C)
(at 49 36)
(path /5BE44C19)
(fp_text reference SW2 (at -24 3 90) (layer F.SilkS) hide
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(fp_text value "Captouch Pads" (at -0.1 9) (layer F.Fab)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_text user 4 (at 18 7) (layer F.SilkS)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(effects (font (size 2 2) (thickness 0.25)))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_text user 3 (at 6 7) (layer F.SilkS)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(effects (font (size 2 2) (thickness 0.25)))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_text user 2 (at -6 7) (layer F.SilkS)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(effects (font (size 2 2) (thickness 0.25)))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(fp_text user 1 (at -18 7) (layer F.SilkS)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(effects (font (size 2 2) (thickness 0.25)))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(pad 4 smd rect (at 18 0 180) (size 10 10) (layers F.Cu F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 62 "Net-(D5-Pad1)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 3 smd rect (at 6 0 180) (size 10 10) (layers F.Cu F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 63 "Net-(D4-Pad1)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 2 smd rect (at -6 0 180) (size 10 10) (layers F.Cu F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 64 "Net-(D3-Pad1)"))
hardware: pcb: update footprints and 3d models for pin 1 marker Update the footprints so that the pin 1 marker is actually visible by using silk where possible. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-13 02:51:06 +00:00
(pad 1 smd rect (at -18 0 180) (size 10 10) (layers F.Cu F.Mask)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(net 65 "Net-(D2-Pad1)"))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(gr_text G (at 44.5 73) (layer F.SilkS) (tstamp 5BF8A6C3)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text D6 (at 44.5 79.4) (layer F.SilkS) (tstamp 5BF8A6C0)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text D5 (at 57.2 73.1) (layer F.SilkS) (tstamp 5BF89A97)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text D4 (at 62.3 79.4) (layer F.SilkS) (tstamp 5BF88BC4)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text G (at 64.9 73.1) (layer F.SilkS) (tstamp 5BF85F9E)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text G (at 52.1 79.4) (layer F.SilkS) (tstamp 5BF85D3C)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text 5V (at 75 79.4) (layer F.SilkS) (tstamp 5BF85838)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text 5V (at 72.5 79.4) (layer F.SilkS) (tstamp 5BF85110)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text G (at 69.9 79.4) (layer F.SilkS) (tstamp 5BF84EAE)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text G (at 59.8 79.4) (layer F.SilkS) (tstamp 5BF88BC9)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text S2 (at 54.8 79.4) (layer F.SilkS) (tstamp 5BF84282)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text S3 (at 49.7 79.4) (layer F.SilkS) (tstamp 5BF83DBE)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text SC (at 47.1 79.4) (layer F.SilkS) (tstamp 5BF8311A)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text TX (at 67.5 79.4) (layer F.SilkS) (tstamp 5BF8057F)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text RX (at 64.8 79.4) (layer F.SilkS) (tstamp 5BF88C0B)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text D1 (at 72.5 73.1) (layer F.SilkS) (tstamp 5BF7FBF7)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text D2 (at 69.9 73) (layer F.SilkS) (tstamp 5BF7F733)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text D3 (at 67.3 73) (layer F.SilkS) (tstamp 5BF7F26F)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text CD (at 62.25 73) (layer F.SilkS) (tstamp 5BF7EDAB)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text CR (at 59.75 73) (layer F.SilkS) (tstamp 5BF7E8E7)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text MO (at 52 73) (layer F.SilkS) (tstamp 5BF7DCFD)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text MI (at 49.5 73) (layer F.SilkS) (tstamp 5BF7D839)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
(gr_text SK (at 47 73) (layer F.SilkS) (tstamp 5BF7CEB1)
(effects (font (size 0.7 0.7) (thickness 0.175)))
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(gr_text GND (at 31 50.5 90) (layer F.SilkS) (tstamp 5BF530E3)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_line (start 29.5 53) (end 25 53) (layer F.SilkS) (width 0.2))
(gr_line (start 29.5 48) (end 29.5 53) (layer F.SilkS) (width 0.2))
(gr_line (start 25 48) (end 29.5 48) (layer F.SilkS) (width 0.2))
(gr_poly (pts (xy 24.5 48) (xy 29.5 48) (xy 29.5 53) (xy 24.5 53)) (layer B.Mask) (width 0.15) (tstamp 5BF52155))
(gr_text 3.3V (at 31 70 90) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(gr_poly (pts (xy 24.5 67.5) (xy 29.5 67.5) (xy 29.5 72.5) (xy 24.5 72.5)) (layer F.Mask) (width 0.15))
(gr_text 1 (at 95.6 75.7) (layer F.SilkS) (tstamp 5BF4F706)
(effects (font (size 1 1) (thickness 0.2)))
)
(gr_text 2 (at 98.1 75.7) (layer F.SilkS) (tstamp 5BF4F6FF)
(effects (font (size 1 1) (thickness 0.2)))
)
(gr_text 3 (at 100.6 75.7) (layer F.SilkS) (tstamp 5BF4F6FB)
(effects (font (size 1 1) (thickness 0.2)))
)
(gr_text 4 (at 103.1 75.7) (layer F.SilkS) (tstamp 5BF4F6F7)
(effects (font (size 1 1) (thickness 0.2)))
)
(gr_text G (at 105.7 75.7) (layer F.SilkS) (tstamp 5BF4E98F)
(effects (font (size 1 1) (thickness 0.2)))
)
(gr_text 3V (at 108.3 75.7) (layer F.SilkS) (tstamp 5BF4E2E7)
(effects (font (size 1 1) (thickness 0.2)))
)
(gr_text PD (at 37.1 60.8 270) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.1)))
)
(gr_line (start 98.6 38) (end 106 30.6) (layer Edge.Cuts) (width 0.15) (tstamp 5BF32414))
(gr_line (start 114.4 37.4) (end 107.6 30.6) (layer Edge.Cuts) (width 0.15) (tstamp 5BF32376))
hardware: pcb: update drill offset, add mfg notes Add a note indicating the PCB thickness and color. Also, move the drill origin to the lower-left corner, to aid in machine assembly. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 05:48:45 +00:00
(gr_text "PCB Thickness: 2.4mm\nSoldermask: Dark Blue\nSilk: White" (at 25.4 25.4) (layer Cmts.User)
(effects (font (size 1.5 1.5) (thickness 0.3)) (justify left))
)
pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
(gr_text "(c) sean@xobs.io\nApache 2.0 License" (at 96.8 55.4) (layer F.SilkS) (tstamp 5C056FAB)
(effects (font (size 0.7 0.7) (thickness 0.15)) (justify left))
)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(gr_text "Tomu FPGA EVT2\nDesigned in\nSingapore\n12/2018\ntomu.im/fpga-evt2/" (at 113.7 64.8) (layer F.SilkS)
pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
(effects (font (size 1.3 1.3) (thickness 0.25)) (justify right))
)
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(gr_text "Raspberry Pi" (at 37 72.74) (layer F.SilkS)
pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
(effects (font (size 1 1) (thickness 0.2)))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(gr_text PMOD (at 102 74.2) (layer F.SilkS)
pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
(effects (font (size 1 1) (thickness 0.2)))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
)
(gr_text Pwr (at 83.4 78.8) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(gr_text PU (at 43.4 60.7 90) (layer F.SilkS)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(effects (font (size 0.8 0.8) (thickness 0.1)))
)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(gr_line (start 106 30.6) (end 107.6 30.6) (layer Edge.Cuts) (width 0.15))
(gr_line (start 114.4 39) (end 114.4 37.4) (layer Edge.Cuts) (width 0.15))
(gr_line (start 98.6 38) (end 90.6 30) (layer Edge.Cuts) (width 0.15))
(gr_line (start 107 46.4) (end 114.4 39) (layer Edge.Cuts) (width 0.15))
(gr_line (start 115 54.4) (end 107 46.4) (layer Edge.Cuts) (width 0.15))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(gr_line (start 25 80) (end 25 30) (layer Edge.Cuts) (width 0.15))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(gr_line (start 115 80) (end 25 80) (layer Edge.Cuts) (width 0.15))
(gr_line (start 115 54.4) (end 115 80) (layer Edge.Cuts) (width 0.15))
(gr_line (start 25 30) (end 90.6 30) (layer Edge.Cuts) (width 0.15))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(segment (start 60.625 49.975) (end 58.95 51.65) (width 0.8) (layer F.Cu) (net 1))
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(segment (start 58.95 50.07) (end 58.38 49.5) (width 0.8) (layer F.Cu) (net 1))
(segment (start 58.95 51.65) (end 58.95 50.07) (width 0.8) (layer F.Cu) (net 1))
(segment (start 55.4 55.875) (end 55.4 56.55) (width 0.8) (layer F.Cu) (net 1))
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(segment (start 52.174954 56) (end 52.5 56) (width 0.8) (layer F.Cu) (net 1))
(segment (start 52.5 56) (end 52.825046 56) (width 0.8) (layer F.Cu) (net 1))
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(via (at 99.7 50.4) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(via (at 101.25 51.75) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1))
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(via (at 100.15 51.8) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(segment (start 61 49.975) (end 61 48.75) (width 0.5) (layer F.Cu) (net 1))
(segment (start 61 48.75) (end 61.25 48.5) (width 0.5) (layer F.Cu) (net 1))
(via (at 62.5 49.25) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1))
(segment (start 61 49.975) (end 61.775 49.975) (width 0.5) (layer F.Cu) (net 1))
(segment (start 61.775 49.975) (end 62.5 49.25) (width 0.5) (layer F.Cu) (net 1))
(segment (start 55.4 51.200678) (end 55.4 55.875) (width 0.8) (layer F.Cu) (net 1))
pcb: remove usb silk, add more 5V vias Add more 5V vias near the 1.2V regulator, and replace a manual trace with a copper pour. This will increase the amount of copper going to both the 3.3V and 1.2V regulators, which should improve stability. While we're at it, remove an errant silk artifact on the USB connector. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 06:03:27 +00:00
(via (at 59.6 49.6) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1) (tstamp 5C05A83B))
(via (at 59 48.7) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1) (tstamp 5C05A848))
(via (at 60 48.7) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1) (tstamp 5C05A84A))
(via (at 61.2 48.6) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1))
hardware: pcb: repour and connect wire in kicad The `VCCPLL` line was listed as "Not Connected" in KiCad. Reconnect it, even though it was already connected. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 03:33:41 +00:00
(segment (start 108.157716 32.882485) (end 107.662742 32.387511) (width 0.1524) (layer F.Cu) (net 1))
(segment (start 108.157716 32.882486) (end 108.157716 32.882485) (width 0.1524) (layer F.Cu) (net 1))
(segment (start 107.132412 32.91784) (end 103.844365 36.205887) (width 0.1524) (layer F.Cu) (net 1))
(segment (start 107.662742 32.387511) (end 107.132412 32.91784) (width 0.1524) (layer F.Cu) (net 1))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(via (at 100.5 50.8) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1) (tstamp 5BFA8117))
(via (at 101.5 50.5) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1))
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(via (at 101.25 38.8) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1))
(via (at 102 38.25) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1))
(segment (start 100.75 40.25) (end 99.8 39.2) (width 1) (layer F.Cu) (net 1))
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(via (at 102.5 37.5) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1))
(segment (start 100 39.5) (end 101.4 37.6) (width 1) (layer F.Cu) (net 1))
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(segment (start 100.5 40.5) (end 99.8 39.2) (width 1) (layer F.Cu) (net 1))
(segment (start 100.6 40) (end 100.5 40.5) (width 1) (layer F.Cu) (net 1))
(via (at 100.5 40.25) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1))
(segment (start 101.4 39.2) (end 102.25 38.75) (width 0.3) (layer B.Cu) (net 1))
(segment (start 101.4 39.2) (end 103.773654 36.976346) (width 0.3) (layer F.Cu) (net 1))
(segment (start 103.773654 36.976346) (end 103.773654 36.276598) (width 0.3) (layer F.Cu) (net 1))
(segment (start 103.773654 36.276598) (end 100.300252 39.75) (width 0.3) (layer F.Cu) (net 1))
(segment (start 100.300252 39.75) (end 100.6 40) (width 0.3) (layer F.Cu) (net 1))
(via (at 101.5 39.75) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1))
(via (at 102.25 39) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1) (tstamp 5BF44C28))
(via (at 99.5 40.75) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1) (tstamp 5BF4BC7A))
(via (at 103 38.25) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 1) (tstamp 5BF4BEB2))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(via (at 89.5 77) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(via (at 87 64.5) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(via (at 89.5 65) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
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(via (at 52.5 57) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
(segment (start 52.35 58.6) (end 52.35 57.15) (width 0.5) (layer F.Cu) (net 2))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(segment (start 52.35 57.15) (end 52.5 57) (width 0.3) (layer F.Cu) (net 2))
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(segment (start 30.1 63.2) (end 28.8 63.2) (width 0.8) (layer F.Cu) (net 2))
(segment (start 28.8 63.2) (end 28.75 63.25) (width 0.8) (layer F.Cu) (net 2))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(via (at 36.9 58.9) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(via (at 72.25 62) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
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(via (at 75.25 57.9) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5BF25D1D))
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(via (at 73 57.9) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5BF263BF))
(via (at 72.25 57.9) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5BF26C97))
(segment (start 72.25 62) (end 76 62) (width 0.5) (layer F.Cu) (net 2))
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(segment (start 74 59.65) (end 72.25 57.9) (width 0.5) (layer F.Cu) (net 2))
(segment (start 74 60) (end 74 59.65) (width 0.5) (layer F.Cu) (net 2))
(via (at 85.1 73.9) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(via (at 65.3 59.9) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 64 60.575) (end 64.625 60.575) (width 0.5) (layer F.Cu) (net 2))
(segment (start 64.625 60.575) (end 65.3 59.9) (width 0.5) (layer F.Cu) (net 2))
(segment (start 63 53.975) (end 63 53.1) (width 0.5) (layer F.Cu) (net 2))
(via (at 56.6 60.4) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(via (at 89.9 72) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
(via (at 73.65 66.6) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
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(segment (start 73.65 66.6) (end 73.225 67.675) (width 0.5) (layer F.Cu) (net 2))
(via (at 72.2 71.95) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 73.025 71.95) (end 73.225 71.75) (width 0.8) (layer F.Cu) (net 2))
(segment (start 72.2 71.95) (end 73.025 71.95) (width 0.8) (layer F.Cu) (net 2))
(via (at 81.1 71.2) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 80.225 71.2) (end 80.025 71) (width 0.8) (layer F.Cu) (net 2))
(segment (start 81.1 71.2) (end 80.225 71.2) (width 0.8) (layer F.Cu) (net 2))
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(via (at 81.3 69) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 80.025 69) (end 81.3 69) (width 0.8) (layer F.Cu) (net 2))
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(segment (start 85.1 73.9) (end 85.1 74.125) (width 0.8) (layer F.Cu) (net 2))
(segment (start 89.5 77) (end 88.05 77) (width 0.8) (layer F.Cu) (net 2))
(segment (start 89.9 72) (end 88.35 72) (width 0.8) (layer F.Cu) (net 2))
(segment (start 89.525 64.975) (end 89.5 65) (width 0.8) (layer F.Cu) (net 2))
(segment (start 91 64.975) (end 89.525 64.975) (width 0.8) (layer F.Cu) (net 2))
(segment (start 87 63.025) (end 87 64.5) (width 0.8) (layer F.Cu) (net 2))
(via (at 88.4 64.5) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 89 63.05) (end 89 63.9) (width 0.8) (layer F.Cu) (net 2))
(segment (start 89 63.9) (end 88.4 64.5) (width 0.8) (layer F.Cu) (net 2))
(segment (start 94 67) (end 94 65.35) (width 0.8) (layer F.Cu) (net 2))
(segment (start 85.7 53) (end 86.15 53.45) (width 0.8) (layer F.Cu) (net 2))
(segment (start 85.025 53) (end 85.7 53) (width 0.8) (layer F.Cu) (net 2))
(via (at 86.15 53.9) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 86.15 53.45) (end 86.15 53.9) (width 0.8) (layer F.Cu) (net 2))
(via (at 67 52.6) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 67 53.975) (end 67 52.6) (width 0.8) (layer F.Cu) (net 2))
(via (at 63 52.7) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 63 53.975) (end 63 52.7) (width 0.8) (layer F.Cu) (net 2))
(segment (start 56.4 60.6) (end 56.6 60.4) (width 0.8) (layer F.Cu) (net 2))
(segment (start 55.4 60.6) (end 56.4 60.6) (width 0.8) (layer F.Cu) (net 2))
(segment (start 55.5 58.5) (end 55.4 58.6) (width 0.8) (layer F.Cu) (net 2))
(segment (start 56.5 58.5) (end 55.5 58.5) (width 0.8) (layer F.Cu) (net 2))
(via (at 65 52.4) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 65 53.975) (end 65 52.4) (width 0.8) (layer F.Cu) (net 2))
(via (at 57.8 50.3953) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 58 51.65) (end 58 50.5953) (width 0.5) (layer F.Cu) (net 2))
(segment (start 58 50.5953) (end 57.8 50.3953) (width 0.5) (layer F.Cu) (net 2))
(via (at 51.9 60) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 52.35 58.6) (end 52.35 59.55) (width 0.5) (layer F.Cu) (net 2))
(segment (start 52.35 59.55) (end 51.9 60) (width 0.5) (layer F.Cu) (net 2))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(via (at 107.7 41.2) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(via (at 105.6 43.3) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D956))
(via (at 106.3 42.6) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D958))
(via (at 106.3 44) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D95A))
(via (at 107 43.3) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D95C))
(via (at 108.4 41.9) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D95E))
(via (at 107 41.9) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D960))
(via (at 107.7 42.6) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D962))
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(via (at 86.5 43) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D9D6))
(via (at 86.5 47) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D9D8))
(via (at 88 47) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D9DA))
(via (at 88 43) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D9DC))
(via (at 88.75 43) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D9EB))
(via (at 87.25 43) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D9ED))
(via (at 87.25 47) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D9EF))
(via (at 88.75 47) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C05D9F5))
(segment (start 112.330473 36.54372) (end 112.818376 37.031623) (width 0.1524) (layer F.Cu) (net 2))
(segment (start 112.330472 36.54372) (end 112.330473 36.54372) (width 0.1524) (layer F.Cu) (net 2))
(segment (start 112.288047 37.561953) (end 109 40.85) (width 0.1524) (layer F.Cu) (net 2))
(segment (start 112.818376 37.031623) (end 112.288047 37.561953) (width 0.1524) (layer F.Cu) (net 2))
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(via (at 73.9 50.2) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 73.9 50.85) (end 73.075 51.675) (width 0.8) (layer F.Cu) (net 2))
(segment (start 73.9 50.2) (end 73.9 50.85) (width 0.8) (layer F.Cu) (net 2))
(via (at 70.3 52.3) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 70.6 52.6) (end 70.3 52.3) (width 0.3) (layer F.Cu) (net 2))
(segment (start 71.225 52.6) (end 70.6 52.6) (width 0.3) (layer F.Cu) (net 2))
(segment (start 37.855 58.9) (end 38.75 59.795) (width 0.5) (layer F.Cu) (net 2))
(segment (start 36.9 58.9) (end 37.855 58.9) (width 0.5) (layer F.Cu) (net 2))
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(via (at 42.75 48) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C02266F))
(via (at 49.25 45.75) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C0228D1))
(segment (start 49.25 45.5) (end 48.5 44.75) (width 0.3) (layer F.Cu) (net 2))
(segment (start 49.25 45.75) (end 49.25 45.5) (width 0.3) (layer F.Cu) (net 2))
(segment (start 104.142893 45.707107) (end 109 40.85) (width 0.8) (layer F.Cu) (net 2))
(segment (start 103.707107 45.707107) (end 104.142893 45.707107) (width 0.8) (layer F.Cu) (net 2))
(via (at 95.25 39) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 96.242462 38.007538) (end 95.25 39) (width 0.3) (layer F.Cu) (net 2))
(segment (start 96.257538 38.007538) (end 96.242462 38.007538) (width 0.3) (layer F.Cu) (net 2))
(via (at 103.75 41.5) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2))
(segment (start 102.914214 41.5) (end 101.207107 43.207107) (width 0.3) (layer F.Cu) (net 2))
(segment (start 103.75 41.5) (end 102.914214 41.5) (width 0.3) (layer F.Cu) (net 2))
(segment (start 42.75 48) (end 44 48) (width 0.3) (layer F.Cu) (net 2))
(via (at 42.75 45.75) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C034D1D))
(segment (start 42.75 45.75) (end 43.75 45.75) (width 0.3) (layer F.Cu) (net 2))
(via (at 57.25 45.5) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 2) (tstamp 5C03884E))
(segment (start 56.5 45.5) (end 56.25 45.25) (width 0.3) (layer F.Cu) (net 2))
(segment (start 57.25 45.5) (end 56.5 45.5) (width 0.3) (layer F.Cu) (net 2))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(segment (start 75.275 67.75) (end 75.275 71.75) (width 0.8) (layer F.Cu) (net 3))
(segment (start 88.35 71.05) (end 88.35 66.35) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 88.35 66.35) (end 88.92139 65.77861) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 91.648248 65.77861) (end 92.1 65.326858) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 92.1 65.326858) (end 92.1 63.7) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 88.92139 65.77861) (end 91.648248 65.77861) (width 0.1524) (layer F.Cu) (net 3))
(via (at 97.8 64.5) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 3))
(segment (start 108.26 77.7) (end 108.26 74.96) (width 0.1524) (layer B.Cu) (net 3))
(segment (start 108.26 74.96) (end 97.8 64.5) (width 0.1524) (layer B.Cu) (net 3))
(segment (start 97 63.7) (end 95.1 63.7) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 97.8 64.5) (end 97 63.7) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 92.1 63.7) (end 95.1 63.7) (width 0.1524) (layer F.Cu) (net 3))
pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
(segment (start 82.6 57.8) (end 82.1 58.5) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 82.1 58.5) (end 78.225 58.5) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 78.225 58.5) (end 77.975 58.75) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 77.975 58.75) (end 77.4375 58.75) (width 0.1524) (layer F.Cu) (net 3))
(via (at 82.6 57.8) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 3))
(via (at 81.8 58.1) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 3))
(segment (start 82.3 57.9) (end 82.6 57.8) (width 0.1524) (layer B.Cu) (net 3))
(segment (start 81.8 58.1) (end 82.3 57.9) (width 0.1524) (layer B.Cu) (net 3))
(via (at 82.4 58.5) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 3))
(segment (start 82.8 58) (end 82.6 57.8) (width 0.1524) (layer B.Cu) (net 3))
(segment (start 82.4 58.5) (end 82.8 58) (width 0.1524) (layer B.Cu) (net 3))
(via (at 75.2 66.3) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 3))
(segment (start 75.2 65.2) (end 75.2 66.3) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 75.75 64.85) (end 75.75 63.4375) (width 0.1524) (layer F.Cu) (net 3))
(via (at 75.2 65.2) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 3))
(segment (start 75.2 65.2) (end 75.75 64.85) (width 0.1524) (layer F.Cu) (net 3))
(via (at 75.65 65.75) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 3))
(segment (start 75.65 65.65) (end 75.2 65.2) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 75.65 65.75) (end 75.65 65.65) (width 0.1524) (layer F.Cu) (net 3))
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(segment (start 95.503601 63.7) (end 95.1 63.7) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 82.975 53) (end 89.075 59.1) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 89.075 59.1) (end 92.4 59.1) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 92.4 59.1) (end 92.9 59.6) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 92.9 59.6) (end 93.416482 59.6) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 93.416482 59.6) (end 95.503601 61.687119) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 95.503601 61.687119) (end 95.503601 63.7) (width 0.1524) (layer F.Cu) (net 3))
hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
(segment (start 74.92 53.13) (end 74.925 53.125) (width 0.3) (layer F.Cu) (net 3))
(segment (start 76.3476 52.7) (end 76.2 52.8476) (width 0.1524) (layer F.Cu) (net 3))
(segment (start 76.3 52.7) (end 76.2 52.8) (width 0.2) (layer F.Cu) (net 3))
pcb: remove usb silk, add more 5V vias Add more 5V vias near the 1.2V regulator, and replace a manual trace with a copper pour. This will increase the amount of copper going to both the 3.3V and 1.2V regulators, which should improve stability. While we're at it, remove an errant silk artifact on the USB connector. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 06:03:27 +00:00
(via (at 78.5 60) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 4))
(segment (start 77.4375 60.25) (end 78.25 60.25) (width 0.3) (layer F.Cu) (net 4))
(segment (start 78.25 60.25) (end 78.5 60) (width 0.3) (layer F.Cu) (net 4))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(via (at 68.5 59.5) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 4))
(via (at 69.3 59.5) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 4))
(segment (start 69.3 59.5) (end 68.5 59.5) (width 0.3) (layer B.Cu) (net 4))
(segment (start 69.75 59.25) (end 70.5625 59.25) (width 0.3) (layer F.Cu) (net 4))
(segment (start 69.3 59.5) (end 69.75 59.25) (width 0.3) (layer F.Cu) (net 4))
(via (at 79.4 60.1) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 4))
pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
(via (at 79.5 59.4) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 4))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(segment (start 79 60) (end 78.5 60) (width 0.3) (layer F.Cu) (net 4))
pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
(segment (start 79.5 59.4) (end 79 60) (width 0.3) (layer F.Cu) (net 4))
(segment (start 79.6 59.6) (end 79.4 60.1) (width 0.1524) (layer B.Cu) (net 4))
(segment (start 79.5 59.4) (end 79.6 59.6) (width 0.1524) (layer B.Cu) (net 4))
(via (at 68.5 60.3) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 4) (tstamp 5C04F100))
pcb: remove usb silk, add more 5V vias Add more 5V vias near the 1.2V regulator, and replace a manual trace with a copper pour. This will increase the amount of copper going to both the 3.3V and 1.2V regulators, which should improve stability. While we're at it, remove an errant silk artifact on the USB connector. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 06:03:27 +00:00
(segment (start 53.3 60.3676) (end 53.3 61.3) (width 0.1524) (layer F.Cu) (net 4))
(segment (start 54.023911 59.643689) (end 53.3 60.3676) (width 0.1524) (layer F.Cu) (net 4))
(segment (start 57.05 51.65) (end 57.05 52.5824) (width 0.1524) (layer F.Cu) (net 4))
(segment (start 57.05 52.5824) (end 57.603601 53.136001) (width 0.1524) (layer F.Cu) (net 4))
(segment (start 54.023911 58.476089) (end 54.023911 59.643689) (width 0.1524) (layer F.Cu) (net 4))
(segment (start 57.603601 56.696399) (end 56.50361 57.79639) (width 0.1524) (layer F.Cu) (net 4))
(segment (start 56.50361 57.79639) (end 54.70361 57.79639) (width 0.1524) (layer F.Cu) (net 4))
(segment (start 57.603601 53.136001) (end 57.603601 56.696399) (width 0.1524) (layer F.Cu) (net 4))
(segment (start 54.70361 57.79639) (end 54.023911 58.476089) (width 0.1524) (layer F.Cu) (net 4))
(segment (start 84.025 77) (end 86 77) (width 0.8) (layer F.Cu) (net 6))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(via (at 68.2 67.4) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 7))
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hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
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pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
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hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
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pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
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hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
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hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
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pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
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hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
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hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
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hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: redo dbg numbering and add silk to rpi header Redo the numbering for the dbg pins. While we're at it, add some silk to the Raspberry Pi header so that we know what we're looking at. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-23 08:14:46 +00:00
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(segment (start 72.25 56.5625) (end 72.25 56.025) (width 0.1524) (layer F.Cu) (net 63))
(segment (start 72.25 56.025) (end 71.2 54.975) (width 0.1524) (layer F.Cu) (net 63))
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(segment (start 51.8285 44.872237) (end 51.8285 39.1715) (width 0.1524) (layer B.Cu) (net 63))
(segment (start 54.4 51.8) (end 55 52.4) (width 0.1524) (layer B.Cu) (net 63))
(segment (start 55 52.4) (end 55 53.737868) (width 0.1524) (layer B.Cu) (net 63))
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(segment (start 71.2 54.315067) (end 70.913432 54.028499) (width 0.1524) (layer B.Cu) (net 63))
(segment (start 71.2 54.8) (end 71.2 54.315067) (width 0.1524) (layer B.Cu) (net 63))
(segment (start 50.622237 44.872237) (end 50.5 44.75) (width 0.3) (layer F.Cu) (net 63))
(segment (start 51.8285 44.872237) (end 50.622237 44.872237) (width 0.3) (layer F.Cu) (net 63))
(segment (start 71.75 56.5625) (end 71.75 56.213306) (width 0.1524) (layer F.Cu) (net 64))
(segment (start 71.75 56.213306) (end 70.2 54.663306) (width 0.1524) (layer F.Cu) (net 64))
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(segment (start 70.3 54.6) (end 69.815067 54.6) (width 0.1524) (layer B.Cu) (net 64))
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(segment (start 56.126256 55.29519) (end 54.607849 53.776783) (width 0.1524) (layer B.Cu) (net 64))
(segment (start 54.607849 53.045473) (end 54.26495 52.702574) (width 0.1524) (layer B.Cu) (net 64))
(segment (start 54.607849 53.776783) (end 54.607849 53.045473) (width 0.1524) (layer B.Cu) (net 64))
(segment (start 46.25 45.75) (end 46.9 45.1) (width 0.3) (layer F.Cu) (net 64))
(segment (start 45.75 45.75) (end 46.25 45.75) (width 0.3) (layer F.Cu) (net 64))
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(segment (start 48.6 48.2) (end 48 48.2) (width 0.1524) (layer F.Cu) (net 65))
(segment (start 56 55.6) (end 53.8 53.4) (width 0.1524) (layer B.Cu) (net 65))
(via (at 31 36) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 65))
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(via (at 70.15 55.4625) (size 0.6858) (drill 0.3302) (layers F.Cu B.Cu) (net 65))
(segment (start 71.25 56.5625) (end 70.15 55.4625) (width 0.1524) (layer F.Cu) (net 65))
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(segment (start 69.665067 55.4625) (end 69.527567 55.6) (width 0.1524) (layer B.Cu) (net 65))
(segment (start 70.15 55.4625) (end 69.665067 55.4625) (width 0.1524) (layer B.Cu) (net 65))
(segment (start 68.6 55.6) (end 68.25 55.6) (width 0.1524) (layer B.Cu) (net 65))
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(segment (start 69.527567 55.6) (end 56 55.6) (width 0.1524) (layer B.Cu) (net 65))
(segment (start 31 36) (end 31 36.2) (width 0.1524) (layer B.Cu) (net 65))
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(segment (start 31 36.2) (end 36.1 41.3) (width 0.1524) (layer B.Cu) (net 65))
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(segment (start 46 48) (end 47.8 48) (width 0.3) (layer F.Cu) (net 65))
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
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(segment (start 70.025 61.75) (end 69.3 62.475) (width 0.1524) (layer F.Cu) (net 68))
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(segment (start 70.025 61.25) (end 68.9 62.375) (width 0.1524) (layer F.Cu) (net 69))
(segment (start 68.9 62.375) (end 68.9 65.868934) (width 0.1524) (layer F.Cu) (net 69))
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(segment (start 67.431066 65.868934) (end 66.5 66.8) (width 0.1524) (layer F.Cu) (net 69))
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(segment (start 45.8 74) (end 46.3 73.5) (width 0.1524) (layer B.Cu) (net 69))
(segment (start 46.3 73.5) (end 47.9 73.5) (width 0.1524) (layer B.Cu) (net 69))
(segment (start 47.9 73.5) (end 52.3 69.1) (width 0.1524) (layer B.Cu) (net 69))
(segment (start 52.3 69.1) (end 65.6 69.1) (width 0.1524) (layer B.Cu) (net 69))
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(zone (net 4) (net_name +1V2) (layer B.Cu) (tstamp 5BF9D062) (hatch edge 0.508)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(priority 1)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(connect_pads yes (clearance 0.154))
(min_thickness 0.254)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(fill yes (arc_segments 16) (thermal_gap 0.154) (thermal_bridge_width 0.154))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(polygon
(pts
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(xy 80 59) (xy 68 59) (xy 68 61) (xy 80 61)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(filled_polygon
(pts
(xy 79.873 60.873) (xy 68.127 60.873) (xy 68.127 59.127) (xy 79.873 59.127)
)
)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(zone (net 1) (net_name +5V) (layer F.Cu) (tstamp 5BF9D05F) (hatch edge 0.508)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(priority 3)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(connect_pads yes (clearance 0.154))
(min_thickness 0.254)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(fill yes (arc_segments 32) (thermal_gap 0.154) (thermal_bridge_width 0.154) (smoothing chamfer))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(polygon
(pts
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(xy 87 78) (xy 87 72.5) (xy 89.5 72.5) (xy 89.5 66.3) (xy 92.5 66.3)
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(xy 92.5 64.3) (xy 98 64.3) (xy 88 53.8) (xy 88 48.7) (xy 106.85 29.85)
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(xy 109.6 32.6) (xy 101.5 40.5) (xy 115.2 54.6) (xy 114.95 80) (xy 71 80)
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(xy 71 76) (xy 76.5 76) (xy 76.5 78)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(filled_polygon
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(zone (net 5) (net_name +2V5) (layer F.Cu) (tstamp 5BF9D05C) (hatch edge 0.508)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(priority 2)
(connect_pads yes (clearance 0.154))
(min_thickness 0.254)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(fill yes (arc_segments 32) (thermal_gap 0.154) (thermal_bridge_width 0.154))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(polygon
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hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(zone (net 2) (net_name GND) (layer B.Cu) (tstamp 5BF9D059) (hatch edge 0.508)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(connect_pads yes (clearance 0.154))
(min_thickness 0.254)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(fill yes (arc_segments 32) (thermal_gap 0.154) (thermal_bridge_width 0.154) (smoothing chamfer))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
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hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(zone (net 29) (net_name /VCCPLL) (layer F.Cu) (tstamp 5BF9D056) (hatch edge 0.508)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(priority 1)
(connect_pads yes (clearance 0.154))
(min_thickness 0.254)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(fill yes (arc_segments 32) (thermal_gap 0.154) (thermal_bridge_width 0.154) (smoothing chamfer))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
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hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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)
)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(zone (net 4) (net_name +1V2) (layer F.Cu) (tstamp 5BF9D053) (hatch edge 0.508)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(priority 2)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(connect_pads yes (clearance 0.154))
(min_thickness 0.254)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(fill yes (arc_segments 16) (thermal_gap 0.154) (thermal_bridge_width 0.154))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
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hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
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hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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)
)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(zone (net 4) (net_name +1V2) (layer F.Cu) (tstamp 5BF9D050) (hatch edge 0.508)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(priority 2)
(connect_pads yes (clearance 0.154))
(min_thickness 0.254)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(fill yes (arc_segments 16) (thermal_gap 0.154) (thermal_bridge_width 0.154))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
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hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(filled_polygon
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)
)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(zone (net 3) (net_name +3V3) (layer F.Cu) (tstamp 5BF9D04D) (hatch edge 0.508)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(connect_pads yes (clearance 0.154))
(min_thickness 0.254)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(fill yes (arc_segments 16) (thermal_gap 0.154) (thermal_bridge_width 0.154))
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
(polygon
(pts
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
(xy 25 41.5) (xy 72.5 41.5) (xy 72.5 30) (xy 91.2 30) (xy 100.2 39)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
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hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(filled_polygon
(pts
pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(zone (net 1) (net_name +5V) (layer B.Cu) (tstamp 5BF9D04A) (hatch edge 0.508)
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
(priority 2)
(connect_pads yes (clearance 0.154))
(min_thickness 0.254)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(fill yes (arc_segments 32) (thermal_gap 0.154) (thermal_bridge_width 0.154))
hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
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hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
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hardware: pcb: finish layout with new PMOD connector This is just about manufacturable. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 03:37:49 +00:00
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hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
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hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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)
hardware: first fully-routed PCB The PCB is terrible, and probably would have all sorts of issues. Will rip it up and try again tomorrow. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 14:28:10 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(zone (net 3) (net_name +3V3) (layer B.Cu) (tstamp 5BF9D047) (hatch edge 0.508)
pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
(priority 1)
(connect_pads yes (clearance 0.154))
(min_thickness 0.254)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(fill yes (arc_segments 32) (thermal_gap 0.154) (thermal_bridge_width 0.154))
pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
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)
)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
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pcb: add more silk, fatten up ground traces Add more silk, indicating website and other info. While we're at it, move some traces around to give more copper area, and drop some more vias to improve ground performance. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 04:49:56 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(zone (net 1) (net_name +5V) (layer F.Cu) (tstamp 5BF9D044) (hatch edge 0.508)
pcb: remove usb silk, add more 5V vias Add more 5V vias near the 1.2V regulator, and replace a manual trace with a copper pour. This will increase the amount of copper going to both the 3.3V and 1.2V regulators, which should improve stability. While we're at it, remove an errant silk artifact on the USB connector. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 06:03:27 +00:00
(priority 1)
(connect_pads yes (clearance 0.154))
(min_thickness 0.254)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
pcb: remove usb silk, add more 5V vias Add more 5V vias near the 1.2V regulator, and replace a manual trace with a copper pour. This will increase the amount of copper going to both the 3.3V and 1.2V regulators, which should improve stability. While we're at it, remove an errant silk artifact on the USB connector. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 06:03:27 +00:00
(polygon
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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pcb: remove usb silk, add more 5V vias Add more 5V vias near the 1.2V regulator, and replace a manual trace with a copper pour. This will increase the amount of copper going to both the 3.3V and 1.2V regulators, which should improve stability. While we're at it, remove an errant silk artifact on the USB connector. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 06:03:27 +00:00
)
)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(filled_polygon
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pcb: rework pcb with correct footprints, add tvs diodes Add TVS diodes, so we make sure they work. Also, rework the PCB so that the clock actually functions now. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-20 14:51:43 +00:00
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hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
)
)
pcb: remove usb silk, add more 5V vias Add more 5V vias near the 1.2V regulator, and replace a manual trace with a copper pour. This will increase the amount of copper going to both the 3.3V and 1.2V regulators, which should improve stability. While we're at it, remove an errant silk artifact on the USB connector. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 06:03:27 +00:00
)
pcb: no changes This appears to be kicad deciding to rewrite the whole file for no particular reason. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-24 20:25:01 +00:00
(zone (net 2) (net_name GND) (layer F.Cu) (tstamp 5BF9D041) (hatch edge 0.508)
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(priority 2)
(connect_pads (clearance 0.154))
(min_thickness 0.254)
hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
(polygon
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(xy 86 42) (xy 89.25 42) (xy 89.25 47.5) (xy 86 47.5)
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hardware: pcb: fill pcb Re-do the fill, because the last commit was done with an unpoured fill. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-10 04:27:38 +00:00
(filled_polygon
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hardware: pcb: re-route USB after flipping the footprint It looks kinda janky, but it's better than ripping everything up and starting over. Signed-off-by: Sean Cross <sean@xobs.io>
2018-11-02 12:39:32 +00:00
)
hardware: pcb: initial commit This is an initial commit. Still unclear of how big it will be, but this is a good "minimum size" estimate. Signed-off-by: Sean Cross <sean@xobs.io>
2018-10-31 08:03:55 +00:00
)
Reference in New Issue Copy Permalink