porting to 52840
This commit is contained in:
hathach
@@ -1,524 +0,0 @@
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/* Copyright (c) 2013 ARM LIMITED
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All rights reserved.
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||||
Redistribution and use in source and binary forms, with or without
|
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modification, are permitted provided that the following conditions are met:
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||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
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||||
- Neither the name of ARM nor the names of its contributors may be used
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||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
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||||
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||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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.syntax unified
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.arch armv7e-m
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
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#else
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.equ Stack_Size, 8192
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 8192
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .isr_vector
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.align 2
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.globl __isr_vector
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__isr_vector:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler
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.long NMI_Handler
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.long HardFault_Handler
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.long MemoryManagement_Handler
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.long BusFault_Handler
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.long UsageFault_Handler
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.long 0 /*Reserved */
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||||
.long 0 /*Reserved */
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||||
.long 0 /*Reserved */
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||||
.long 0 /*Reserved */
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||||
.long SVC_Handler
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||||
.long DebugMonitor_Handler
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||||
.long 0 /*Reserved */
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.long PendSV_Handler
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||||
.long SysTick_Handler
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||||
|
||||
/* External Interrupts */
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||||
.long POWER_CLOCK_IRQHandler
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||||
.long RADIO_IRQHandler
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||||
.long UARTE0_UART0_IRQHandler
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||||
.long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
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||||
.long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
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||||
.long NFCT_IRQHandler
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||||
.long GPIOTE_IRQHandler
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||||
.long SAADC_IRQHandler
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||||
.long TIMER0_IRQHandler
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||||
.long TIMER1_IRQHandler
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||||
.long TIMER2_IRQHandler
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.long RTC0_IRQHandler
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||||
.long TEMP_IRQHandler
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||||
.long RNG_IRQHandler
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.long ECB_IRQHandler
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||||
.long CCM_AAR_IRQHandler
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||||
.long WDT_IRQHandler
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.long RTC1_IRQHandler
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||||
.long QDEC_IRQHandler
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.long COMP_LPCOMP_IRQHandler
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||||
.long SWI0_EGU0_IRQHandler
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.long SWI1_EGU1_IRQHandler
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||||
.long SWI2_EGU2_IRQHandler
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||||
.long SWI3_EGU3_IRQHandler
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||||
.long SWI4_EGU4_IRQHandler
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.long SWI5_EGU5_IRQHandler
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||||
.long TIMER3_IRQHandler
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||||
.long TIMER4_IRQHandler
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.long PWM0_IRQHandler
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||||
.long PDM_IRQHandler
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||||
.long 0 /*Reserved */
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||||
.long 0 /*Reserved */
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||||
.long MWU_IRQHandler
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||||
.long PWM1_IRQHandler
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||||
.long PWM2_IRQHandler
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||||
.long SPIM2_SPIS2_SPI2_IRQHandler
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||||
.long RTC2_IRQHandler
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||||
.long I2S_IRQHandler
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||||
.long FPU_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
|
||||
/* Loop to copy data from read only memory to RAM.
|
||||
* The ranges of copy from/to are specified by following symbols:
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to.
|
||||
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
|
||||
* the user can add their own initialized data section before BSS section with the INTERT AFTER command.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__bss_start__
|
||||
|
||||
subs r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
|
||||
* clears the RAM where BSS data is located.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Execute SystemInit function. */
|
||||
bl SystemInit
|
||||
|
||||
/* Call _start function provided by libraries.
|
||||
* If those libraries are not accessible, define __START as your entry point.
|
||||
*/
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
b .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak MemoryManagement_Handler
|
||||
.type MemoryManagement_Handler, %function
|
||||
MemoryManagement_Handler:
|
||||
b .
|
||||
.size MemoryManagement_Handler, . - MemoryManagement_Handler
|
||||
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
b .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
b .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak DebugMonitor_Handler
|
||||
.type DebugMonitor_Handler, %function
|
||||
DebugMonitor_Handler:
|
||||
b .
|
||||
.size DebugMonitor_Handler, . - DebugMonitor_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ POWER_CLOCK_IRQHandler
|
||||
IRQ RADIO_IRQHandler
|
||||
IRQ UARTE0_UART0_IRQHandler
|
||||
IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
IRQ NFCT_IRQHandler
|
||||
IRQ GPIOTE_IRQHandler
|
||||
IRQ SAADC_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ TEMP_IRQHandler
|
||||
IRQ RNG_IRQHandler
|
||||
IRQ ECB_IRQHandler
|
||||
IRQ CCM_AAR_IRQHandler
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ QDEC_IRQHandler
|
||||
IRQ COMP_LPCOMP_IRQHandler
|
||||
IRQ SWI0_EGU0_IRQHandler
|
||||
IRQ SWI1_EGU1_IRQHandler
|
||||
IRQ SWI2_EGU2_IRQHandler
|
||||
IRQ SWI3_EGU3_IRQHandler
|
||||
IRQ SWI4_EGU4_IRQHandler
|
||||
IRQ SWI5_EGU5_IRQHandler
|
||||
IRQ TIMER3_IRQHandler
|
||||
IRQ TIMER4_IRQHandler
|
||||
IRQ PWM0_IRQHandler
|
||||
IRQ PDM_IRQHandler
|
||||
IRQ MWU_IRQHandler
|
||||
IRQ PWM1_IRQHandler
|
||||
IRQ PWM2_IRQHandler
|
||||
IRQ SPIM2_SPIS2_SPI2_IRQHandler
|
||||
IRQ RTC2_IRQHandler
|
||||
IRQ I2S_IRQHandler
|
||||
IRQ FPU_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -1,301 +0,0 @@
|
||||
/* Copyright (c) 2015, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "nrf.h"
|
||||
#include "system_nrf52.h"
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
#define __SYSTEM_CLOCK_64M (64000000UL)
|
||||
|
||||
static bool errata_16(void);
|
||||
static bool errata_31(void);
|
||||
static bool errata_32(void);
|
||||
static bool errata_36(void);
|
||||
static bool errata_37(void);
|
||||
static bool errata_57(void);
|
||||
static bool errata_66(void);
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
|
||||
#elif defined ( __ICCARM__ )
|
||||
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
|
||||
#elif defined ( __GNUC__ )
|
||||
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
|
||||
#endif
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClock = __SYSTEM_CLOCK_64M;
|
||||
}
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_16()){
|
||||
*(volatile uint32_t *)0x4007C074 = 3131961357ul;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_31()){
|
||||
*(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_32()){
|
||||
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_36()){
|
||||
NRF_CLOCK->EVENTS_DONE = 0;
|
||||
NRF_CLOCK->EVENTS_CTTO = 0;
|
||||
NRF_CLOCK->CTIV = 0;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_37()){
|
||||
*(volatile uint32_t *)0x400005A0 = 0x3;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_57()){
|
||||
*(volatile uint32_t *)0x40005610 = 0x00000005;
|
||||
*(volatile uint32_t *)0x40005688 = 0x00000001;
|
||||
*(volatile uint32_t *)0x40005618 = 0x00000000;
|
||||
*(volatile uint32_t *)0x40005614 = 0x0000003F;
|
||||
}
|
||||
|
||||
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
|
||||
for your device located at https://infocenter.nordicsemi.com/ */
|
||||
if (errata_66()){
|
||||
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
|
||||
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
|
||||
NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
|
||||
NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
|
||||
NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
|
||||
NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
|
||||
NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
|
||||
NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
|
||||
NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
|
||||
NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
|
||||
NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
|
||||
NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
|
||||
NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
|
||||
NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
|
||||
NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
|
||||
NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
|
||||
NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
|
||||
}
|
||||
|
||||
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
|
||||
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
|
||||
* operations are not used in your code. */
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= (3UL << 20) | (3UL << 22);
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
|
||||
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
|
||||
normal GPIOs. */
|
||||
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
|
||||
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
|
||||
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
|
||||
reserved for PinReset and not available as normal GPIO. */
|
||||
#if defined (CONFIG_GPIO_AS_PINRESET)
|
||||
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
|
||||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->PSELRESET[0] = 21;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_UICR->PSELRESET[1] = 21;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
|
||||
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
|
||||
Specification to see which one). */
|
||||
#if defined (ENABLE_SWO)
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
|
||||
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
#endif
|
||||
|
||||
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
|
||||
Specification to see which ones). */
|
||||
#if defined (ENABLE_TRACE)
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
|
||||
NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
#endif
|
||||
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
|
||||
static bool errata_16(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_31(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_32(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_36(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_37(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_57(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool errata_66(void)
|
||||
{
|
||||
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
|
||||
{
|
||||
if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
@@ -1,69 +0,0 @@
|
||||
/* Copyright (c) 2015, Nordic Semiconductor ASA
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* * Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_NRF52_H
|
||||
#define SYSTEM_NRF52_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_NRF52_H */
|
||||
Reference in New Issue
Block a user