From 7de0b115293a7529cd0c2cb8a2d232c078be9baf Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 8 Feb 2018 17:34:27 +0700 Subject: [PATCH] porting to 52840 --- .../components/device/compiler_abstraction.h | 91 +- .../components/device/nrf.h | 112 +- .../components/device/nrf51_to_nrf52.h | 88 +- .../components/device/nrf52.h | 111 +- .../components/device/nrf52_bitfields.h | 2780 ++--------------- .../components/device/nrf52_name_change.h | 75 +- .../toolchain/gcc/gcc_startup_nrf52.S | 524 ---- .../components/toolchain/system_nrf52.c | 301 -- .../components/toolchain/system_nrf52.h | 69 - src/boards.h | 4 +- src/{feather52.h => feather52840.h} | 18 +- src/make_common.mk | 50 +- 12 files changed, 603 insertions(+), 3620 deletions(-) delete mode 100644 nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/gcc_startup_nrf52.S delete mode 100644 nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.c delete mode 100644 nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.h rename src/{feather52.h => feather52840.h} (88%) diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/compiler_abstraction.h b/nRF5_SDK_11.0.0_89a8197/components/device/compiler_abstraction.h index 6a41e8e..b444c52 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/device/compiler_abstraction.h +++ b/nRF5_SDK_11.0.0_89a8197/components/device/compiler_abstraction.h @@ -1,32 +1,44 @@ -/* Copyright (c) 2015, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ +/* + +Copyright (c) 2010 - 2017, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + #ifndef _COMPILER_ABSTRACTION_H #define _COMPILER_ABSTRACTION_H @@ -50,6 +62,10 @@ #define __ALIGN(n) __align(n) #endif + #ifndef __PACKED + #define __PACKED __packed + #endif + #define GET_SP() __current_sp() #elif defined ( __ICCARM__ ) @@ -66,11 +82,15 @@ #define __WEAK __weak #endif - /* Not defined for IAR since it requires a new line to work, and C preprocessor does not allow that. */ #ifndef __ALIGN - #define __ALIGN(n) + #define STRING_PRAGMA(x) _Pragma(#x) + #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) #endif + #ifndef __PACKED + #define __PACKED __packed + #endif + #define GET_SP() __get_SP() #elif defined ( __GNUC__ ) @@ -91,6 +111,10 @@ #define __ALIGN(n) __attribute__((aligned(n))) #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #define GET_SP() gcc_current_sp() static inline unsigned int gcc_current_sp(void) @@ -116,6 +140,11 @@ #ifndef __ALIGN #define __ALIGN(n) __align(n) #endif + + /* Not defined for TASKING. */ + #ifndef __PACKED + #define __PACKED + #endif #define GET_SP() __get_MSP() diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h b/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h index adbb763..6f5bf34 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h +++ b/nRF5_SDK_11.0.0_89a8197/components/device/nrf.h @@ -1,62 +1,98 @@ -/* Copyright (c) 2015, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ +/* + +Copyright (c) 2010 - 2017, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ #ifndef NRF_H #define NRF_H /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 5 +#define MDK_MINOR_VERSION 15 #define MDK_MICRO_VERSION 0 +/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ +#if defined (NRF52) + #ifndef NRF52832_XXAA + #define NRF52832_XXAA + #endif +#endif + +/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */ +#if defined (NRF52810_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52840_XXAA) + #ifndef NRF52_SERIES + #define NRF52_SERIES + #endif +#endif + + #if defined(_WIN32) - /* Do not include nrf51 specific files when building for PC host */ -//#elif defined(__unix) - /* Do not include nrf51 specific files when building for PC host */ + /* Do not include nrf specific files when building for PC host */ +#elif defined(__unix) + /* Do not include nrf specific files when building for PC host */ #elif defined(__APPLE__) - /* Do not include nrf51 specific files when building for PC host */ + /* Do not include nrf specific files when building for PC host */ #else - /* Family selection for family includes. */ + /* Device selection for device includes. */ #if defined (NRF51) #include "nrf51.h" #include "nrf51_bitfields.h" #include "nrf51_deprecated.h" - #elif defined (NRF52) + #elif defined (NRF52840_XXAA) + #include "nrf52840.h" + #include "nrf52840_bitfields.h" + #include "nrf51_to_nrf52840.h" + #include "nrf52_to_nrf52840.h" + #elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) #include "nrf52.h" #include "nrf52_bitfields.h" #include "nrf51_to_nrf52.h" #include "nrf52_name_change.h" + #elif defined (NRF52810_XXAA) + #include "nrf52810.h" + #include "nrf52810_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" #else - #error "Device family must be defined. See nrf.h." - #endif /* NRF51, NRF52 */ + #error "Device must be defined. See nrf.h." + #endif /* NRF51, NRF52832_XXAA, NRF52832_XXAB, NRF52810_XXAA, NRF52840_XXAA */ #include "compiler_abstraction.h" diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf51_to_nrf52.h b/nRF5_SDK_11.0.0_89a8197/components/device/nrf51_to_nrf52.h index 16ae6f7..e04f498 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/device/nrf51_to_nrf52.h +++ b/nRF5_SDK_11.0.0_89a8197/components/device/nrf51_to_nrf52.h @@ -1,32 +1,43 @@ -/* Copyright (c) 2015, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ +/* + +Copyright (c) 2010 - 2017, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ #ifndef NRF51_TO_NRF52_H #define NRF51_TO_NRF52_H @@ -35,7 +46,7 @@ /* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the - * functionality is gone, there old names are not define, so compilation will fail. Note that also includes macros + * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros * from the nrf51_deprecated.h file. */ @@ -82,6 +93,13 @@ #define NRF_GPIO_BASE NRF_P0_BASE +/* QDEC */ +/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ +#define PSELLED PSEL.LED +#define PSELA PSEL.A +#define PSELB PSEL.B + + /* SPIS */ /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ #define PSELSCK PSEL.SCK @@ -524,6 +542,16 @@ #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn +/* REFSEL register redefined enumerated values and added some more. */ +#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd +#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd + + /* RADIO */ /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52.h b/nRF5_SDK_11.0.0_89a8197/components/device/nrf52.h index 412ecef..8e1e4d3 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52.h +++ b/nRF5_SDK_11.0.0_89a8197/components/device/nrf52.h @@ -6,38 +6,47 @@ * nrf52 from Nordic Semiconductor. * * @version V1 - * @date 23. February 2016 + * @date 3. October 2017 * * @note Generated with SVDConv V2.81d * from CMSIS SVD File 'nrf52.svd' Version 1, * - * @par Copyright (c) 2015, Nordic Semiconductor ASA + * @par Copyright (c) 2010 - 2017, Nordic Semiconductor ASA + * * All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: * - * * Redistributions of source code must retain the above copyright notice, this + * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * *******************************************************************************************************/ @@ -212,25 +221,6 @@ typedef struct { __I uint32_t RESERVED0; } POWER_RAM_Type; -typedef struct { - __IO uint32_t CPU0; /*!< AHB bus master priority register for CPU0 */ - __IO uint32_t SPIS1; /*!< AHB bus master priority register for SPIM1, SPIS1, TWIM1 and - TWIS1 */ - __IO uint32_t RADIO; /*!< AHB bus master priority register for RADIO */ - __IO uint32_t ECB; /*!< AHB bus master priority register for ECB */ - __IO uint32_t CCM; /*!< AHB bus master priority register for CCM */ - __IO uint32_t AAR; /*!< AHB bus master priority register for AAR */ - __IO uint32_t SAADC; /*!< AHB bus master priority register for SAADC */ - __IO uint32_t UARTE; /*!< AHB bus master priority register for UARTE */ - __IO uint32_t SERIAL0; /*!< AHB bus master priority register for SPIM0, SPIS0, TWIM0 and - TWIS0 */ - __IO uint32_t SERIAL2; /*!< AHB bus master priority register for SPIM2 and SPIS2 */ - __IO uint32_t NFCT; /*!< AHB bus master priority register for NFCT */ - __IO uint32_t I2S; /*!< AHB bus master priority register for I2S */ - __IO uint32_t PDM; /*!< AHB bus master priority register for PDM */ - __IO uint32_t PWM; /*!< AHB bus master priority register for PWM0, PWM1 and PWM2 */ -} AMLI_RAMPRI_Type; - typedef struct { __IO uint32_t RTS; /*!< Pin select for RTS signal */ __IO uint32_t TXD; /*!< Pin select for TXD signal */ @@ -371,12 +361,12 @@ typedef struct { } QDEC_PSEL_Type; typedef struct { - __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of sequence - A */ - __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in sequence - A */ + __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of this + sequence */ + __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in this + sequence */ __IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between - samples loaded to compare register (load every CNT+1 PWM periods) */ + samples loaded into compare register */ __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */ __I uint32_t RESERVED1[4]; } PWM_SEQ_Type; @@ -633,28 +623,12 @@ typedef struct { /*!< CLOCK Structure __I uint32_t RESERVED5[62]; __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */ __I uint32_t RESERVED6[7]; - __IO uint32_t CTIV; /*!< Calibration timer interval (retained register, same reset behaviour - as RESETREAS) */ + __IO uint32_t CTIV; /*!< Calibration timer interval */ __I uint32_t RESERVED7[8]; __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */ } NRF_CLOCK_Type; -/* ================================================================================ */ -/* ================ AMLI ================ */ -/* ================================================================================ */ - - -/** - * @brief AHB Multi-Layer Interface (AMLI) - */ - -typedef struct { /*!< AMLI Structure */ - __I uint32_t RESERVED0[896]; - AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure */ -} NRF_AMLI_Type; - - /* ================================================================================ */ /* ================ RADIO ================ */ /* ================================================================================ */ @@ -754,9 +728,12 @@ typedef struct { /*!< UARTE Structure __I uint32_t RESERVED1[52]; __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ - __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD (but potentially not yet transferred to + Data RAM) */ + __I uint32_t RESERVED2; __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */ - __I uint32_t RESERVED3[3]; + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */ __IO uint32_t EVENTS_ERROR; /*!< Error detected */ __I uint32_t RESERVED4[7]; @@ -779,7 +756,7 @@ typedef struct { /*!< UARTE Structure __I uint32_t RESERVED11; UARTE_PSEL_Type PSEL; /*!< Unspecified */ __I uint32_t RESERVED12[3]; - __IO uint32_t BAUDRATE; /*!< Baud rate */ + __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */ __I uint32_t RESERVED13[3]; UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */ __I uint32_t RESERVED14; @@ -874,7 +851,7 @@ typedef struct { /*!< SPIM Structure __I uint32_t RESERVED10; SPIM_PSEL_Type PSEL; /*!< Unspecified */ __I uint32_t RESERVED11[4]; - __IO uint32_t FREQUENCY; /*!< SPI frequency */ + __IO uint32_t FREQUENCY; /*!< SPI frequency. Accuracy depends on the HFCLK source selected. */ __I uint32_t RESERVED12[3]; SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ @@ -1977,7 +1954,6 @@ typedef struct { /*!< GPIO Structure #define NRF_BPROT_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL -#define NRF_AMLI_BASE 0x40000000UL #define NRF_RADIO_BASE 0x40001000UL #define NRF_UARTE0_BASE 0x40002000UL #define NRF_UART0_BASE 0x40002000UL @@ -2049,7 +2025,6 @@ typedef struct { /*!< GPIO Structure #define NRF_BPROT ((NRF_BPROT_Type *) NRF_BPROT_BASE) #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) -#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE) #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) #define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE) #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_bitfields.h b/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_bitfields.h index ae959d4..29d79a0 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_bitfields.h +++ b/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_bitfields.h @@ -1,32 +1,44 @@ -/* Copyright (c) 2015, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ +/* + +Copyright (c) 2010 - 2017, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + #ifndef __NRF52_BITS_H #define __NRF52_BITS_H @@ -128,2292 +140,6 @@ #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ -/* Peripheral: AMLI */ -/* Description: AHB Multi-Layer Interface */ - -/* Register: AMLI_RAMPRI_CPU0 */ -/* Description: AHB bus master priority register for CPU0 */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_SPIS1 */ -/* Description: AHB bus master priority register for SPIM1, SPIS1, TWIM1 and TWIS1 */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_RADIO */ -/* Description: AHB bus master priority register for RADIO */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_ECB */ -/* Description: AHB bus master priority register for ECB */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_ECB_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_CCM */ -/* Description: AHB bus master priority register for CCM */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_CCM_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_AAR */ -/* Description: AHB bus master priority register for AAR */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_AAR_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_SAADC */ -/* Description: AHB bus master priority register for SAADC */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_SAADC_RAM7_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_SAADC_RAM6_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_SAADC_RAM5_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_SAADC_RAM4_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_SAADC_RAM3_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_SAADC_RAM2_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_SAADC_RAM1_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_SAADC_RAM0_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SAADC_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_UARTE */ -/* Description: AHB bus master priority register for UARTE */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_UARTE_RAM7_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_UARTE_RAM6_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_UARTE_RAM5_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_UARTE_RAM4_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_UARTE_RAM3_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_UARTE_RAM2_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_UARTE_RAM1_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_UARTE_RAM0_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_UARTE_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_SERIAL0 */ -/* Description: AHB bus master priority register for SPIM0, SPIS0, TWIM0 and TWIS0 */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL0_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_SERIAL2 */ -/* Description: AHB bus master priority register for SPIM2 and SPIS2 */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_SERIAL2_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_NFCT */ -/* Description: AHB bus master priority register for NFCT */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_NFCT_RAM7_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_NFCT_RAM6_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_NFCT_RAM5_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_NFCT_RAM4_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_NFCT_RAM3_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_NFCT_RAM2_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_NFCT_RAM1_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_NFCT_RAM0_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_NFCT_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_I2S */ -/* Description: AHB bus master priority register for I2S */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_I2S_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_I2S_RAM7_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_I2S_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_I2S_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_I2S_RAM6_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_I2S_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_I2S_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_I2S_RAM5_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_I2S_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_I2S_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_I2S_RAM4_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_I2S_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_I2S_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_I2S_RAM3_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_I2S_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_I2S_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_I2S_RAM2_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_I2S_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_I2S_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_I2S_RAM1_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_I2S_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_I2S_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_I2S_RAM0_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_I2S_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_I2S_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_PDM */ -/* Description: AHB bus master priority register for PDM */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_PDM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_PDM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_PDM_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_PDM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_PDM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_PDM_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_PDM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_PDM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_PDM_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_PDM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_PDM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_PDM_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_PDM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_PDM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_PDM_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_PDM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_PDM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_PDM_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_PDM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_PDM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_PDM_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_PDM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_PDM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_PDM_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PDM_RAM0_Pri15 (15UL) /*!< Priority 15 */ - -/* Register: AMLI_RAMPRI_PWM */ -/* Description: AHB bus master priority register for PWM0, PWM1 and PWM2 */ - -/* Bits 31..28 : Priority register for RAM AHB slave 7 */ -#define AMLI_RAMPRI_PWM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_PWM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_PWM_RAM7_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM7_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 27..24 : Priority register for RAM AHB slave 6 */ -#define AMLI_RAMPRI_PWM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_PWM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_PWM_RAM6_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM6_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 23..20 : Priority register for RAM AHB slave 5 */ -#define AMLI_RAMPRI_PWM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_PWM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_PWM_RAM5_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM5_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 19..16 : Priority register for RAM AHB slave 4 */ -#define AMLI_RAMPRI_PWM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_PWM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_PWM_RAM4_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM4_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 15..12 : Priority register for RAM AHB slave 3 */ -#define AMLI_RAMPRI_PWM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_PWM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_PWM_RAM3_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM3_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 11..8 : Priority register for RAM AHB slave 2 */ -#define AMLI_RAMPRI_PWM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_PWM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_PWM_RAM2_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM2_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 7..4 : Priority register for RAM AHB slave 1 */ -#define AMLI_RAMPRI_PWM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_PWM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_PWM_RAM1_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM1_Pri15 (15UL) /*!< Priority 15 */ - -/* Bits 3..0 : Priority register for RAM AHB slave 0 */ -#define AMLI_RAMPRI_PWM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_PWM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_PWM_RAM0_Pri0 (0UL) /*!< Priority 0 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri1 (1UL) /*!< Priority 1 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri2 (2UL) /*!< Priority 2 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri3 (3UL) /*!< Priority 3 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri4 (4UL) /*!< Priority 4 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri5 (5UL) /*!< Priority 5 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri6 (6UL) /*!< Priority 6 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri7 (7UL) /*!< Priority 7 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri8 (8UL) /*!< Priority 8 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri9 (9UL) /*!< Priority 9 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri10 (10UL) /*!< Priority 10 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri11 (11UL) /*!< Priority 11 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri12 (12UL) /*!< Priority 12 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri13 (13UL) /*!< Priority 13 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri14 (14UL) /*!< Priority 14 */ -#define AMLI_RAMPRI_PWM_RAM0_Pri15 (15UL) /*!< Priority 15 */ - - /* Peripheral: BPROT */ /* Description: Block Protect */ @@ -3462,6 +1188,18 @@ /* Register: CLOCK_LFCLKSRC */ /* Description: Clock source for the LFCLK */ +/* Bit 17 : Enable or disable external source for LFCLK */ +#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ +#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ +#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ + +/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ +#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ +#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ +#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ + /* Bits 1..0 : Clock source */ #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ @@ -3470,7 +1208,7 @@ #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ /* Register: CLOCK_CTIV */ -/* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */ +/* Description: Calibration timer interval */ /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ @@ -4171,8 +1909,10 @@ #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ +#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_AAE0 (0x41414530UL) /*!< AAE0 */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_PACKAGE */ @@ -4183,6 +1923,8 @@ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ #define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */ +#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 7x8 WLCSP 56 balls with backside coating for light protection */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -4954,7 +2696,7 @@ /* Bit 0 : Result of last compare. Decision point SAMPLE task. */ #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ +#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ /* Register: LPCOMP_ENABLE */ @@ -7095,193 +4837,193 @@ /* Register: GPIO_OUT */ /* Description: Write GPIO port */ -/* Bit 31 : P0.31 pin */ +/* Bit 31 : Pin 31 */ #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ -/* Bit 30 : P0.30 pin */ +/* Bit 30 : Pin 30 */ #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ -/* Bit 29 : P0.29 pin */ +/* Bit 29 : Pin 29 */ #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ -/* Bit 28 : P0.28 pin */ +/* Bit 28 : Pin 28 */ #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ -/* Bit 27 : P0.27 pin */ +/* Bit 27 : Pin 27 */ #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ -/* Bit 26 : P0.26 pin */ +/* Bit 26 : Pin 26 */ #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ -/* Bit 25 : P0.25 pin */ +/* Bit 25 : Pin 25 */ #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ -/* Bit 24 : P0.24 pin */ +/* Bit 24 : Pin 24 */ #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ -/* Bit 23 : P0.23 pin */ +/* Bit 23 : Pin 23 */ #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ -/* Bit 22 : P0.22 pin */ +/* Bit 22 : Pin 22 */ #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ -/* Bit 21 : P0.21 pin */ +/* Bit 21 : Pin 21 */ #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ -/* Bit 20 : P0.20 pin */ +/* Bit 20 : Pin 20 */ #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ -/* Bit 19 : P0.19 pin */ +/* Bit 19 : Pin 19 */ #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ -/* Bit 18 : P0.18 pin */ +/* Bit 18 : Pin 18 */ #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ -/* Bit 17 : P0.17 pin */ +/* Bit 17 : Pin 17 */ #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ -/* Bit 16 : P0.16 pin */ +/* Bit 16 : Pin 16 */ #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ -/* Bit 15 : P0.15 pin */ +/* Bit 15 : Pin 15 */ #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ -/* Bit 14 : P0.14 pin */ +/* Bit 14 : Pin 14 */ #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ -/* Bit 13 : P0.13 pin */ +/* Bit 13 : Pin 13 */ #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ -/* Bit 12 : P0.12 pin */ +/* Bit 12 : Pin 12 */ #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ -/* Bit 11 : P0.11 pin */ +/* Bit 11 : Pin 11 */ #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ -/* Bit 10 : P0.10 pin */ +/* Bit 10 : Pin 10 */ #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ -/* Bit 9 : P0.9 pin */ +/* Bit 9 : Pin 9 */ #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ -/* Bit 8 : P0.8 pin */ +/* Bit 8 : Pin 8 */ #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ -/* Bit 7 : P0.7 pin */ +/* Bit 7 : Pin 7 */ #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ -/* Bit 6 : P0.6 pin */ +/* Bit 6 : Pin 6 */ #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ -/* Bit 5 : P0.5 pin */ +/* Bit 5 : Pin 5 */ #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ -/* Bit 4 : P0.4 pin */ +/* Bit 4 : Pin 4 */ #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ -/* Bit 3 : P0.3 pin */ +/* Bit 3 : Pin 3 */ #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ -/* Bit 2 : P0.2 pin */ +/* Bit 2 : Pin 2 */ #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ -/* Bit 1 : P0.1 pin */ +/* Bit 1 : Pin 1 */ #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ -/* Bit 0 : P0.0 pin */ +/* Bit 0 : Pin 0 */ #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ @@ -7290,224 +5032,224 @@ /* Register: GPIO_OUTSET */ /* Description: Set individual bits in GPIO port */ -/* Bit 31 : P0.31 pin */ +/* Bit 31 : Pin 31 */ #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 30 : P0.30 pin */ +/* Bit 30 : Pin 30 */ #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 29 : P0.29 pin */ +/* Bit 29 : Pin 29 */ #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 28 : P0.28 pin */ +/* Bit 28 : Pin 28 */ #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 27 : P0.27 pin */ +/* Bit 27 : Pin 27 */ #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 26 : P0.26 pin */ +/* Bit 26 : Pin 26 */ #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 25 : P0.25 pin */ +/* Bit 25 : Pin 25 */ #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 24 : P0.24 pin */ +/* Bit 24 : Pin 24 */ #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 23 : P0.23 pin */ +/* Bit 23 : Pin 23 */ #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 22 : P0.22 pin */ +/* Bit 22 : Pin 22 */ #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 21 : P0.21 pin */ +/* Bit 21 : Pin 21 */ #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 20 : P0.20 pin */ +/* Bit 20 : Pin 20 */ #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 19 : P0.19 pin */ +/* Bit 19 : Pin 19 */ #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 18 : P0.18 pin */ +/* Bit 18 : Pin 18 */ #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 17 : P0.17 pin */ +/* Bit 17 : Pin 17 */ #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 16 : P0.16 pin */ +/* Bit 16 : Pin 16 */ #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 15 : P0.15 pin */ +/* Bit 15 : Pin 15 */ #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 14 : P0.14 pin */ +/* Bit 14 : Pin 14 */ #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 13 : P0.13 pin */ +/* Bit 13 : Pin 13 */ #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 12 : P0.12 pin */ +/* Bit 12 : Pin 12 */ #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 11 : P0.11 pin */ +/* Bit 11 : Pin 11 */ #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 10 : P0.10 pin */ +/* Bit 10 : Pin 10 */ #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 9 : P0.9 pin */ +/* Bit 9 : Pin 9 */ #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 8 : P0.8 pin */ +/* Bit 8 : Pin 8 */ #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 7 : P0.7 pin */ +/* Bit 7 : Pin 7 */ #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 6 : P0.6 pin */ +/* Bit 6 : Pin 6 */ #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 5 : P0.5 pin */ +/* Bit 5 : Pin 5 */ #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 4 : P0.4 pin */ +/* Bit 4 : Pin 4 */ #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 3 : P0.3 pin */ +/* Bit 3 : Pin 3 */ #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 2 : P0.2 pin */ +/* Bit 2 : Pin 2 */ #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 1 : P0.1 pin */ +/* Bit 1 : Pin 1 */ #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 0 : P0.0 pin */ +/* Bit 0 : Pin 0 */ #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ @@ -7517,224 +5259,224 @@ /* Register: GPIO_OUTCLR */ /* Description: Clear individual bits in GPIO port */ -/* Bit 31 : P0.31 pin */ +/* Bit 31 : Pin 31 */ #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 30 : P0.30 pin */ +/* Bit 30 : Pin 30 */ #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 29 : P0.29 pin */ +/* Bit 29 : Pin 29 */ #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 28 : P0.28 pin */ +/* Bit 28 : Pin 28 */ #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 27 : P0.27 pin */ +/* Bit 27 : Pin 27 */ #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 26 : P0.26 pin */ +/* Bit 26 : Pin 26 */ #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 25 : P0.25 pin */ +/* Bit 25 : Pin 25 */ #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 24 : P0.24 pin */ +/* Bit 24 : Pin 24 */ #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 23 : P0.23 pin */ +/* Bit 23 : Pin 23 */ #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 22 : P0.22 pin */ +/* Bit 22 : Pin 22 */ #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 21 : P0.21 pin */ +/* Bit 21 : Pin 21 */ #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 20 : P0.20 pin */ +/* Bit 20 : Pin 20 */ #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 19 : P0.19 pin */ +/* Bit 19 : Pin 19 */ #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 18 : P0.18 pin */ +/* Bit 18 : Pin 18 */ #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 17 : P0.17 pin */ +/* Bit 17 : Pin 17 */ #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 16 : P0.16 pin */ +/* Bit 16 : Pin 16 */ #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 15 : P0.15 pin */ +/* Bit 15 : Pin 15 */ #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 14 : P0.14 pin */ +/* Bit 14 : Pin 14 */ #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 13 : P0.13 pin */ +/* Bit 13 : Pin 13 */ #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 12 : P0.12 pin */ +/* Bit 12 : Pin 12 */ #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 11 : P0.11 pin */ +/* Bit 11 : Pin 11 */ #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 10 : P0.10 pin */ +/* Bit 10 : Pin 10 */ #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 9 : P0.9 pin */ +/* Bit 9 : Pin 9 */ #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 8 : P0.8 pin */ +/* Bit 8 : Pin 8 */ #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 7 : P0.7 pin */ +/* Bit 7 : Pin 7 */ #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 6 : P0.6 pin */ +/* Bit 6 : Pin 6 */ #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 5 : P0.5 pin */ +/* Bit 5 : Pin 5 */ #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 4 : P0.4 pin */ +/* Bit 4 : Pin 4 */ #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 3 : P0.3 pin */ +/* Bit 3 : Pin 3 */ #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 2 : P0.2 pin */ +/* Bit 2 : Pin 2 */ #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 1 : P0.1 pin */ +/* Bit 1 : Pin 1 */ #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 0 : P0.0 pin */ +/* Bit 0 : Pin 0 */ #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ @@ -7744,193 +5486,193 @@ /* Register: GPIO_IN */ /* Description: Read GPIO port */ -/* Bit 31 : P0.31 pin */ +/* Bit 31 : Pin 31 */ #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ -/* Bit 30 : P0.30 pin */ +/* Bit 30 : Pin 30 */ #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ -/* Bit 29 : P0.29 pin */ +/* Bit 29 : Pin 29 */ #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ -/* Bit 28 : P0.28 pin */ +/* Bit 28 : Pin 28 */ #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ -/* Bit 27 : P0.27 pin */ +/* Bit 27 : Pin 27 */ #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ -/* Bit 26 : P0.26 pin */ +/* Bit 26 : Pin 26 */ #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ -/* Bit 25 : P0.25 pin */ +/* Bit 25 : Pin 25 */ #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ -/* Bit 24 : P0.24 pin */ +/* Bit 24 : Pin 24 */ #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ -/* Bit 23 : P0.23 pin */ +/* Bit 23 : Pin 23 */ #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ -/* Bit 22 : P0.22 pin */ +/* Bit 22 : Pin 22 */ #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ -/* Bit 21 : P0.21 pin */ +/* Bit 21 : Pin 21 */ #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ -/* Bit 20 : P0.20 pin */ +/* Bit 20 : Pin 20 */ #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ -/* Bit 19 : P0.19 pin */ +/* Bit 19 : Pin 19 */ #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ -/* Bit 18 : P0.18 pin */ +/* Bit 18 : Pin 18 */ #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ -/* Bit 17 : P0.17 pin */ +/* Bit 17 : Pin 17 */ #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ -/* Bit 16 : P0.16 pin */ +/* Bit 16 : Pin 16 */ #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ -/* Bit 15 : P0.15 pin */ +/* Bit 15 : Pin 15 */ #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ -/* Bit 14 : P0.14 pin */ +/* Bit 14 : Pin 14 */ #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ -/* Bit 13 : P0.13 pin */ +/* Bit 13 : Pin 13 */ #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ -/* Bit 12 : P0.12 pin */ +/* Bit 12 : Pin 12 */ #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ -/* Bit 11 : P0.11 pin */ +/* Bit 11 : Pin 11 */ #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ -/* Bit 10 : P0.10 pin */ +/* Bit 10 : Pin 10 */ #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ -/* Bit 9 : P0.9 pin */ +/* Bit 9 : Pin 9 */ #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ -/* Bit 8 : P0.8 pin */ +/* Bit 8 : Pin 8 */ #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ -/* Bit 7 : P0.7 pin */ +/* Bit 7 : Pin 7 */ #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ -/* Bit 6 : P0.6 pin */ +/* Bit 6 : Pin 6 */ #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ -/* Bit 5 : P0.5 pin */ +/* Bit 5 : Pin 5 */ #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ -/* Bit 4 : P0.4 pin */ +/* Bit 4 : Pin 4 */ #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ -/* Bit 3 : P0.3 pin */ +/* Bit 3 : Pin 3 */ #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ -/* Bit 2 : P0.2 pin */ +/* Bit 2 : Pin 2 */ #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ -/* Bit 1 : P0.1 pin */ +/* Bit 1 : Pin 1 */ #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ -/* Bit 0 : P0.0 pin */ +/* Bit 0 : Pin 0 */ #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ @@ -7939,193 +5681,193 @@ /* Register: GPIO_DIR */ /* Description: Direction of GPIO pins */ -/* Bit 31 : P0.31 pin */ +/* Bit 31 : Pin 31 */ #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ -/* Bit 30 : P0.30 pin */ +/* Bit 30 : Pin 30 */ #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ -/* Bit 29 : P0.29 pin */ +/* Bit 29 : Pin 29 */ #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ -/* Bit 28 : P0.28 pin */ +/* Bit 28 : Pin 28 */ #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ -/* Bit 27 : P0.27 pin */ +/* Bit 27 : Pin 27 */ #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ -/* Bit 26 : P0.26 pin */ +/* Bit 26 : Pin 26 */ #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ -/* Bit 25 : P0.25 pin */ +/* Bit 25 : Pin 25 */ #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ -/* Bit 24 : P0.24 pin */ +/* Bit 24 : Pin 24 */ #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ -/* Bit 23 : P0.23 pin */ +/* Bit 23 : Pin 23 */ #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ -/* Bit 22 : P0.22 pin */ +/* Bit 22 : Pin 22 */ #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ -/* Bit 21 : P0.21 pin */ +/* Bit 21 : Pin 21 */ #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ -/* Bit 20 : P0.20 pin */ +/* Bit 20 : Pin 20 */ #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ -/* Bit 19 : P0.19 pin */ +/* Bit 19 : Pin 19 */ #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ -/* Bit 18 : P0.18 pin */ +/* Bit 18 : Pin 18 */ #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ -/* Bit 17 : P0.17 pin */ +/* Bit 17 : Pin 17 */ #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ -/* Bit 16 : P0.16 pin */ +/* Bit 16 : Pin 16 */ #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ -/* Bit 15 : P0.15 pin */ +/* Bit 15 : Pin 15 */ #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ -/* Bit 14 : P0.14 pin */ +/* Bit 14 : Pin 14 */ #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ -/* Bit 13 : P0.13 pin */ +/* Bit 13 : Pin 13 */ #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ -/* Bit 12 : P0.12 pin */ +/* Bit 12 : Pin 12 */ #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ -/* Bit 11 : P0.11 pin */ +/* Bit 11 : Pin 11 */ #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ -/* Bit 10 : P0.10 pin */ +/* Bit 10 : Pin 10 */ #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ -/* Bit 9 : P0.9 pin */ +/* Bit 9 : Pin 9 */ #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ -/* Bit 8 : P0.8 pin */ +/* Bit 8 : Pin 8 */ #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ -/* Bit 7 : P0.7 pin */ +/* Bit 7 : Pin 7 */ #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ -/* Bit 6 : P0.6 pin */ +/* Bit 6 : Pin 6 */ #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ -/* Bit 5 : P0.5 pin */ +/* Bit 5 : Pin 5 */ #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ -/* Bit 4 : P0.4 pin */ +/* Bit 4 : Pin 4 */ #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ -/* Bit 3 : P0.3 pin */ +/* Bit 3 : Pin 3 */ #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ -/* Bit 2 : P0.2 pin */ +/* Bit 2 : Pin 2 */ #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ -/* Bit 1 : P0.1 pin */ +/* Bit 1 : Pin 1 */ #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ -/* Bit 0 : P0.0 pin */ +/* Bit 0 : Pin 0 */ #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ @@ -10414,9 +8156,9 @@ #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ -/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */ +/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ -#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ @@ -10431,24 +8173,24 @@ #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ /* Register: PWM_SEQ_PTR */ -/* Description: Description cluster[0]: Beginning address in Data RAM of sequence A */ +/* Description: Description cluster[0]: Beginning address in Data RAM of this sequence */ -/* Bits 31..0 : Beginning address in Data RAM of sequence A */ +/* Bits 31..0 : Beginning address in Data RAM of this sequence */ #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: PWM_SEQ_CNT */ -/* Description: Description cluster[0]: Amount of values (duty cycles) in sequence A */ +/* Description: Description cluster[0]: Amount of values (duty cycles) in this sequence */ -/* Bits 14..0 : Amount of values (duty cycles) in sequence A */ +/* Bits 14..0 : Amount of values (duty cycles) in this sequence */ #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ /* Register: PWM_SEQ_REFRESH */ -/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ +/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register */ -/* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ +/* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ @@ -11032,6 +8774,7 @@ #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ #define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */ #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ +#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */ /* Register: RADIO_PCNF0 */ /* Description: Packet configuration register 0 */ @@ -12567,7 +10310,7 @@ #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: SPIM_FREQUENCY */ -/* Description: SPI frequency */ +/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ /* Bits 31..0 : SPI master data rate */ #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ @@ -13366,18 +11109,21 @@ #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ +#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Bit 1 : NACK received after sending the address (write '1' to clear) */ #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ +#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Bit 0 : Overrun error */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Register: TWI_ENABLE */ /* Description: Enable TWI */ @@ -13636,6 +11382,12 @@ #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ +/* Bit 0 : Overrun error */ +#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ + /* Register: TWIM_ENABLE */ /* Description: Enable TWIM */ @@ -14224,7 +11976,7 @@ /* Register: UART_BAUDRATE */ /* Description: Baud rate */ -/* Bits 31..0 : Baud-rate */ +/* Bits 31..0 : Baud rate */ #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ @@ -14234,7 +11986,9 @@ #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ +#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ +#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ @@ -14317,12 +12071,24 @@ #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ +/* Bit 7 : Enable or disable interrupt for TXDRDY event */ +#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ + /* Bit 4 : Enable or disable interrupt for ENDRX event */ #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ +/* Bit 2 : Enable or disable interrupt for RXDRDY event */ +#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ + /* Bit 1 : Enable or disable interrupt for NCTS event */ #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ @@ -14380,6 +12146,13 @@ #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ +#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ + /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ @@ -14387,6 +12160,13 @@ #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ +#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ + /* Bit 1 : Write '1' to Enable interrupt for NCTS event */ #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ @@ -14446,6 +12226,13 @@ #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ +#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ + /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ @@ -14453,6 +12240,13 @@ #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ +#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ + /* Bit 1 : Write '1' to Disable interrupt for NCTS event */ #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ @@ -14556,9 +12350,9 @@ #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: UARTE_BAUDRATE */ -/* Description: Baud rate */ +/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ -/* Bits 31..0 : Baud-rate */ +/* Bits 31..0 : Baud rate */ #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ @@ -14568,7 +12362,9 @@ #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ +#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ @@ -14669,14 +12465,14 @@ #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */ +/* Bits 5..0 : GPIO number P0.n onto which Reset is exposed */ #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: UICR_APPROTECT */ /* Description: Access Port protection */ -/* Bits 7..0 : Enable or disable Access Port protection. */ +/* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */ #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_name_change.h b/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_name_change.h index 5ce8ba4..5686b00 100644 --- a/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_name_change.h +++ b/nRF5_SDK_11.0.0_89a8197/components/device/nrf52_name_change.h @@ -1,32 +1,43 @@ -/* Copyright (c) 2015, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ +/* + +Copyright (c) 2010 - 2017, Nordic Semiconductor ASA + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + +5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + +THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS +OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE +GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ #ifndef NRF52_NAME_CHANGE_H #define NRF52_NAME_CHANGE_H @@ -60,9 +71,9 @@ #define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left #define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right - - - +/* LPCOMP */ +/* Corrected typo in RESULT register. */ +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below /*lint --flb "Leave library region" */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/gcc_startup_nrf52.S b/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/gcc_startup_nrf52.S deleted file mode 100644 index a321e72..0000000 --- a/nRF5_SDK_11.0.0_89a8197/components/toolchain/gcc/gcc_startup_nrf52.S +++ /dev/null @@ -1,524 +0,0 @@ -/* Copyright (c) 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - .syntax unified - .arch armv7e-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 8192 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 8192 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler - .long NMI_Handler - .long HardFault_Handler - .long MemoryManagement_Handler - .long BusFault_Handler - .long UsageFault_Handler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long SVC_Handler - .long DebugMonitor_Handler - .long 0 /*Reserved */ - .long PendSV_Handler - .long SysTick_Handler - - /* External Interrupts */ - .long POWER_CLOCK_IRQHandler - .long RADIO_IRQHandler - .long UARTE0_UART0_IRQHandler - .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - .long NFCT_IRQHandler - .long GPIOTE_IRQHandler - .long SAADC_IRQHandler - .long TIMER0_IRQHandler - .long TIMER1_IRQHandler - .long TIMER2_IRQHandler - .long RTC0_IRQHandler - .long TEMP_IRQHandler - .long RNG_IRQHandler - .long ECB_IRQHandler - .long CCM_AAR_IRQHandler - .long WDT_IRQHandler - .long RTC1_IRQHandler - .long QDEC_IRQHandler - .long COMP_LPCOMP_IRQHandler - .long SWI0_EGU0_IRQHandler - .long SWI1_EGU1_IRQHandler - .long SWI2_EGU2_IRQHandler - .long SWI3_EGU3_IRQHandler - .long SWI4_EGU4_IRQHandler - .long SWI5_EGU5_IRQHandler - .long TIMER3_IRQHandler - .long TIMER4_IRQHandler - .long PWM0_IRQHandler - .long PDM_IRQHandler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long MWU_IRQHandler - .long PWM1_IRQHandler - .long PWM2_IRQHandler - .long SPIM2_SPIS2_SPI2_IRQHandler - .long RTC2_IRQHandler - .long I2S_IRQHandler - .long FPU_IRQHandler - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - - .size __isr_vector, . - __isr_vector - -/* Reset Handler */ - - - .text - .thumb - .thumb_func - .align 1 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - - -/* Loop to copy data from read only memory to RAM. - * The ranges of copy from/to are specified by following symbols: - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to. - * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__bss_start__ - - subs r3, r2 - ble .L_loop1_done - -.L_loop1: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .L_loop1 - -.L_loop1_done: - -/* This part of work usually is done in C library startup code. Otherwise, - * define __STARTUP_CLEAR_BSS to enable it in this startup. This section - * clears the RAM where BSS data is located. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * All addresses must be aligned to 4 bytes boundary. - */ -#ifdef __STARTUP_CLEAR_BSS - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 - - subs r2, r1 - ble .L_loop3_done - -.L_loop3: - subs r2, #4 - str r0, [r1, r2] - bgt .L_loop3 - -.L_loop3_done: -#endif /* __STARTUP_CLEAR_BSS */ - -/* Execute SystemInit function. */ - bl SystemInit - -/* Call _start function provided by libraries. - * If those libraries are not accessible, define __START as your entry point. - */ -#ifndef __START -#define __START _start -#endif - bl __START - - .pool - .size Reset_Handler,.-Reset_Handler - - .section ".text" - - -/* Dummy Exception Handlers (infinite loops which can be modified) */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - b . - .size NMI_Handler, . - NMI_Handler - - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - b . - .size HardFault_Handler, . - HardFault_Handler - - - .weak MemoryManagement_Handler - .type MemoryManagement_Handler, %function -MemoryManagement_Handler: - b . - .size MemoryManagement_Handler, . - MemoryManagement_Handler - - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - b . - .size BusFault_Handler, . - BusFault_Handler - - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - b . - .size UsageFault_Handler, . - UsageFault_Handler - - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - b . - .size SVC_Handler, . - SVC_Handler - - - .weak DebugMonitor_Handler - .type DebugMonitor_Handler, %function -DebugMonitor_Handler: - b . - .size DebugMonitor_Handler, . - DebugMonitor_Handler - - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - b . - .size PendSV_Handler, . - PendSV_Handler - - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - b . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ POWER_CLOCK_IRQHandler - IRQ RADIO_IRQHandler - IRQ UARTE0_UART0_IRQHandler - IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler - IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler - IRQ NFCT_IRQHandler - IRQ GPIOTE_IRQHandler - IRQ SAADC_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ RTC0_IRQHandler - IRQ TEMP_IRQHandler - IRQ RNG_IRQHandler - IRQ ECB_IRQHandler - IRQ CCM_AAR_IRQHandler - IRQ WDT_IRQHandler - IRQ RTC1_IRQHandler - IRQ QDEC_IRQHandler - IRQ COMP_LPCOMP_IRQHandler - IRQ SWI0_EGU0_IRQHandler - IRQ SWI1_EGU1_IRQHandler - IRQ SWI2_EGU2_IRQHandler - IRQ SWI3_EGU3_IRQHandler - IRQ SWI4_EGU4_IRQHandler - IRQ SWI5_EGU5_IRQHandler - IRQ TIMER3_IRQHandler - IRQ TIMER4_IRQHandler - IRQ PWM0_IRQHandler - IRQ PDM_IRQHandler - IRQ MWU_IRQHandler - IRQ PWM1_IRQHandler - IRQ PWM2_IRQHandler - IRQ SPIM2_SPIS2_SPI2_IRQHandler - IRQ RTC2_IRQHandler - IRQ I2S_IRQHandler - IRQ FPU_IRQHandler - - .end diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.c b/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.c deleted file mode 100644 index 18c0754..0000000 --- a/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.c +++ /dev/null @@ -1,301 +0,0 @@ -/* Copyright (c) 2015, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include -#include -#include "nrf.h" -#include "system_nrf52.h" - -/*lint ++flb "Enter library region" */ - -#define __SYSTEM_CLOCK_64M (64000000UL) - -static bool errata_16(void); -static bool errata_31(void); -static bool errata_32(void); -static bool errata_36(void); -static bool errata_37(void); -static bool errata_57(void); -static bool errata_66(void); - - -#if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; -#elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M; -#elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; -#endif - -void SystemCoreClockUpdate(void) -{ - SystemCoreClock = __SYSTEM_CLOCK_64M; -} - -void SystemInit(void) -{ - /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_16()){ - *(volatile uint32_t *)0x4007C074 = 3131961357ul; - } - - /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_31()){ - *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; - } - - /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_32()){ - CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; - } - - /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_36()){ - NRF_CLOCK->EVENTS_DONE = 0; - NRF_CLOCK->EVENTS_CTTO = 0; - NRF_CLOCK->CTIV = 0; - } - - /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_37()){ - *(volatile uint32_t *)0x400005A0 = 0x3; - } - - /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_57()){ - *(volatile uint32_t *)0x40005610 = 0x00000005; - *(volatile uint32_t *)0x40005688 = 0x00000001; - *(volatile uint32_t *)0x40005618 = 0x00000000; - *(volatile uint32_t *)0x40005614 = 0x0000003F; - } - - /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/ */ - if (errata_66()){ - NRF_TEMP->A0 = NRF_FICR->TEMP.A0; - NRF_TEMP->A1 = NRF_FICR->TEMP.A1; - NRF_TEMP->A2 = NRF_FICR->TEMP.A2; - NRF_TEMP->A3 = NRF_FICR->TEMP.A3; - NRF_TEMP->A4 = NRF_FICR->TEMP.A4; - NRF_TEMP->A5 = NRF_FICR->TEMP.A5; - NRF_TEMP->B0 = NRF_FICR->TEMP.B0; - NRF_TEMP->B1 = NRF_FICR->TEMP.B1; - NRF_TEMP->B2 = NRF_FICR->TEMP.B2; - NRF_TEMP->B3 = NRF_FICR->TEMP.B3; - NRF_TEMP->B4 = NRF_FICR->TEMP.B4; - NRF_TEMP->B5 = NRF_FICR->TEMP.B5; - NRF_TEMP->T0 = NRF_FICR->TEMP.T0; - NRF_TEMP->T1 = NRF_FICR->TEMP.T1; - NRF_TEMP->T2 = NRF_FICR->TEMP.T2; - NRF_TEMP->T3 = NRF_FICR->TEMP.T3; - NRF_TEMP->T4 = NRF_FICR->TEMP.T4; - } - - /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the - * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit - * operations are not used in your code. */ - #if (__FPU_USED == 1) - SCB->CPACR |= (3UL << 20) | (3UL << 22); - __DSB(); - __ISB(); - #endif - - /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, - two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as - normal GPIOs. */ - #if defined (CONFIG_NFCT_PINS_AS_GPIOS) - if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NVIC_SystemReset(); - } - #endif - - /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not - defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be - reserved for PinReset and not available as normal GPIO. */ - #if defined (CONFIG_GPIO_AS_PINRESET) - if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || - ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->PSELRESET[0] = 21; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->PSELRESET[1] = 21; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NVIC_SystemReset(); - } - #endif - - /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product - Specification to see which one). */ - #if defined (ENABLE_SWO) - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; - NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - #endif - - /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product - Specification to see which ones). */ - #if defined (ENABLE_TRACE) - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; - NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - #endif - - SystemCoreClockUpdate(); -} - - -static bool errata_16(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) - { - return true; - } - } - - return false; -} - -static bool errata_31(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) - { - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) - { - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) - { - return true; - } - } - - return false; -} - -static bool errata_32(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) - { - return true; - } - } - - return false; -} - -static bool errata_36(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) - { - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) - { - return true; - } - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) - { - return true; - } - } - - return false; -} - -static bool errata_37(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) - { - return true; - } - } - - return false; -} - -static bool errata_57(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) - { - return true; - } - } - - return false; -} - -static bool errata_66(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) - { - return true; - } - } - - return false; -} - - -/*lint --flb "Leave library region" */ diff --git a/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.h b/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.h deleted file mode 100644 index d16037f..0000000 --- a/nRF5_SDK_11.0.0_89a8197/components/toolchain/system_nrf52.h +++ /dev/null @@ -1,69 +0,0 @@ -/* Copyright (c) 2015, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef SYSTEM_NRF52_H -#define SYSTEM_NRF52_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_NRF52_H */ diff --git a/src/boards.h b/src/boards.h index 1fec4ea..aca44b3 100644 --- a/src/boards.h +++ b/src/boards.h @@ -16,8 +16,8 @@ #include #include "nrf_gpio.h" -#if defined BOARD_FEATHER52 -#include "feather52.h" +#if defined BOARD_FEATHER52840 +#include "feather52840.h" #elif defined BOARD_METRO52 #include "metro52.h" #else diff --git a/src/feather52.h b/src/feather52840.h similarity index 88% rename from src/feather52.h rename to src/feather52840.h index 70d4aa6..f623934 100644 --- a/src/feather52.h +++ b/src/feather52840.h @@ -34,23 +34,23 @@ */ /**************************************************************************/ -#ifndef FEATHER52_H -#define FEATHER52_H +#ifndef _FEATHER52840_H +#define _FEATHER52840_H /*------------------------------------------------------------------*/ /* LED *------------------------------------------------------------------*/ #define LEDS_NUMBER 2 -#define LED_1 17 -#define LED_2 19 -#define LED_STATE_ON 1 +#define LED_1 13 +#define LED_2 14 +#define LED_STATE_ON 0 /*------------------------------------------------------------------*/ /* BUTTON *------------------------------------------------------------------*/ #define BUTTONS_NUMBER 2 -#define BUTTON_1 20 -#define BUTTON_2 22 +#define BUTTON_1 11 +#define BUTTON_2 12 #define BUTTON_PULL NRF_GPIO_PIN_PULLUP /*------------------------------------------------------------------*/ @@ -63,6 +63,6 @@ #define HWFC false // Used as model string in OTA mode -#define DIS_MODEL "Bluefruit Feather 52" +#define DIS_MODEL "Bluefruit Feather 52840" -#endif // FEATHER52_H +#endif // _FEATHER52840_H diff --git a/src/make_common.mk b/src/make_common.mk index 9f361cf..48e69a1 100644 --- a/src/make_common.mk +++ b/src/make_common.mk @@ -20,6 +20,8 @@ SRC_PATH = .. SD_NAME = s140 SD_VERSION = 6.0.0 +SD_NAME_UPPER = $(subst s,S,$(SD_NAME)) + SD_PATH = ../../softdevice/$(SD_NAME)/$(SD_VERSION) SD_HEX = $(SD_PATH)/hex/$(SD_NAME)_nrf52840_$(SD_VERSION)-6.alpha_softdevice.hex LINKER_SCRIPT = $(SRC_PATH)/$(SD_NAME)_$(SD_VERSION).ld @@ -32,7 +34,7 @@ BANKMODE = dual C_SOURCE_FILES += $(SDK_PATH)/libraries/bootloader_dfu/dfu_dual_bank.c endif -BOOTLOADER_S132_SUFFIX = $(VERSION_MAJOR).$(VERSION_MINOR).$(VERSION_REVISION)_$(SD_NAME)_$(BANKMODE) +BOOTLOADER_SD_SUFFIX = $(VERSION_MAJOR).$(VERSION_MINOR).$(VERSION_REVISION)_$(SD_NAME)_$(BANKMODE) FINAL_BIN_DIR := ../../bin TEMPLATE_PATH = $(SDK_PATH)/toolchain/gcc @@ -257,9 +259,9 @@ default: all #building all targets all: @$(MAKE) -s -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e clean - @echo Making Feather52 board + @echo Making Feather52840 board @echo ---------------------- - @$(MAKE) -s -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e feather52 + @$(MAKE) -s -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e feather52840 @$(MAKE) -s -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e clean @echo Making Metro52 board @echo -------------------- @@ -268,9 +270,9 @@ all: #target for printing all targets help: @echo following targets are available: - @echo - feather52 : build for Feather nrf52 board + @echo - feather52840 : build for Feather nrf52 board @echo - metro52 : build for Metro nrf52 board - @echo - flash_feather52 : flash Feather nrf52 board + @echo - flash_feather52840 : flash Feather nrf52 board @echo - flash_metro52 : flash Metro nrf52 board C_SOURCE_FILE_NAMES = $(notdir $(C_SOURCE_FILES)) @@ -288,13 +290,13 @@ OBJECTS = $(C_OBJECTS) $(ASM_OBJECTS) export OUTPUT_FILENAME export FINAL_BIN_DIR -BOOTLOADER_WITH_S132_NAME := $(OUTPUT_FILENAME)_$(BOOTLOADER_S132_SUFFIX) +BOOTLOADER_WITH_SD_NAME := $(OUTPUT_FILENAME)_$(BOOTLOADER_SD_SUFFIX) # Target for Feather nrf52 board -feather52: OUTPUT_FILENAME := feather52_bootloader -feather52: FINAL_BIN_DIR := $(FINAL_BIN_DIR)/feather52/$(VERSION_MAJOR).$(VERSION_MINOR).$(VERSION_REVISION)/$(BANKMODE) -feather52: CFLAGS += -DBOARD_FEATHER52 -feather52: $(BUILD_DIRECTORIES) $(OBJECTS) +feather52840: OUTPUT_FILENAME := feather52840_bootloader +feather52840: FINAL_BIN_DIR := $(FINAL_BIN_DIR)/feather52840/$(VERSION_MAJOR).$(VERSION_MINOR).$(VERSION_REVISION)/$(BANKMODE) +feather52840: CFLAGS += -DBOARD_FEATHER52840 +feather52840: $(BUILD_DIRECTORIES) $(OBJECTS) @echo Linking target: $(OUTPUT_FILENAME).out $(NO_ECHO)$(CC) $(LDFLAGS) $(OBJECTS) $(LIBS) -lm -o $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(NO_ECHO)$(MAKE) -f $(MAKEFILE_NAME) -C $(MAKEFILE_DIR) -e finalize @@ -331,21 +333,21 @@ finalize: genhex genbin genpkg echosize ## Create binary .hex file from the .out file genhex: - @echo Preparing: $(OUTPUT_FILENAME).hex $(BOOTLOADER_WITH_S132_NAME).hex + @echo Preparing: $(OUTPUT_FILENAME).hex $(BOOTLOADER_WITH_SD_NAME).hex $(NO_ECHO)$(OBJCOPY) -O ihex $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex - @mergehex -q -m $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex $(SD_HEX) -o $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_S132_NAME).hex + @mergehex -q -m $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex $(SD_HEX) -o $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_SD_NAME).hex @mkdir -p $(FINAL_BIN_DIR) - @cp $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_S132_NAME).hex $(FINAL_BIN_DIR)/ + @cp $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_SD_NAME).hex $(FINAL_BIN_DIR)/ ## Create .bin file genbin: - @echo Preparing: $(BOOTLOADER_WITH_S132_NAME).bin - $(NO_ECHO)$(OBJCOPY) -j .text -j .data -j .bss -O binary $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(FINAL_BIN_DIR)/$(BOOTLOADER_WITH_S132_NAME).bin + @echo Preparing: $(BOOTLOADER_WITH_SD_NAME).bin + $(NO_ECHO)$(OBJCOPY) -j .text -j .data -j .bss -O binary $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).out $(FINAL_BIN_DIR)/$(BOOTLOADER_WITH_SD_NAME).bin ## Create pkg file for bootloader only and bootloader+SD combo to use with DFU genpkg: - @echo Preparing: $(BOOTLOADER_WITH_S132_NAME).zip - @$(NRFUTIL) dfu genpkg --dev-type 0x0052 --dev-revision 0xADAF --bootloader $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex --softdevice $(SD_HEX) $(FINAL_BIN_DIR)/$(BOOTLOADER_WITH_S132_NAME).zip + @echo Preparing: $(BOOTLOADER_WITH_SD_NAME).zip + @$(NRFUTIL) dfu genpkg --dev-type 0x0052 --dev-revision 0xADAF --bootloader $(OUTPUT_BINARY_DIRECTORY)/$(OUTPUT_FILENAME).hex --softdevice $(SD_HEX) $(FINAL_BIN_DIR)/$(BOOTLOADER_WITH_SD_NAME).zip echosize: -@echo '' @@ -355,12 +357,12 @@ echosize: clean: @$(RM) $(BUILD_DIRECTORIES) -flash_feather52: BOOTLOADER_WITH_S132_NAME := feather52_bootloader_$(BOOTLOADER_S132_SUFFIX) -flash_feather52: feather52 - @echo Flashing: $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_S132_NAME).hex - nrfjprog --program $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_S132_NAME).hex -f nrf52 --chiperase --reset +flash_feather52840: BOOTLOADER_WITH_SD_NAME := feather52840_bootloader_$(BOOTLOADER_SD_SUFFIX) +flash_feather52840: feather52840 + @echo Flashing: $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_SD_NAME).hex + nrfjprog --program $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_SD_NAME).hex -f nrf52 --chiperase --reset -flash_metro52: BOOTLOADER_WITH_S132_NAME := metro52_bootloader_$(BOOTLOADER_S132_SUFFIX) +flash_metro52: BOOTLOADER_WITH_SD_NAME := metro52_bootloader_$(BOOTLOADER_SD_SUFFIX) flash_metro52: metro52 - @echo Flashing: $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_S132_NAME).hex - nrfjprog --program $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_S132_NAME).hex -f nrf52 --chiperase --reset \ No newline at end of file + @echo Flashing: $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_SD_NAME).hex + nrfjprog --program $(OUTPUT_BINARY_DIRECTORY)/$(BOOTLOADER_WITH_SD_NAME).hex -f nrf52 --chiperase --reset \ No newline at end of file