539 lines
14 KiB
Rust
539 lines
14 KiB
Rust
#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::LR {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `TCL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TCLR {
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#[doc = "Time Compensation Register is locked and writes are ignored."]
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_0,
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#[doc = "Time Compensation Register is not locked and writes complete as normal."]
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_1,
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}
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impl TCLR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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TCLR::_0 => false,
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TCLR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> TCLR {
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match value {
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false => TCLR::_0,
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true => TCLR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == TCLR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == TCLR::_1
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}
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}
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#[doc = "Possible values of the field `CRL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum CRLR {
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#[doc = "Control Register is locked and writes are ignored."]
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_0,
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#[doc = "Control Register is not locked and writes complete as normal."]
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_1,
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}
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impl CRLR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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CRLR::_0 => false,
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CRLR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> CRLR {
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match value {
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false => CRLR::_0,
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true => CRLR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == CRLR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == CRLR::_1
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}
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}
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#[doc = "Possible values of the field `SRL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SRLR {
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#[doc = "Status Register is locked and writes are ignored."]
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_0,
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#[doc = "Status Register is not locked and writes complete as normal."]
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_1,
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}
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impl SRLR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SRLR::_0 => false,
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SRLR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SRLR {
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match value {
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false => SRLR::_0,
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true => SRLR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SRLR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SRLR::_1
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}
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}
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#[doc = "Possible values of the field `LRL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum LRLR {
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#[doc = "Lock Register is locked and writes are ignored."]
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_0,
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#[doc = "Lock Register is not locked and writes complete as normal."]
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_1,
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}
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impl LRLR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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LRLR::_0 => false,
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LRLR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> LRLR {
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match value {
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false => LRLR::_0,
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true => LRLR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == LRLR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == LRLR::_1
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}
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}
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#[doc = "Values that can be written to the field `TCL`"]
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pub enum TCLW {
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#[doc = "Time Compensation Register is locked and writes are ignored."]
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_0,
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#[doc = "Time Compensation Register is not locked and writes complete as normal."]
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_1,
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}
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impl TCLW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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TCLW::_0 => false,
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TCLW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _TCLW<'a> {
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w: &'a mut W,
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}
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impl<'a> _TCLW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: TCLW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Time Compensation Register is locked and writes are ignored."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(TCLW::_0)
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}
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#[doc = "Time Compensation Register is not locked and writes complete as normal."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(TCLW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 3;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `CRL`"]
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pub enum CRLW {
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#[doc = "Control Register is locked and writes are ignored."]
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_0,
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#[doc = "Control Register is not locked and writes complete as normal."]
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_1,
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}
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impl CRLW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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CRLW::_0 => false,
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CRLW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _CRLW<'a> {
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w: &'a mut W,
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}
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impl<'a> _CRLW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: CRLW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Control Register is locked and writes are ignored."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(CRLW::_0)
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}
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#[doc = "Control Register is not locked and writes complete as normal."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(CRLW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 4;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `SRL`"]
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pub enum SRLW {
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#[doc = "Status Register is locked and writes are ignored."]
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_0,
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#[doc = "Status Register is not locked and writes complete as normal."]
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_1,
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}
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impl SRLW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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SRLW::_0 => false,
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SRLW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _SRLW<'a> {
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w: &'a mut W,
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}
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impl<'a> _SRLW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: SRLW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Status Register is locked and writes are ignored."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(SRLW::_0)
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}
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#[doc = "Status Register is not locked and writes complete as normal."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(SRLW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 5;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `LRL`"]
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pub enum LRLW {
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#[doc = "Lock Register is locked and writes are ignored."]
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_0,
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#[doc = "Lock Register is not locked and writes complete as normal."]
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_1,
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}
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impl LRLW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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LRLW::_0 => false,
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LRLW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _LRLW<'a> {
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w: &'a mut W,
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}
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impl<'a> _LRLW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: LRLW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Lock Register is locked and writes are ignored."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(LRLW::_0)
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}
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#[doc = "Lock Register is not locked and writes complete as normal."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(LRLW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 6;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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impl R {
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#[doc = r" Value of the register as raw bits"]
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#[inline]
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pub fn bits(&self) -> u32 {
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self.bits
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}
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#[doc = "Bit 3 - Time Compensation Lock"]
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#[inline]
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pub fn tcl(&self) -> TCLR {
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TCLR::_from({
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const MASK: bool = true;
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const OFFSET: u8 = 3;
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((self.bits >> OFFSET) & MASK as u32) != 0
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})
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}
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#[doc = "Bit 4 - Control Register Lock"]
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#[inline]
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pub fn crl(&self) -> CRLR {
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CRLR::_from({
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const MASK: bool = true;
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const OFFSET: u8 = 4;
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((self.bits >> OFFSET) & MASK as u32) != 0
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})
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}
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#[doc = "Bit 5 - Status Register Lock"]
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#[inline]
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pub fn srl(&self) -> SRLR {
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SRLR::_from({
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const MASK: bool = true;
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const OFFSET: u8 = 5;
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((self.bits >> OFFSET) & MASK as u32) != 0
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})
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}
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#[doc = "Bit 6 - Lock Register Lock"]
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#[inline]
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pub fn lrl(&self) -> LRLR {
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LRLR::_from({
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const MASK: bool = true;
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const OFFSET: u8 = 6;
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((self.bits >> OFFSET) & MASK as u32) != 0
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})
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}
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}
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impl W {
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#[doc = r" Reset value of the register"]
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#[inline]
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pub fn reset_value() -> W {
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W { bits: 255 }
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}
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#[doc = r" Writes raw bits to the register"]
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#[inline]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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self.bits = bits;
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self
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}
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#[doc = "Bit 3 - Time Compensation Lock"]
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#[inline]
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pub fn tcl(&mut self) -> _TCLW {
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_TCLW { w: self }
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}
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#[doc = "Bit 4 - Control Register Lock"]
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|
#[inline]
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pub fn crl(&mut self) -> _CRLW {
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|
_CRLW { w: self }
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|
}
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|
#[doc = "Bit 5 - Status Register Lock"]
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|
#[inline]
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|
pub fn srl(&mut self) -> _SRLW {
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|
_SRLW { w: self }
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|
}
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|
#[doc = "Bit 6 - Lock Register Lock"]
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|
#[inline]
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|
pub fn lrl(&mut self) -> _LRLW {
|
|
_LRLW { w: self }
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|
}
|
|
}
|