965 lines
27 KiB
Rust
965 lines
27 KiB
Rust
#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::PCR18 {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `PS`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PSR {
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#[doc = "Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
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_0,
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#[doc = "Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
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_1,
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}
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impl PSR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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PSR::_0 => false,
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PSR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> PSR {
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match value {
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false => PSR::_0,
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true => PSR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == PSR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == PSR::_1
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}
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}
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#[doc = "Possible values of the field `PE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PER {
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#[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."]
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_0,
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#[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."]
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_1,
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}
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impl PER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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PER::_0 => false,
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PER::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> PER {
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match value {
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false => PER::_0,
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true => PER::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == PER::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == PER::_1
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}
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}
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#[doc = "Possible values of the field `MUX`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum MUXR {
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#[doc = "Pin disabled (Alternative 0) (analog)."]
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_000,
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#[doc = "Alternative 1 (GPIO)."]
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_001,
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#[doc = "Alternative 2 (chip-specific)."]
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_010,
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#[doc = "Alternative 3 (chip-specific)."]
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_011,
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#[doc = "Alternative 4 (chip-specific)."]
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_100,
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#[doc = "Alternative 5 (chip-specific)."]
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_101,
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#[doc = "Alternative 6 (chip-specific)."]
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_110,
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#[doc = "Alternative 7 (chip-specific)."]
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_111,
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}
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impl MUXR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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MUXR::_000 => 0,
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MUXR::_001 => 1,
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MUXR::_010 => 2,
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MUXR::_011 => 3,
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MUXR::_100 => 4,
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MUXR::_101 => 5,
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MUXR::_110 => 6,
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MUXR::_111 => 7,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> MUXR {
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match value {
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0 => MUXR::_000,
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1 => MUXR::_001,
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2 => MUXR::_010,
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3 => MUXR::_011,
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4 => MUXR::_100,
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5 => MUXR::_101,
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6 => MUXR::_110,
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7 => MUXR::_111,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_000`"]
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#[inline]
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pub fn is_000(&self) -> bool {
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*self == MUXR::_000
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}
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#[doc = "Checks if the value of the field is `_001`"]
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#[inline]
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pub fn is_001(&self) -> bool {
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*self == MUXR::_001
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}
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#[doc = "Checks if the value of the field is `_010`"]
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#[inline]
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pub fn is_010(&self) -> bool {
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*self == MUXR::_010
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}
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#[doc = "Checks if the value of the field is `_011`"]
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#[inline]
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pub fn is_011(&self) -> bool {
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*self == MUXR::_011
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}
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#[doc = "Checks if the value of the field is `_100`"]
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#[inline]
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pub fn is_100(&self) -> bool {
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*self == MUXR::_100
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}
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#[doc = "Checks if the value of the field is `_101`"]
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#[inline]
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pub fn is_101(&self) -> bool {
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*self == MUXR::_101
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}
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#[doc = "Checks if the value of the field is `_110`"]
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#[inline]
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pub fn is_110(&self) -> bool {
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*self == MUXR::_110
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}
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#[doc = "Checks if the value of the field is `_111`"]
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#[inline]
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pub fn is_111(&self) -> bool {
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*self == MUXR::_111
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}
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}
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#[doc = "Possible values of the field `LK`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum LKR {
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#[doc = "Pin Control Register fields \\[15:0\\] are not locked."]
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_0,
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#[doc = "Pin Control Register fields \\[15:0\\] are locked and cannot be updated until the next system reset."]
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_1,
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}
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impl LKR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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LKR::_0 => false,
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LKR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> LKR {
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match value {
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false => LKR::_0,
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true => LKR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == LKR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == LKR::_1
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}
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}
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#[doc = "Possible values of the field `IRQC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum IRQCR {
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#[doc = "Interrupt Status Flag (ISF) is disabled."]
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_0000,
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#[doc = "ISF flag and DMA request on rising edge."]
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_0001,
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#[doc = "ISF flag and DMA request on falling edge."]
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_0010,
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#[doc = "ISF flag and DMA request on either edge."]
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_0011,
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#[doc = "ISF flag and Interrupt when logic 0."]
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_1000,
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#[doc = "ISF flag and Interrupt on rising-edge."]
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_1001,
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#[doc = "ISF flag and Interrupt on falling-edge."]
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_1010,
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#[doc = "ISF flag and Interrupt on either edge."]
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_1011,
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#[doc = "ISF flag and Interrupt when logic 1."]
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_1100,
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#[doc = r" Reserved"]
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_Reserved(u8),
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}
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impl IRQCR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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IRQCR::_0000 => 0,
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IRQCR::_0001 => 1,
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IRQCR::_0010 => 2,
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IRQCR::_0011 => 3,
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IRQCR::_1000 => 8,
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IRQCR::_1001 => 9,
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IRQCR::_1010 => 10,
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IRQCR::_1011 => 11,
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IRQCR::_1100 => 12,
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IRQCR::_Reserved(bits) => bits,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> IRQCR {
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match value {
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0 => IRQCR::_0000,
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1 => IRQCR::_0001,
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2 => IRQCR::_0010,
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3 => IRQCR::_0011,
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8 => IRQCR::_1000,
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9 => IRQCR::_1001,
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10 => IRQCR::_1010,
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11 => IRQCR::_1011,
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12 => IRQCR::_1100,
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i => IRQCR::_Reserved(i),
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}
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}
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#[doc = "Checks if the value of the field is `_0000`"]
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#[inline]
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pub fn is_0000(&self) -> bool {
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*self == IRQCR::_0000
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}
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#[doc = "Checks if the value of the field is `_0001`"]
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#[inline]
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pub fn is_0001(&self) -> bool {
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*self == IRQCR::_0001
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}
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#[doc = "Checks if the value of the field is `_0010`"]
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#[inline]
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pub fn is_0010(&self) -> bool {
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*self == IRQCR::_0010
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}
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#[doc = "Checks if the value of the field is `_0011`"]
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#[inline]
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pub fn is_0011(&self) -> bool {
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*self == IRQCR::_0011
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}
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#[doc = "Checks if the value of the field is `_1000`"]
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#[inline]
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pub fn is_1000(&self) -> bool {
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*self == IRQCR::_1000
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}
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#[doc = "Checks if the value of the field is `_1001`"]
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#[inline]
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pub fn is_1001(&self) -> bool {
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*self == IRQCR::_1001
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}
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#[doc = "Checks if the value of the field is `_1010`"]
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#[inline]
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pub fn is_1010(&self) -> bool {
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*self == IRQCR::_1010
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}
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#[doc = "Checks if the value of the field is `_1011`"]
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#[inline]
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pub fn is_1011(&self) -> bool {
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*self == IRQCR::_1011
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}
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|
#[doc = "Checks if the value of the field is `_1100`"]
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#[inline]
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pub fn is_1100(&self) -> bool {
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*self == IRQCR::_1100
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}
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}
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#[doc = "Possible values of the field `ISF`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum ISFR {
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#[doc = "Configured interrupt is not detected."]
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_0,
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#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
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_1,
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}
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impl ISFR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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|
#[doc = r" Value of the field as raw bits"]
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|
#[inline]
|
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pub fn bit(&self) -> bool {
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match *self {
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ISFR::_0 => false,
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|
ISFR::_1 => true,
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}
|
|
}
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|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _from(value: bool) -> ISFR {
|
|
match value {
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|
false => ISFR::_0,
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|
true => ISFR::_1,
|
|
}
|
|
}
|
|
#[doc = "Checks if the value of the field is `_0`"]
|
|
#[inline]
|
|
pub fn is_0(&self) -> bool {
|
|
*self == ISFR::_0
|
|
}
|
|
#[doc = "Checks if the value of the field is `_1`"]
|
|
#[inline]
|
|
pub fn is_1(&self) -> bool {
|
|
*self == ISFR::_1
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `PS`"]
|
|
pub enum PSW {
|
|
#[doc = "Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
|
|
_0,
|
|
#[doc = "Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
|
|
_1,
|
|
}
|
|
impl PSW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
PSW::_0 => false,
|
|
PSW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _PSW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _PSW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: PSW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(PSW::_0)
|
|
}
|
|
#[doc = "Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set."]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(PSW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 0;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `PE`"]
|
|
pub enum PEW {
|
|
#[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."]
|
|
_0,
|
|
#[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."]
|
|
_1,
|
|
}
|
|
impl PEW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
PEW::_0 => false,
|
|
PEW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _PEW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _PEW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: PEW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Internal pullup or pulldown resistor is not enabled on the corresponding pin."]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(PEW::_0)
|
|
}
|
|
#[doc = "Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input."]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(PEW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 1;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `MUX`"]
|
|
pub enum MUXW {
|
|
#[doc = "Pin disabled (Alternative 0) (analog)."]
|
|
_000,
|
|
#[doc = "Alternative 1 (GPIO)."]
|
|
_001,
|
|
#[doc = "Alternative 2 (chip-specific)."]
|
|
_010,
|
|
#[doc = "Alternative 3 (chip-specific)."]
|
|
_011,
|
|
#[doc = "Alternative 4 (chip-specific)."]
|
|
_100,
|
|
#[doc = "Alternative 5 (chip-specific)."]
|
|
_101,
|
|
#[doc = "Alternative 6 (chip-specific)."]
|
|
_110,
|
|
#[doc = "Alternative 7 (chip-specific)."]
|
|
_111,
|
|
}
|
|
impl MUXW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
MUXW::_000 => 0,
|
|
MUXW::_001 => 1,
|
|
MUXW::_010 => 2,
|
|
MUXW::_011 => 3,
|
|
MUXW::_100 => 4,
|
|
MUXW::_101 => 5,
|
|
MUXW::_110 => 6,
|
|
MUXW::_111 => 7,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _MUXW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _MUXW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: MUXW) -> &'a mut W {
|
|
{
|
|
self.bits(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Pin disabled (Alternative 0) (analog)."]
|
|
#[inline]
|
|
pub fn _000(self) -> &'a mut W {
|
|
self.variant(MUXW::_000)
|
|
}
|
|
#[doc = "Alternative 1 (GPIO)."]
|
|
#[inline]
|
|
pub fn _001(self) -> &'a mut W {
|
|
self.variant(MUXW::_001)
|
|
}
|
|
#[doc = "Alternative 2 (chip-specific)."]
|
|
#[inline]
|
|
pub fn _010(self) -> &'a mut W {
|
|
self.variant(MUXW::_010)
|
|
}
|
|
#[doc = "Alternative 3 (chip-specific)."]
|
|
#[inline]
|
|
pub fn _011(self) -> &'a mut W {
|
|
self.variant(MUXW::_011)
|
|
}
|
|
#[doc = "Alternative 4 (chip-specific)."]
|
|
#[inline]
|
|
pub fn _100(self) -> &'a mut W {
|
|
self.variant(MUXW::_100)
|
|
}
|
|
#[doc = "Alternative 5 (chip-specific)."]
|
|
#[inline]
|
|
pub fn _101(self) -> &'a mut W {
|
|
self.variant(MUXW::_101)
|
|
}
|
|
#[doc = "Alternative 6 (chip-specific)."]
|
|
#[inline]
|
|
pub fn _110(self) -> &'a mut W {
|
|
self.variant(MUXW::_110)
|
|
}
|
|
#[doc = "Alternative 7 (chip-specific)."]
|
|
#[inline]
|
|
pub fn _111(self) -> &'a mut W {
|
|
self.variant(MUXW::_111)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 8;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `LK`"]
|
|
pub enum LKW {
|
|
#[doc = "Pin Control Register fields \\[15:0\\] are not locked."]
|
|
_0,
|
|
#[doc = "Pin Control Register fields \\[15:0\\] are locked and cannot be updated until the next system reset."]
|
|
_1,
|
|
}
|
|
impl LKW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
LKW::_0 => false,
|
|
LKW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _LKW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _LKW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: LKW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Pin Control Register fields \\[15:0\\] are not locked."]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(LKW::_0)
|
|
}
|
|
#[doc = "Pin Control Register fields \\[15:0\\] are locked and cannot be updated until the next system reset."]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(LKW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 15;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `IRQC`"]
|
|
pub enum IRQCW {
|
|
#[doc = "Interrupt Status Flag (ISF) is disabled."]
|
|
_0000,
|
|
#[doc = "ISF flag and DMA request on rising edge."]
|
|
_0001,
|
|
#[doc = "ISF flag and DMA request on falling edge."]
|
|
_0010,
|
|
#[doc = "ISF flag and DMA request on either edge."]
|
|
_0011,
|
|
#[doc = "ISF flag and Interrupt when logic 0."]
|
|
_1000,
|
|
#[doc = "ISF flag and Interrupt on rising-edge."]
|
|
_1001,
|
|
#[doc = "ISF flag and Interrupt on falling-edge."]
|
|
_1010,
|
|
#[doc = "ISF flag and Interrupt on either edge."]
|
|
_1011,
|
|
#[doc = "ISF flag and Interrupt when logic 1."]
|
|
_1100,
|
|
}
|
|
impl IRQCW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
IRQCW::_0000 => 0,
|
|
IRQCW::_0001 => 1,
|
|
IRQCW::_0010 => 2,
|
|
IRQCW::_0011 => 3,
|
|
IRQCW::_1000 => 8,
|
|
IRQCW::_1001 => 9,
|
|
IRQCW::_1010 => 10,
|
|
IRQCW::_1011 => 11,
|
|
IRQCW::_1100 => 12,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _IRQCW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _IRQCW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: IRQCW) -> &'a mut W {
|
|
unsafe { self.bits(variant._bits()) }
|
|
}
|
|
#[doc = "Interrupt Status Flag (ISF) is disabled."]
|
|
#[inline]
|
|
pub fn _0000(self) -> &'a mut W {
|
|
self.variant(IRQCW::_0000)
|
|
}
|
|
#[doc = "ISF flag and DMA request on rising edge."]
|
|
#[inline]
|
|
pub fn _0001(self) -> &'a mut W {
|
|
self.variant(IRQCW::_0001)
|
|
}
|
|
#[doc = "ISF flag and DMA request on falling edge."]
|
|
#[inline]
|
|
pub fn _0010(self) -> &'a mut W {
|
|
self.variant(IRQCW::_0010)
|
|
}
|
|
#[doc = "ISF flag and DMA request on either edge."]
|
|
#[inline]
|
|
pub fn _0011(self) -> &'a mut W {
|
|
self.variant(IRQCW::_0011)
|
|
}
|
|
#[doc = "ISF flag and Interrupt when logic 0."]
|
|
#[inline]
|
|
pub fn _1000(self) -> &'a mut W {
|
|
self.variant(IRQCW::_1000)
|
|
}
|
|
#[doc = "ISF flag and Interrupt on rising-edge."]
|
|
#[inline]
|
|
pub fn _1001(self) -> &'a mut W {
|
|
self.variant(IRQCW::_1001)
|
|
}
|
|
#[doc = "ISF flag and Interrupt on falling-edge."]
|
|
#[inline]
|
|
pub fn _1010(self) -> &'a mut W {
|
|
self.variant(IRQCW::_1010)
|
|
}
|
|
#[doc = "ISF flag and Interrupt on either edge."]
|
|
#[inline]
|
|
pub fn _1011(self) -> &'a mut W {
|
|
self.variant(IRQCW::_1011)
|
|
}
|
|
#[doc = "ISF flag and Interrupt when logic 1."]
|
|
#[inline]
|
|
pub fn _1100(self) -> &'a mut W {
|
|
self.variant(IRQCW::_1100)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 16;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `ISF`"]
|
|
pub enum ISFW {
|
|
#[doc = "Configured interrupt is not detected."]
|
|
_0,
|
|
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
|
|
_1,
|
|
}
|
|
impl ISFW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
ISFW::_0 => false,
|
|
ISFW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _ISFW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _ISFW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: ISFW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Configured interrupt is not detected."]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(ISFW::_0)
|
|
}
|
|
#[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(ISFW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 24;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
impl R {
|
|
#[doc = r" Value of the register as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u32 {
|
|
self.bits
|
|
}
|
|
#[doc = "Bit 0 - Pull Select"]
|
|
#[inline]
|
|
pub fn ps(&self) -> PSR {
|
|
PSR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 0;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 1 - Pull Enable"]
|
|
#[inline]
|
|
pub fn pe(&self) -> PER {
|
|
PER::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 1;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bits 8:10 - Pin Mux Control"]
|
|
#[inline]
|
|
pub fn mux(&self) -> MUXR {
|
|
MUXR::_from({
|
|
const MASK: u8 = 7;
|
|
const OFFSET: u8 = 8;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 15 - Lock Register"]
|
|
#[inline]
|
|
pub fn lk(&self) -> LKR {
|
|
LKR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 15;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bits 16:19 - Interrupt Configuration"]
|
|
#[inline]
|
|
pub fn irqc(&self) -> IRQCR {
|
|
IRQCR::_from({
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 16;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 24 - Interrupt Status Flag"]
|
|
#[inline]
|
|
pub fn isf(&self) -> ISFR {
|
|
ISFR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 24;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
}
|
|
impl W {
|
|
#[doc = r" Reset value of the register"]
|
|
#[inline]
|
|
pub fn reset_value() -> W {
|
|
W { bits: 0 }
|
|
}
|
|
#[doc = r" Writes raw bits to the register"]
|
|
#[inline]
|
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
|
self.bits = bits;
|
|
self
|
|
}
|
|
#[doc = "Bit 0 - Pull Select"]
|
|
#[inline]
|
|
pub fn ps(&mut self) -> _PSW {
|
|
_PSW { w: self }
|
|
}
|
|
#[doc = "Bit 1 - Pull Enable"]
|
|
#[inline]
|
|
pub fn pe(&mut self) -> _PEW {
|
|
_PEW { w: self }
|
|
}
|
|
#[doc = "Bits 8:10 - Pin Mux Control"]
|
|
#[inline]
|
|
pub fn mux(&mut self) -> _MUXW {
|
|
_MUXW { w: self }
|
|
}
|
|
#[doc = "Bit 15 - Lock Register"]
|
|
#[inline]
|
|
pub fn lk(&mut self) -> _LKW {
|
|
_LKW { w: self }
|
|
}
|
|
#[doc = "Bits 16:19 - Interrupt Configuration"]
|
|
#[inline]
|
|
pub fn irqc(&mut self) -> _IRQCW {
|
|
_IRQCW { w: self }
|
|
}
|
|
#[doc = "Bit 24 - Interrupt Status Flag"]
|
|
#[inline]
|
|
pub fn isf(&mut self) -> _ISFW {
|
|
_ISFW { w: self }
|
|
}
|
|
}
|