658 lines
22 KiB
Rust
658 lines
22 KiB
Rust
#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::PSR {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `PCS`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PCSR {
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#[doc = "Prescaler/glitch filter clock 0 selected."]
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_00,
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#[doc = "Prescaler/glitch filter clock 1 selected."]
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_01,
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#[doc = "Prescaler/glitch filter clock 2 selected."]
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_10,
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#[doc = "Prescaler/glitch filter clock 3 selected."]
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_11,
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}
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impl PCSR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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PCSR::_00 => 0,
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PCSR::_01 => 1,
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PCSR::_10 => 2,
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PCSR::_11 => 3,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> PCSR {
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match value {
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0 => PCSR::_00,
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1 => PCSR::_01,
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2 => PCSR::_10,
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3 => PCSR::_11,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_00`"]
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#[inline]
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pub fn is_00(&self) -> bool {
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*self == PCSR::_00
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}
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#[doc = "Checks if the value of the field is `_01`"]
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#[inline]
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pub fn is_01(&self) -> bool {
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*self == PCSR::_01
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}
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#[doc = "Checks if the value of the field is `_10`"]
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#[inline]
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pub fn is_10(&self) -> bool {
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*self == PCSR::_10
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}
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#[doc = "Checks if the value of the field is `_11`"]
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#[inline]
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pub fn is_11(&self) -> bool {
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*self == PCSR::_11
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}
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}
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#[doc = "Possible values of the field `PBYP`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PBYPR {
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#[doc = "Prescaler/glitch filter is enabled."]
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_0,
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#[doc = "Prescaler/glitch filter is bypassed."]
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_1,
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}
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impl PBYPR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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PBYPR::_0 => false,
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PBYPR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> PBYPR {
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match value {
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false => PBYPR::_0,
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true => PBYPR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == PBYPR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == PBYPR::_1
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}
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}
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#[doc = "Possible values of the field `PRESCALE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum PRESCALER {
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#[doc = "Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration."]
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_0000,
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#[doc = "Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges."]
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_0001,
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#[doc = "Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges."]
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_0010,
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#[doc = "Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges."]
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_0011,
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#[doc = "Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges."]
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_0100,
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#[doc = "Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges."]
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_0101,
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#[doc = "Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges."]
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_0110,
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#[doc = "Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges."]
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_0111,
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#[doc = "Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges."]
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_1000,
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#[doc = "Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges."]
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_1001,
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#[doc = "Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges."]
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_1010,
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#[doc = "Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges."]
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_1011,
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#[doc = "Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges."]
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_1100,
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#[doc = "Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges."]
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_1101,
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#[doc = "Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges."]
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_1110,
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#[doc = "Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges."]
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_1111,
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}
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impl PRESCALER {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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PRESCALER::_0000 => 0,
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PRESCALER::_0001 => 1,
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PRESCALER::_0010 => 2,
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PRESCALER::_0011 => 3,
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PRESCALER::_0100 => 4,
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PRESCALER::_0101 => 5,
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PRESCALER::_0110 => 6,
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PRESCALER::_0111 => 7,
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PRESCALER::_1000 => 8,
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PRESCALER::_1001 => 9,
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PRESCALER::_1010 => 10,
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PRESCALER::_1011 => 11,
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PRESCALER::_1100 => 12,
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PRESCALER::_1101 => 13,
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PRESCALER::_1110 => 14,
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PRESCALER::_1111 => 15,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> PRESCALER {
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match value {
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0 => PRESCALER::_0000,
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1 => PRESCALER::_0001,
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2 => PRESCALER::_0010,
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3 => PRESCALER::_0011,
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4 => PRESCALER::_0100,
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5 => PRESCALER::_0101,
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6 => PRESCALER::_0110,
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7 => PRESCALER::_0111,
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8 => PRESCALER::_1000,
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9 => PRESCALER::_1001,
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10 => PRESCALER::_1010,
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11 => PRESCALER::_1011,
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12 => PRESCALER::_1100,
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13 => PRESCALER::_1101,
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14 => PRESCALER::_1110,
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15 => PRESCALER::_1111,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_0000`"]
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#[inline]
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pub fn is_0000(&self) -> bool {
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*self == PRESCALER::_0000
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}
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#[doc = "Checks if the value of the field is `_0001`"]
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#[inline]
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pub fn is_0001(&self) -> bool {
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*self == PRESCALER::_0001
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}
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#[doc = "Checks if the value of the field is `_0010`"]
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#[inline]
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pub fn is_0010(&self) -> bool {
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*self == PRESCALER::_0010
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}
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#[doc = "Checks if the value of the field is `_0011`"]
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#[inline]
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pub fn is_0011(&self) -> bool {
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*self == PRESCALER::_0011
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}
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#[doc = "Checks if the value of the field is `_0100`"]
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#[inline]
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pub fn is_0100(&self) -> bool {
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*self == PRESCALER::_0100
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}
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#[doc = "Checks if the value of the field is `_0101`"]
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#[inline]
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pub fn is_0101(&self) -> bool {
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*self == PRESCALER::_0101
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}
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#[doc = "Checks if the value of the field is `_0110`"]
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#[inline]
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pub fn is_0110(&self) -> bool {
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*self == PRESCALER::_0110
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}
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#[doc = "Checks if the value of the field is `_0111`"]
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#[inline]
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pub fn is_0111(&self) -> bool {
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*self == PRESCALER::_0111
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}
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#[doc = "Checks if the value of the field is `_1000`"]
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#[inline]
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pub fn is_1000(&self) -> bool {
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*self == PRESCALER::_1000
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}
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#[doc = "Checks if the value of the field is `_1001`"]
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#[inline]
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pub fn is_1001(&self) -> bool {
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*self == PRESCALER::_1001
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}
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#[doc = "Checks if the value of the field is `_1010`"]
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#[inline]
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pub fn is_1010(&self) -> bool {
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*self == PRESCALER::_1010
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}
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#[doc = "Checks if the value of the field is `_1011`"]
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#[inline]
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pub fn is_1011(&self) -> bool {
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*self == PRESCALER::_1011
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}
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#[doc = "Checks if the value of the field is `_1100`"]
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#[inline]
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pub fn is_1100(&self) -> bool {
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*self == PRESCALER::_1100
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}
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#[doc = "Checks if the value of the field is `_1101`"]
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#[inline]
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pub fn is_1101(&self) -> bool {
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*self == PRESCALER::_1101
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}
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#[doc = "Checks if the value of the field is `_1110`"]
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#[inline]
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pub fn is_1110(&self) -> bool {
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*self == PRESCALER::_1110
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}
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#[doc = "Checks if the value of the field is `_1111`"]
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#[inline]
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pub fn is_1111(&self) -> bool {
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*self == PRESCALER::_1111
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}
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}
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#[doc = "Values that can be written to the field `PCS`"]
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pub enum PCSW {
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#[doc = "Prescaler/glitch filter clock 0 selected."]
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_00,
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#[doc = "Prescaler/glitch filter clock 1 selected."]
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_01,
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#[doc = "Prescaler/glitch filter clock 2 selected."]
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_10,
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#[doc = "Prescaler/glitch filter clock 3 selected."]
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_11,
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}
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impl PCSW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> u8 {
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match *self {
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PCSW::_00 => 0,
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PCSW::_01 => 1,
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PCSW::_10 => 2,
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PCSW::_11 => 3,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _PCSW<'a> {
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w: &'a mut W,
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}
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impl<'a> _PCSW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: PCSW) -> &'a mut W {
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{
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self.bits(variant._bits())
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}
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}
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#[doc = "Prescaler/glitch filter clock 0 selected."]
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#[inline]
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pub fn _00(self) -> &'a mut W {
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self.variant(PCSW::_00)
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}
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#[doc = "Prescaler/glitch filter clock 1 selected."]
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#[inline]
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pub fn _01(self) -> &'a mut W {
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self.variant(PCSW::_01)
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}
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#[doc = "Prescaler/glitch filter clock 2 selected."]
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#[inline]
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pub fn _10(self) -> &'a mut W {
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self.variant(PCSW::_10)
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}
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#[doc = "Prescaler/glitch filter clock 3 selected."]
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#[inline]
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pub fn _11(self) -> &'a mut W {
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self.variant(PCSW::_11)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bits(self, value: u8) -> &'a mut W {
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const MASK: u8 = 3;
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const OFFSET: u8 = 0;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `PBYP`"]
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pub enum PBYPW {
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#[doc = "Prescaler/glitch filter is enabled."]
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_0,
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#[doc = "Prescaler/glitch filter is bypassed."]
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_1,
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}
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impl PBYPW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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PBYPW::_0 => false,
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PBYPW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _PBYPW<'a> {
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w: &'a mut W,
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}
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impl<'a> _PBYPW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: PBYPW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Prescaler/glitch filter is enabled."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(PBYPW::_0)
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}
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#[doc = "Prescaler/glitch filter is bypassed."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(PBYPW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 2;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `PRESCALE`"]
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pub enum PRESCALEW {
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#[doc = "Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration."]
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_0000,
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#[doc = "Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges."]
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_0001,
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#[doc = "Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges."]
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_0010,
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#[doc = "Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges."]
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_0011,
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#[doc = "Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges."]
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_0100,
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#[doc = "Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges."]
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_0101,
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#[doc = "Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges."]
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_0110,
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#[doc = "Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges."]
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_0111,
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#[doc = "Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges."]
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_1000,
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#[doc = "Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges."]
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_1001,
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#[doc = "Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges."]
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_1010,
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#[doc = "Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges."]
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_1011,
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#[doc = "Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges."]
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_1100,
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#[doc = "Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges."]
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_1101,
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#[doc = "Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges."]
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_1110,
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#[doc = "Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges."]
|
|
_1111,
|
|
}
|
|
impl PRESCALEW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> u8 {
|
|
match *self {
|
|
PRESCALEW::_0000 => 0,
|
|
PRESCALEW::_0001 => 1,
|
|
PRESCALEW::_0010 => 2,
|
|
PRESCALEW::_0011 => 3,
|
|
PRESCALEW::_0100 => 4,
|
|
PRESCALEW::_0101 => 5,
|
|
PRESCALEW::_0110 => 6,
|
|
PRESCALEW::_0111 => 7,
|
|
PRESCALEW::_1000 => 8,
|
|
PRESCALEW::_1001 => 9,
|
|
PRESCALEW::_1010 => 10,
|
|
PRESCALEW::_1011 => 11,
|
|
PRESCALEW::_1100 => 12,
|
|
PRESCALEW::_1101 => 13,
|
|
PRESCALEW::_1110 => 14,
|
|
PRESCALEW::_1111 => 15,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _PRESCALEW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _PRESCALEW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: PRESCALEW) -> &'a mut W {
|
|
{
|
|
self.bits(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration."]
|
|
#[inline]
|
|
pub fn _0000(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_0000)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges."]
|
|
#[inline]
|
|
pub fn _0001(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_0001)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges."]
|
|
#[inline]
|
|
pub fn _0010(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_0010)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges."]
|
|
#[inline]
|
|
pub fn _0011(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_0011)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges."]
|
|
#[inline]
|
|
pub fn _0100(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_0100)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges."]
|
|
#[inline]
|
|
pub fn _0101(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_0101)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges."]
|
|
#[inline]
|
|
pub fn _0110(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_0110)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges."]
|
|
#[inline]
|
|
pub fn _0111(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_0111)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges."]
|
|
#[inline]
|
|
pub fn _1000(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_1000)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges."]
|
|
#[inline]
|
|
pub fn _1001(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_1001)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges."]
|
|
#[inline]
|
|
pub fn _1010(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_1010)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges."]
|
|
#[inline]
|
|
pub fn _1011(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_1011)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges."]
|
|
#[inline]
|
|
pub fn _1100(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_1100)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges."]
|
|
#[inline]
|
|
pub fn _1101(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_1101)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges."]
|
|
#[inline]
|
|
pub fn _1110(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_1110)
|
|
}
|
|
#[doc = "Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges."]
|
|
#[inline]
|
|
pub fn _1111(self) -> &'a mut W {
|
|
self.variant(PRESCALEW::_1111)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bits(self, value: u8) -> &'a mut W {
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 3;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
impl R {
|
|
#[doc = r" Value of the register as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u32 {
|
|
self.bits
|
|
}
|
|
#[doc = "Bits 0:1 - Prescaler Clock Select"]
|
|
#[inline]
|
|
pub fn pcs(&self) -> PCSR {
|
|
PCSR::_from({
|
|
const MASK: u8 = 3;
|
|
const OFFSET: u8 = 0;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
#[doc = "Bit 2 - Prescaler Bypass"]
|
|
#[inline]
|
|
pub fn pbyp(&self) -> PBYPR {
|
|
PBYPR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 2;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bits 3:6 - Prescale Value"]
|
|
#[inline]
|
|
pub fn prescale(&self) -> PRESCALER {
|
|
PRESCALER::_from({
|
|
const MASK: u8 = 15;
|
|
const OFFSET: u8 = 3;
|
|
((self.bits >> OFFSET) & MASK as u32) as u8
|
|
})
|
|
}
|
|
}
|
|
impl W {
|
|
#[doc = r" Reset value of the register"]
|
|
#[inline]
|
|
pub fn reset_value() -> W {
|
|
W { bits: 0 }
|
|
}
|
|
#[doc = r" Writes raw bits to the register"]
|
|
#[inline]
|
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
|
self.bits = bits;
|
|
self
|
|
}
|
|
#[doc = "Bits 0:1 - Prescaler Clock Select"]
|
|
#[inline]
|
|
pub fn pcs(&mut self) -> _PCSW {
|
|
_PCSW { w: self }
|
|
}
|
|
#[doc = "Bit 2 - Prescaler Bypass"]
|
|
#[inline]
|
|
pub fn pbyp(&mut self) -> _PBYPW {
|
|
_PBYPW { w: self }
|
|
}
|
|
#[doc = "Bits 3:6 - Prescale Value"]
|
|
#[inline]
|
|
pub fn prescale(&mut self) -> _PRESCALEW {
|
|
_PRESCALEW { w: self }
|
|
}
|
|
}
|