772 lines
20 KiB
Rust
772 lines
20 KiB
Rust
#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::SPLLCSR {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `SPLLEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SPLLENR {
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#[doc = "System PLL is disabled"]
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_0,
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#[doc = "System PLL is enabled"]
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_1,
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}
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impl SPLLENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SPLLENR::_0 => false,
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SPLLENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SPLLENR {
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match value {
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false => SPLLENR::_0,
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true => SPLLENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SPLLENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SPLLENR::_1
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}
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}
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#[doc = "Possible values of the field `SPLLCM`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SPLLCMR {
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#[doc = "System PLL Clock Monitor is disabled"]
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_0,
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#[doc = "System PLL Clock Monitor is enabled"]
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_1,
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}
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impl SPLLCMR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SPLLCMR::_0 => false,
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SPLLCMR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SPLLCMR {
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match value {
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false => SPLLCMR::_0,
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true => SPLLCMR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SPLLCMR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SPLLCMR::_1
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}
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}
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#[doc = "Possible values of the field `SPLLCMRE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SPLLCMRER {
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#[doc = "Clock Monitor generates interrupt when error detected"]
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_0,
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#[doc = "Clock Monitor generates reset when error detected"]
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_1,
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}
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impl SPLLCMRER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SPLLCMRER::_0 => false,
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SPLLCMRER::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SPLLCMRER {
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match value {
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false => SPLLCMRER::_0,
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true => SPLLCMRER::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SPLLCMRER::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SPLLCMRER::_1
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}
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}
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#[doc = "Possible values of the field `LK`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum LKR {
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#[doc = "Control Status Register can be written."]
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_0,
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#[doc = "Control Status Register cannot be written."]
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_1,
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}
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impl LKR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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LKR::_0 => false,
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LKR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> LKR {
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match value {
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false => LKR::_0,
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true => LKR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == LKR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == LKR::_1
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}
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}
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#[doc = "Possible values of the field `SPLLVLD`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SPLLVLDR {
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#[doc = "System PLL is not enabled or clock is not valid"]
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_0,
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#[doc = "System PLL is enabled and output clock is valid"]
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_1,
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}
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impl SPLLVLDR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SPLLVLDR::_0 => false,
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SPLLVLDR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SPLLVLDR {
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match value {
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false => SPLLVLDR::_0,
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true => SPLLVLDR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SPLLVLDR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SPLLVLDR::_1
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}
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}
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#[doc = "Possible values of the field `SPLLSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SPLLSELR {
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#[doc = "System PLL is not the system clock source"]
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_0,
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#[doc = "System PLL is the system clock source"]
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_1,
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}
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impl SPLLSELR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SPLLSELR::_0 => false,
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SPLLSELR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SPLLSELR {
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match value {
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false => SPLLSELR::_0,
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true => SPLLSELR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SPLLSELR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SPLLSELR::_1
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}
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}
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#[doc = "Possible values of the field `SPLLERR`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SPLLERRR {
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#[doc = "System PLL Clock Monitor is disabled or has not detected an error"]
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_0,
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#[doc = "System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set."]
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_1,
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}
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impl SPLLERRR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SPLLERRR::_0 => false,
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SPLLERRR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SPLLERRR {
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match value {
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false => SPLLERRR::_0,
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true => SPLLERRR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SPLLERRR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SPLLERRR::_1
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}
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}
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#[doc = "Values that can be written to the field `SPLLEN`"]
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pub enum SPLLENW {
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#[doc = "System PLL is disabled"]
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_0,
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#[doc = "System PLL is enabled"]
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_1,
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}
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impl SPLLENW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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SPLLENW::_0 => false,
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SPLLENW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _SPLLENW<'a> {
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w: &'a mut W,
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}
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impl<'a> _SPLLENW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: SPLLENW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "System PLL is disabled"]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(SPLLENW::_0)
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}
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#[doc = "System PLL is enabled"]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(SPLLENW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 0;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `SPLLCM`"]
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pub enum SPLLCMW {
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#[doc = "System PLL Clock Monitor is disabled"]
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_0,
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#[doc = "System PLL Clock Monitor is enabled"]
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_1,
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}
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impl SPLLCMW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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SPLLCMW::_0 => false,
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SPLLCMW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _SPLLCMW<'a> {
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w: &'a mut W,
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}
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impl<'a> _SPLLCMW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: SPLLCMW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "System PLL Clock Monitor is disabled"]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(SPLLCMW::_0)
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}
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#[doc = "System PLL Clock Monitor is enabled"]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(SPLLCMW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 16;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `SPLLCMRE`"]
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pub enum SPLLCMREW {
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#[doc = "Clock Monitor generates interrupt when error detected"]
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_0,
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#[doc = "Clock Monitor generates reset when error detected"]
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_1,
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}
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impl SPLLCMREW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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SPLLCMREW::_0 => false,
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SPLLCMREW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _SPLLCMREW<'a> {
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w: &'a mut W,
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}
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impl<'a> _SPLLCMREW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: SPLLCMREW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Clock Monitor generates interrupt when error detected"]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(SPLLCMREW::_0)
|
|
}
|
|
#[doc = "Clock Monitor generates reset when error detected"]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(SPLLCMREW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 17;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `LK`"]
|
|
pub enum LKW {
|
|
#[doc = "Control Status Register can be written."]
|
|
_0,
|
|
#[doc = "Control Status Register cannot be written."]
|
|
_1,
|
|
}
|
|
impl LKW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
LKW::_0 => false,
|
|
LKW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _LKW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _LKW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: LKW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "Control Status Register can be written."]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(LKW::_0)
|
|
}
|
|
#[doc = "Control Status Register cannot be written."]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(LKW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 23;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
#[doc = "Values that can be written to the field `SPLLERR`"]
|
|
pub enum SPLLERRW {
|
|
#[doc = "System PLL Clock Monitor is disabled or has not detected an error"]
|
|
_0,
|
|
#[doc = "System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set."]
|
|
_1,
|
|
}
|
|
impl SPLLERRW {
|
|
#[allow(missing_docs)]
|
|
#[doc(hidden)]
|
|
#[inline]
|
|
pub fn _bits(&self) -> bool {
|
|
match *self {
|
|
SPLLERRW::_0 => false,
|
|
SPLLERRW::_1 => true,
|
|
}
|
|
}
|
|
}
|
|
#[doc = r" Proxy"]
|
|
pub struct _SPLLERRW<'a> {
|
|
w: &'a mut W,
|
|
}
|
|
impl<'a> _SPLLERRW<'a> {
|
|
#[doc = r" Writes `variant` to the field"]
|
|
#[inline]
|
|
pub fn variant(self, variant: SPLLERRW) -> &'a mut W {
|
|
{
|
|
self.bit(variant._bits())
|
|
}
|
|
}
|
|
#[doc = "System PLL Clock Monitor is disabled or has not detected an error"]
|
|
#[inline]
|
|
pub fn _0(self) -> &'a mut W {
|
|
self.variant(SPLLERRW::_0)
|
|
}
|
|
#[doc = "System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set."]
|
|
#[inline]
|
|
pub fn _1(self) -> &'a mut W {
|
|
self.variant(SPLLERRW::_1)
|
|
}
|
|
#[doc = r" Sets the field bit"]
|
|
pub fn set_bit(self) -> &'a mut W {
|
|
self.bit(true)
|
|
}
|
|
#[doc = r" Clears the field bit"]
|
|
pub fn clear_bit(self) -> &'a mut W {
|
|
self.bit(false)
|
|
}
|
|
#[doc = r" Writes raw bits to the field"]
|
|
#[inline]
|
|
pub fn bit(self, value: bool) -> &'a mut W {
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 26;
|
|
self.w.bits &= !((MASK as u32) << OFFSET);
|
|
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
|
self.w
|
|
}
|
|
}
|
|
impl R {
|
|
#[doc = r" Value of the register as raw bits"]
|
|
#[inline]
|
|
pub fn bits(&self) -> u32 {
|
|
self.bits
|
|
}
|
|
#[doc = "Bit 0 - System PLL Enable"]
|
|
#[inline]
|
|
pub fn spllen(&self) -> SPLLENR {
|
|
SPLLENR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 0;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 16 - System PLL Clock Monitor"]
|
|
#[inline]
|
|
pub fn spllcm(&self) -> SPLLCMR {
|
|
SPLLCMR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 16;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 17 - System PLL Clock Monitor Reset Enable"]
|
|
#[inline]
|
|
pub fn spllcmre(&self) -> SPLLCMRER {
|
|
SPLLCMRER::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 17;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 23 - Lock Register"]
|
|
#[inline]
|
|
pub fn lk(&self) -> LKR {
|
|
LKR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 23;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 24 - System PLL Valid"]
|
|
#[inline]
|
|
pub fn spllvld(&self) -> SPLLVLDR {
|
|
SPLLVLDR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 24;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 25 - System PLL Selected"]
|
|
#[inline]
|
|
pub fn spllsel(&self) -> SPLLSELR {
|
|
SPLLSELR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 25;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
#[doc = "Bit 26 - System PLL Clock Error"]
|
|
#[inline]
|
|
pub fn spllerr(&self) -> SPLLERRR {
|
|
SPLLERRR::_from({
|
|
const MASK: bool = true;
|
|
const OFFSET: u8 = 26;
|
|
((self.bits >> OFFSET) & MASK as u32) != 0
|
|
})
|
|
}
|
|
}
|
|
impl W {
|
|
#[doc = r" Reset value of the register"]
|
|
#[inline]
|
|
pub fn reset_value() -> W {
|
|
W { bits: 0 }
|
|
}
|
|
#[doc = r" Writes raw bits to the register"]
|
|
#[inline]
|
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
|
self.bits = bits;
|
|
self
|
|
}
|
|
#[doc = "Bit 0 - System PLL Enable"]
|
|
#[inline]
|
|
pub fn spllen(&mut self) -> _SPLLENW {
|
|
_SPLLENW { w: self }
|
|
}
|
|
#[doc = "Bit 16 - System PLL Clock Monitor"]
|
|
#[inline]
|
|
pub fn spllcm(&mut self) -> _SPLLCMW {
|
|
_SPLLCMW { w: self }
|
|
}
|
|
#[doc = "Bit 17 - System PLL Clock Monitor Reset Enable"]
|
|
#[inline]
|
|
pub fn spllcmre(&mut self) -> _SPLLCMREW {
|
|
_SPLLCMREW { w: self }
|
|
}
|
|
#[doc = "Bit 23 - Lock Register"]
|
|
#[inline]
|
|
pub fn lk(&mut self) -> _LKW {
|
|
_LKW { w: self }
|
|
}
|
|
#[doc = "Bit 26 - System PLL Clock Error"]
|
|
#[inline]
|
|
pub fn spllerr(&mut self) -> _SPLLERRW {
|
|
_SPLLERRW { w: self }
|
|
}
|
|
}
|