Regenerate crate with svd2rust v0.14.0
This commit is contained in:
Tmplt
470
src/scg/fircdiv.rs
Normal file
470
src/scg/fircdiv.rs
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@ -0,0 +1,470 @@
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#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::FIRCDIV {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `FIRCDIV1`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum FIRCDIV1R {
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#[doc = "Output disabled"]
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_000,
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#[doc = "Divide by 1"]
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_001,
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#[doc = "Divide by 2"]
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_010,
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#[doc = "Divide by 4"]
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_011,
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#[doc = "Divide by 8"]
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_100,
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#[doc = "Divide by 16"]
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_101,
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#[doc = "Divide by 32"]
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_110,
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#[doc = "Divide by 64"]
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_111,
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}
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impl FIRCDIV1R {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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FIRCDIV1R::_000 => 0,
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FIRCDIV1R::_001 => 1,
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FIRCDIV1R::_010 => 2,
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FIRCDIV1R::_011 => 3,
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FIRCDIV1R::_100 => 4,
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FIRCDIV1R::_101 => 5,
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FIRCDIV1R::_110 => 6,
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FIRCDIV1R::_111 => 7,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> FIRCDIV1R {
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match value {
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0 => FIRCDIV1R::_000,
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1 => FIRCDIV1R::_001,
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2 => FIRCDIV1R::_010,
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3 => FIRCDIV1R::_011,
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4 => FIRCDIV1R::_100,
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5 => FIRCDIV1R::_101,
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6 => FIRCDIV1R::_110,
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7 => FIRCDIV1R::_111,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_000`"]
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#[inline]
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pub fn is_000(&self) -> bool {
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*self == FIRCDIV1R::_000
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}
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#[doc = "Checks if the value of the field is `_001`"]
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#[inline]
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pub fn is_001(&self) -> bool {
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*self == FIRCDIV1R::_001
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}
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#[doc = "Checks if the value of the field is `_010`"]
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#[inline]
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pub fn is_010(&self) -> bool {
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*self == FIRCDIV1R::_010
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}
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#[doc = "Checks if the value of the field is `_011`"]
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#[inline]
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pub fn is_011(&self) -> bool {
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*self == FIRCDIV1R::_011
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}
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#[doc = "Checks if the value of the field is `_100`"]
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#[inline]
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pub fn is_100(&self) -> bool {
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*self == FIRCDIV1R::_100
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}
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#[doc = "Checks if the value of the field is `_101`"]
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#[inline]
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pub fn is_101(&self) -> bool {
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*self == FIRCDIV1R::_101
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}
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#[doc = "Checks if the value of the field is `_110`"]
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#[inline]
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pub fn is_110(&self) -> bool {
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*self == FIRCDIV1R::_110
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}
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#[doc = "Checks if the value of the field is `_111`"]
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#[inline]
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pub fn is_111(&self) -> bool {
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*self == FIRCDIV1R::_111
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}
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}
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#[doc = "Possible values of the field `FIRCDIV2`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum FIRCDIV2R {
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#[doc = "Output disabled"]
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_000,
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#[doc = "Divide by 1"]
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_001,
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#[doc = "Divide by 2"]
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_010,
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#[doc = "Divide by 4"]
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_011,
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#[doc = "Divide by 8"]
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_100,
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#[doc = "Divide by 16"]
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_101,
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#[doc = "Divide by 32"]
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_110,
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#[doc = "Divide by 64"]
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_111,
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}
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impl FIRCDIV2R {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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match *self {
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FIRCDIV2R::_000 => 0,
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FIRCDIV2R::_001 => 1,
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FIRCDIV2R::_010 => 2,
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FIRCDIV2R::_011 => 3,
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FIRCDIV2R::_100 => 4,
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FIRCDIV2R::_101 => 5,
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FIRCDIV2R::_110 => 6,
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FIRCDIV2R::_111 => 7,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: u8) -> FIRCDIV2R {
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match value {
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0 => FIRCDIV2R::_000,
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1 => FIRCDIV2R::_001,
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2 => FIRCDIV2R::_010,
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3 => FIRCDIV2R::_011,
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4 => FIRCDIV2R::_100,
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5 => FIRCDIV2R::_101,
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6 => FIRCDIV2R::_110,
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7 => FIRCDIV2R::_111,
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_ => unreachable!(),
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}
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}
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#[doc = "Checks if the value of the field is `_000`"]
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#[inline]
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pub fn is_000(&self) -> bool {
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*self == FIRCDIV2R::_000
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}
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#[doc = "Checks if the value of the field is `_001`"]
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#[inline]
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pub fn is_001(&self) -> bool {
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*self == FIRCDIV2R::_001
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}
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#[doc = "Checks if the value of the field is `_010`"]
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#[inline]
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pub fn is_010(&self) -> bool {
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*self == FIRCDIV2R::_010
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}
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#[doc = "Checks if the value of the field is `_011`"]
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#[inline]
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pub fn is_011(&self) -> bool {
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*self == FIRCDIV2R::_011
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}
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#[doc = "Checks if the value of the field is `_100`"]
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#[inline]
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pub fn is_100(&self) -> bool {
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*self == FIRCDIV2R::_100
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}
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#[doc = "Checks if the value of the field is `_101`"]
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#[inline]
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pub fn is_101(&self) -> bool {
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*self == FIRCDIV2R::_101
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}
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#[doc = "Checks if the value of the field is `_110`"]
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#[inline]
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pub fn is_110(&self) -> bool {
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*self == FIRCDIV2R::_110
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}
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#[doc = "Checks if the value of the field is `_111`"]
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#[inline]
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pub fn is_111(&self) -> bool {
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*self == FIRCDIV2R::_111
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}
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}
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#[doc = "Values that can be written to the field `FIRCDIV1`"]
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pub enum FIRCDIV1W {
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#[doc = "Output disabled"]
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_000,
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#[doc = "Divide by 1"]
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_001,
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#[doc = "Divide by 2"]
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_010,
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#[doc = "Divide by 4"]
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_011,
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#[doc = "Divide by 8"]
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_100,
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#[doc = "Divide by 16"]
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_101,
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#[doc = "Divide by 32"]
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_110,
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#[doc = "Divide by 64"]
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_111,
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}
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impl FIRCDIV1W {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> u8 {
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match *self {
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FIRCDIV1W::_000 => 0,
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FIRCDIV1W::_001 => 1,
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FIRCDIV1W::_010 => 2,
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FIRCDIV1W::_011 => 3,
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FIRCDIV1W::_100 => 4,
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FIRCDIV1W::_101 => 5,
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FIRCDIV1W::_110 => 6,
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FIRCDIV1W::_111 => 7,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _FIRCDIV1W<'a> {
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w: &'a mut W,
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}
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impl<'a> _FIRCDIV1W<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: FIRCDIV1W) -> &'a mut W {
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{
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self.bits(variant._bits())
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}
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}
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#[doc = "Output disabled"]
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#[inline]
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pub fn _000(self) -> &'a mut W {
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self.variant(FIRCDIV1W::_000)
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}
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#[doc = "Divide by 1"]
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#[inline]
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pub fn _001(self) -> &'a mut W {
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self.variant(FIRCDIV1W::_001)
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}
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#[doc = "Divide by 2"]
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#[inline]
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pub fn _010(self) -> &'a mut W {
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self.variant(FIRCDIV1W::_010)
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}
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#[doc = "Divide by 4"]
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#[inline]
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pub fn _011(self) -> &'a mut W {
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self.variant(FIRCDIV1W::_011)
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}
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#[doc = "Divide by 8"]
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#[inline]
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pub fn _100(self) -> &'a mut W {
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self.variant(FIRCDIV1W::_100)
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}
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#[doc = "Divide by 16"]
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#[inline]
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pub fn _101(self) -> &'a mut W {
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self.variant(FIRCDIV1W::_101)
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}
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#[doc = "Divide by 32"]
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#[inline]
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pub fn _110(self) -> &'a mut W {
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self.variant(FIRCDIV1W::_110)
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}
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#[doc = "Divide by 64"]
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#[inline]
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pub fn _111(self) -> &'a mut W {
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self.variant(FIRCDIV1W::_111)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bits(self, value: u8) -> &'a mut W {
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const MASK: u8 = 7;
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const OFFSET: u8 = 0;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `FIRCDIV2`"]
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pub enum FIRCDIV2W {
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#[doc = "Output disabled"]
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_000,
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#[doc = "Divide by 1"]
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_001,
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#[doc = "Divide by 2"]
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_010,
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#[doc = "Divide by 4"]
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_011,
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#[doc = "Divide by 8"]
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_100,
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#[doc = "Divide by 16"]
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_101,
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#[doc = "Divide by 32"]
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_110,
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#[doc = "Divide by 64"]
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_111,
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}
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impl FIRCDIV2W {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> u8 {
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match *self {
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FIRCDIV2W::_000 => 0,
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FIRCDIV2W::_001 => 1,
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FIRCDIV2W::_010 => 2,
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FIRCDIV2W::_011 => 3,
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FIRCDIV2W::_100 => 4,
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FIRCDIV2W::_101 => 5,
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FIRCDIV2W::_110 => 6,
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FIRCDIV2W::_111 => 7,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _FIRCDIV2W<'a> {
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w: &'a mut W,
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}
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impl<'a> _FIRCDIV2W<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: FIRCDIV2W) -> &'a mut W {
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{
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self.bits(variant._bits())
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}
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}
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#[doc = "Output disabled"]
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#[inline]
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pub fn _000(self) -> &'a mut W {
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self.variant(FIRCDIV2W::_000)
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}
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#[doc = "Divide by 1"]
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#[inline]
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pub fn _001(self) -> &'a mut W {
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self.variant(FIRCDIV2W::_001)
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}
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#[doc = "Divide by 2"]
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#[inline]
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pub fn _010(self) -> &'a mut W {
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self.variant(FIRCDIV2W::_010)
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}
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#[doc = "Divide by 4"]
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#[inline]
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pub fn _011(self) -> &'a mut W {
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self.variant(FIRCDIV2W::_011)
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}
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#[doc = "Divide by 8"]
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#[inline]
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pub fn _100(self) -> &'a mut W {
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self.variant(FIRCDIV2W::_100)
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}
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#[doc = "Divide by 16"]
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#[inline]
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pub fn _101(self) -> &'a mut W {
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self.variant(FIRCDIV2W::_101)
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}
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#[doc = "Divide by 32"]
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#[inline]
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pub fn _110(self) -> &'a mut W {
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self.variant(FIRCDIV2W::_110)
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}
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#[doc = "Divide by 64"]
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#[inline]
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pub fn _111(self) -> &'a mut W {
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self.variant(FIRCDIV2W::_111)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bits(self, value: u8) -> &'a mut W {
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const MASK: u8 = 7;
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const OFFSET: u8 = 8;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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impl R {
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#[doc = r" Value of the register as raw bits"]
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#[inline]
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pub fn bits(&self) -> u32 {
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self.bits
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}
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#[doc = "Bits 0:2 - Fast IRC Clock Divide 1"]
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#[inline]
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pub fn fircdiv1(&self) -> FIRCDIV1R {
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FIRCDIV1R::_from({
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const MASK: u8 = 7;
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const OFFSET: u8 = 0;
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((self.bits >> OFFSET) & MASK as u32) as u8
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})
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}
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#[doc = "Bits 8:10 - Fast IRC Clock Divide 2"]
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#[inline]
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pub fn fircdiv2(&self) -> FIRCDIV2R {
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FIRCDIV2R::_from({
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const MASK: u8 = 7;
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const OFFSET: u8 = 8;
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((self.bits >> OFFSET) & MASK as u32) as u8
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})
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}
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}
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impl W {
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#[doc = r" Reset value of the register"]
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#[inline]
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pub fn reset_value() -> W {
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W { bits: 0 }
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}
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#[doc = r" Writes raw bits to the register"]
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#[inline]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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self.bits = bits;
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self
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}
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#[doc = "Bits 0:2 - Fast IRC Clock Divide 1"]
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#[inline]
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pub fn fircdiv1(&mut self) -> _FIRCDIV1W {
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_FIRCDIV1W { w: self }
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}
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#[doc = "Bits 8:10 - Fast IRC Clock Divide 2"]
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#[inline]
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pub fn fircdiv2(&mut self) -> _FIRCDIV2W {
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_FIRCDIV2W { w: self }
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}
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}
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