xobs/s32k118.rs
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Regenerate crate with svd2rust v0.14.0

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This commit is contained in:
Tmplt
2019-01-16 15:39:25 +01:00
parent e96ee18df6
commit e0ddb38a51
2821 changed files with 598414 additions and 601164 deletions
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4
src/lpspi1/ccr/mod.rs → src/lpspi1/ccr.rs
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@ -22,9 +22,7 @@ impl super::CCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/lpspi1/cfgr0/mod.rs → src/lpspi1/cfgr0.rs
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@ -22,9 +22,7 @@ impl super::CFGR0 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

40
src/lpspi1/cfgr1/mod.rs → src/lpspi1/cfgr1.rs
View File

@ -22,9 +22,7 @@ impl super::CFGR1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
@ -280,13 +278,13 @@ pub enum MATCFGR {
_010,
#[doc = "011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"]
_011,
#[doc = "100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)]"]
#[doc = "100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., \\[(1st data word = MATCH0) * (2nd data word = MATCH1)\\]"]
_100,
#[doc = "101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)]"]
#[doc = "101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., \\[(any data word = MATCH0) * (next data word = MATCH1)\\]"]
_101,
#[doc = "110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]"]
#[doc = "110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., \\[(1st data word * MATCH1) = (MATCH0 * MATCH1)\\]"]
_110,
#[doc = "111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]"]
#[doc = "111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., \\[(any data word * MATCH1) = (MATCH0 * MATCH1)\\]"]
_111,
#[doc = r" Reserved"]
_Reserved(u8),
@ -463,9 +461,9 @@ impl OUTCFGR {
#[doc = "Possible values of the field `PCSCFG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCSCFGR {
#[doc = "PCS[3:2] are enabled."]
#[doc = "PCS\\[3:2\\] are enabled."]
_0,
#[doc = "PCS[3:2] are disabled."]
#[doc = "PCS\\[3:2\\] are disabled."]
_1,
}
impl PCSCFGR {
@ -795,13 +793,13 @@ pub enum MATCFGW {
_010,
#[doc = "011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)"]
_011,
#[doc = "100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)]"]
#[doc = "100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., \\[(1st data word = MATCH0) * (2nd data word = MATCH1)\\]"]
_100,
#[doc = "101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)]"]
#[doc = "101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., \\[(any data word = MATCH0) * (next data word = MATCH1)\\]"]
_101,
#[doc = "110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]"]
#[doc = "110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., \\[(1st data word * MATCH1) = (MATCH0 * MATCH1)\\]"]
_110,
#[doc = "111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]"]
#[doc = "111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., \\[(any data word * MATCH1) = (MATCH0 * MATCH1)\\]"]
_111,
}
impl MATCFGW {
@ -845,22 +843,22 @@ impl<'a> _MATCFGW<'a> {
pub fn _011(self) -> &'a mut W {
self.variant(MATCFGW::_011)
}
#[doc = "100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)]"]
#[doc = "100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., \\[(1st data word = MATCH0) * (2nd data word = MATCH1)\\]"]
#[inline]
pub fn _100(self) -> &'a mut W {
self.variant(MATCFGW::_100)
}
#[doc = "101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)]"]
#[doc = "101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., \\[(any data word = MATCH0) * (next data word = MATCH1)\\]"]
#[inline]
pub fn _101(self) -> &'a mut W {
self.variant(MATCFGW::_101)
}
#[doc = "110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)]"]
#[doc = "110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., \\[(1st data word * MATCH1) = (MATCH0 * MATCH1)\\]"]
#[inline]
pub fn _110(self) -> &'a mut W {
self.variant(MATCFGW::_110)
}
#[doc = "111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]"]
#[doc = "111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., \\[(any data word * MATCH1) = (MATCH0 * MATCH1)\\]"]
#[inline]
pub fn _111(self) -> &'a mut W {
self.variant(MATCFGW::_111)
@ -1001,9 +999,9 @@ impl<'a> _OUTCFGW<'a> {
}
#[doc = "Values that can be written to the field `PCSCFG`"]
pub enum PCSCFGW {
#[doc = "PCS[3:2] are enabled."]
#[doc = "PCS\\[3:2\\] are enabled."]
_0,
#[doc = "PCS[3:2] are disabled."]
#[doc = "PCS\\[3:2\\] are disabled."]
_1,
}
impl PCSCFGW {
@ -1029,12 +1027,12 @@ impl<'a> _PCSCFGW<'a> {
self.bit(variant._bits())
}
}
#[doc = "PCS[3:2] are enabled."]
#[doc = "PCS\\[3:2\\] are enabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(PCSCFGW::_0)
}
#[doc = "PCS[3:2] are disabled."]
#[doc = "PCS\\[3:2\\] are disabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(PCSCFGW::_1)

4
src/lpspi1/cr/mod.rs → src/lpspi1/cr.rs
View File

@ -22,9 +22,7 @@ impl super::CR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/lpspi1/der/mod.rs → src/lpspi1/der.rs
View File

@ -22,9 +22,7 @@ impl super::DER {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/lpspi1/dmr0/mod.rs → src/lpspi1/dmr0.rs
View File

@ -22,9 +22,7 @@ impl super::DMR0 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/lpspi1/dmr1/mod.rs → src/lpspi1/dmr1.rs
View File

@ -22,9 +22,7 @@ impl super::DMR1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/lpspi1/fcr/mod.rs → src/lpspi1/fcr.rs
View File

@ -22,9 +22,7 @@ impl super::FCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/lpspi1/fsr/mod.rs → src/lpspi1/fsr.rs
View File

@ -6,9 +6,7 @@ impl super::FSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/lpspi1/ier/mod.rs → src/lpspi1/ier.rs
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@ -22,9 +22,7 @@ impl super::IER {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

146
src/lpspi1/mod.rs
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@ -1,146 +0,0 @@
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Version ID Register"]
pub verid: VERID,
#[doc = "0x04 - Parameter Register"]
pub param: PARAM,
_reserved0: [u8; 8usize],
#[doc = "0x10 - Control Register"]
pub cr: CR,
#[doc = "0x14 - Status Register"]
pub sr: SR,
#[doc = "0x18 - Interrupt Enable Register"]
pub ier: IER,
#[doc = "0x1c - DMA Enable Register"]
pub der: DER,
#[doc = "0x20 - Configuration Register 0"]
pub cfgr0: CFGR0,
#[doc = "0x24 - Configuration Register 1"]
pub cfgr1: CFGR1,
_reserved1: [u8; 8usize],
#[doc = "0x30 - Data Match Register 0"]
pub dmr0: DMR0,
#[doc = "0x34 - Data Match Register 1"]
pub dmr1: DMR1,
_reserved2: [u8; 8usize],
#[doc = "0x40 - Clock Configuration Register"]
pub ccr: CCR,
_reserved3: [u8; 20usize],
#[doc = "0x58 - FIFO Control Register"]
pub fcr: FCR,
#[doc = "0x5c - FIFO Status Register"]
pub fsr: FSR,
#[doc = "0x60 - Transmit Command Register"]
pub tcr: TCR,
#[doc = "0x64 - Transmit Data Register"]
pub tdr: TDR,
_reserved4: [u8; 8usize],
#[doc = "0x70 - Receive Status Register"]
pub rsr: RSR,
#[doc = "0x74 - Receive Data Register"]
pub rdr: RDR,
}
#[doc = "Version ID Register"]
pub struct VERID {
register: VolatileCell<u32>,
}
#[doc = "Version ID Register"]
pub mod verid;
#[doc = "Parameter Register"]
pub struct PARAM {
register: VolatileCell<u32>,
}
#[doc = "Parameter Register"]
pub mod param;
#[doc = "Control Register"]
pub struct CR {
register: VolatileCell<u32>,
}
#[doc = "Control Register"]
pub mod cr;
#[doc = "Status Register"]
pub struct SR {
register: VolatileCell<u32>,
}
#[doc = "Status Register"]
pub mod sr;
#[doc = "Interrupt Enable Register"]
pub struct IER {
register: VolatileCell<u32>,
}
#[doc = "Interrupt Enable Register"]
pub mod ier;
#[doc = "DMA Enable Register"]
pub struct DER {
register: VolatileCell<u32>,
}
#[doc = "DMA Enable Register"]
pub mod der;
#[doc = "Configuration Register 0"]
pub struct CFGR0 {
register: VolatileCell<u32>,
}
#[doc = "Configuration Register 0"]
pub mod cfgr0;
#[doc = "Configuration Register 1"]
pub struct CFGR1 {
register: VolatileCell<u32>,
}
#[doc = "Configuration Register 1"]
pub mod cfgr1;
#[doc = "Data Match Register 0"]
pub struct DMR0 {
register: VolatileCell<u32>,
}
#[doc = "Data Match Register 0"]
pub mod dmr0;
#[doc = "Data Match Register 1"]
pub struct DMR1 {
register: VolatileCell<u32>,
}
#[doc = "Data Match Register 1"]
pub mod dmr1;
#[doc = "Clock Configuration Register"]
pub struct CCR {
register: VolatileCell<u32>,
}
#[doc = "Clock Configuration Register"]
pub mod ccr;
#[doc = "FIFO Control Register"]
pub struct FCR {
register: VolatileCell<u32>,
}
#[doc = "FIFO Control Register"]
pub mod fcr;
#[doc = "FIFO Status Register"]
pub struct FSR {
register: VolatileCell<u32>,
}
#[doc = "FIFO Status Register"]
pub mod fsr;
#[doc = "Transmit Command Register"]
pub struct TCR {
register: VolatileCell<u32>,
}
#[doc = "Transmit Command Register"]
pub mod tcr;
#[doc = "Transmit Data Register"]
pub struct TDR {
register: VolatileCell<u32>,
}
#[doc = "Transmit Data Register"]
pub mod tdr;
#[doc = "Receive Status Register"]
pub struct RSR {
register: VolatileCell<u32>,
}
#[doc = "Receive Status Register"]
pub mod rsr;
#[doc = "Receive Data Register"]
pub struct RDR {
register: VolatileCell<u32>,
}
#[doc = "Receive Data Register"]
pub mod rdr;

4
src/lpspi1/param/mod.rs → src/lpspi1/param.rs
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@ -6,9 +6,7 @@ impl super::PARAM {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/lpspi1/rdr/mod.rs → src/lpspi1/rdr.rs
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@ -6,9 +6,7 @@ impl super::RDR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/lpspi1/rsr/mod.rs → src/lpspi1/rsr.rs
View File

@ -6,9 +6,7 @@ impl super::RSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = "Possible values of the field `SOF`"]

4
src/lpspi1/sr/mod.rs → src/lpspi1/sr.rs
View File

@ -22,9 +22,7 @@ impl super::SR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

28
src/lpspi1/tcr/mod.rs → src/lpspi1/tcr.rs
View File

@ -22,9 +22,7 @@ impl super::TCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
@ -388,13 +386,13 @@ impl LSBFR {
#[doc = "Possible values of the field `PCS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PCSR {
#[doc = "Transfer using LPSPI_PCS[0]"]
#[doc = "Transfer using LPSPI_PCS\\[0\\]"]
_00,
#[doc = "Transfer using LPSPI_PCS[1]"]
#[doc = "Transfer using LPSPI_PCS\\[1\\]"]
_01,
#[doc = "Transfer using LPSPI_PCS[2]"]
#[doc = "Transfer using LPSPI_PCS\\[2\\]"]
_10,
#[doc = "Transfer using LPSPI_PCS[3]"]
#[doc = "Transfer using LPSPI_PCS\\[3\\]"]
_11,
}
impl PCSR {
@ -1048,13 +1046,13 @@ impl<'a> _LSBFW<'a> {
}
#[doc = "Values that can be written to the field `PCS`"]
pub enum PCSW {
#[doc = "Transfer using LPSPI_PCS[0]"]
#[doc = "Transfer using LPSPI_PCS\\[0\\]"]
_00,
#[doc = "Transfer using LPSPI_PCS[1]"]
#[doc = "Transfer using LPSPI_PCS\\[1\\]"]
_01,
#[doc = "Transfer using LPSPI_PCS[2]"]
#[doc = "Transfer using LPSPI_PCS\\[2\\]"]
_10,
#[doc = "Transfer using LPSPI_PCS[3]"]
#[doc = "Transfer using LPSPI_PCS\\[3\\]"]
_11,
}
impl PCSW {
@ -1082,22 +1080,22 @@ impl<'a> _PCSW<'a> {
self.bits(variant._bits())
}
}
#[doc = "Transfer using LPSPI_PCS[0]"]
#[doc = "Transfer using LPSPI_PCS\\[0\\]"]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(PCSW::_00)
}
#[doc = "Transfer using LPSPI_PCS[1]"]
#[doc = "Transfer using LPSPI_PCS\\[1\\]"]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(PCSW::_01)
}
#[doc = "Transfer using LPSPI_PCS[2]"]
#[doc = "Transfer using LPSPI_PCS\\[2\\]"]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(PCSW::_10)
}
#[doc = "Transfer using LPSPI_PCS[3]"]
#[doc = "Transfer using LPSPI_PCS\\[3\\]"]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(PCSW::_11)

0
src/lpspi1/tdr/mod.rs → src/lpspi1/tdr.rs
View File

4
src/lpspi1/verid/mod.rs → src/lpspi1/verid.rs
View File

@ -6,9 +6,7 @@ impl super::VERID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = "Possible values of the field `FEATURE`"]