Regenerate crate with svd2rust v0.14.0
This commit is contained in:
Tmplt
657
src/flexio/ctrl.rs
Normal file
657
src/flexio/ctrl.rs
Normal file
@ -0,0 +1,657 @@
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#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::CTRL {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `FLEXEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum FLEXENR {
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#[doc = "FlexIO module is disabled."]
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_0,
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#[doc = "FlexIO module is enabled."]
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_1,
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}
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impl FLEXENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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FLEXENR::_0 => false,
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FLEXENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> FLEXENR {
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match value {
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false => FLEXENR::_0,
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true => FLEXENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == FLEXENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == FLEXENR::_1
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}
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}
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#[doc = "Possible values of the field `SWRST`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SWRSTR {
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#[doc = "Software reset is disabled"]
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_0,
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#[doc = "Software reset is enabled, all FlexIO registers except the Control Register are reset."]
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_1,
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}
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impl SWRSTR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SWRSTR::_0 => false,
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SWRSTR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SWRSTR {
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match value {
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false => SWRSTR::_0,
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true => SWRSTR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SWRSTR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SWRSTR::_1
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}
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}
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#[doc = "Possible values of the field `FASTACC`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum FASTACCR {
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#[doc = "Configures for normal register accesses to FlexIO"]
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_0,
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#[doc = "Configures for fast register accesses to FlexIO"]
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_1,
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}
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impl FASTACCR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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FASTACCR::_0 => false,
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FASTACCR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> FASTACCR {
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match value {
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false => FASTACCR::_0,
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true => FASTACCR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == FASTACCR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == FASTACCR::_1
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}
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}
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#[doc = "Possible values of the field `DBGE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum DBGER {
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#[doc = "FlexIO is disabled in debug modes."]
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_0,
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#[doc = "FlexIO is enabled in debug modes"]
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_1,
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}
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impl DBGER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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DBGER::_0 => false,
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DBGER::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> DBGER {
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match value {
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false => DBGER::_0,
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true => DBGER::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == DBGER::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == DBGER::_1
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}
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}
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#[doc = "Possible values of the field `DOZEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum DOZENR {
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#[doc = "FlexIO enabled in Doze modes."]
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_0,
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#[doc = "FlexIO disabled in Doze modes."]
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_1,
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}
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impl DOZENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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DOZENR::_0 => false,
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DOZENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> DOZENR {
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match value {
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false => DOZENR::_0,
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true => DOZENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == DOZENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == DOZENR::_1
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}
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}
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#[doc = "Values that can be written to the field `FLEXEN`"]
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pub enum FLEXENW {
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#[doc = "FlexIO module is disabled."]
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_0,
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#[doc = "FlexIO module is enabled."]
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_1,
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}
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impl FLEXENW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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FLEXENW::_0 => false,
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FLEXENW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _FLEXENW<'a> {
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w: &'a mut W,
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}
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impl<'a> _FLEXENW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: FLEXENW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "FlexIO module is disabled."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(FLEXENW::_0)
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}
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#[doc = "FlexIO module is enabled."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(FLEXENW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 0;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `SWRST`"]
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pub enum SWRSTW {
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#[doc = "Software reset is disabled"]
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_0,
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#[doc = "Software reset is enabled, all FlexIO registers except the Control Register are reset."]
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_1,
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}
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impl SWRSTW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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SWRSTW::_0 => false,
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SWRSTW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _SWRSTW<'a> {
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w: &'a mut W,
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}
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impl<'a> _SWRSTW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: SWRSTW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Software reset is disabled"]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(SWRSTW::_0)
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}
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#[doc = "Software reset is enabled, all FlexIO registers except the Control Register are reset."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(SWRSTW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 1;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `FASTACC`"]
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pub enum FASTACCW {
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#[doc = "Configures for normal register accesses to FlexIO"]
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_0,
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#[doc = "Configures for fast register accesses to FlexIO"]
|
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_1,
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||||
}
|
||||
impl FASTACCW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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||||
FASTACCW::_0 => false,
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||||
FASTACCW::_1 => true,
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||||
}
|
||||
}
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||||
}
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#[doc = r" Proxy"]
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pub struct _FASTACCW<'a> {
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||||
w: &'a mut W,
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||||
}
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impl<'a> _FASTACCW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
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#[inline]
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pub fn variant(self, variant: FASTACCW) -> &'a mut W {
|
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{
|
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self.bit(variant._bits())
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||||
}
|
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}
|
||||
#[doc = "Configures for normal register accesses to FlexIO"]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(FASTACCW::_0)
|
||||
}
|
||||
#[doc = "Configures for fast register accesses to FlexIO"]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
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self.variant(FASTACCW::_1)
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}
|
||||
#[doc = r" Sets the field bit"]
|
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pub fn set_bit(self) -> &'a mut W {
|
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self.bit(true)
|
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}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 2;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `DBGE`"]
|
||||
pub enum DBGEW {
|
||||
#[doc = "FlexIO is disabled in debug modes."]
|
||||
_0,
|
||||
#[doc = "FlexIO is enabled in debug modes"]
|
||||
_1,
|
||||
}
|
||||
impl DBGEW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
DBGEW::_0 => false,
|
||||
DBGEW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _DBGEW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _DBGEW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: DBGEW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "FlexIO is disabled in debug modes."]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(DBGEW::_0)
|
||||
}
|
||||
#[doc = "FlexIO is enabled in debug modes"]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(DBGEW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 30;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `DOZEN`"]
|
||||
pub enum DOZENW {
|
||||
#[doc = "FlexIO enabled in Doze modes."]
|
||||
_0,
|
||||
#[doc = "FlexIO disabled in Doze modes."]
|
||||
_1,
|
||||
}
|
||||
impl DOZENW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
DOZENW::_0 => false,
|
||||
DOZENW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _DOZENW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _DOZENW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: DOZENW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "FlexIO enabled in Doze modes."]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(DOZENW::_0)
|
||||
}
|
||||
#[doc = "FlexIO disabled in Doze modes."]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(DOZENW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 31;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bit 0 - FlexIO Enable"]
|
||||
#[inline]
|
||||
pub fn flexen(&self) -> FLEXENR {
|
||||
FLEXENR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 1 - Software Reset"]
|
||||
#[inline]
|
||||
pub fn swrst(&self) -> SWRSTR {
|
||||
SWRSTR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 1;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 2 - Fast Access"]
|
||||
#[inline]
|
||||
pub fn fastacc(&self) -> FASTACCR {
|
||||
FASTACCR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 2;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 30 - Debug Enable"]
|
||||
#[inline]
|
||||
pub fn dbge(&self) -> DBGER {
|
||||
DBGER::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 30;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 31 - Doze Enable"]
|
||||
#[inline]
|
||||
pub fn dozen(&self) -> DOZENR {
|
||||
DOZENR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 31;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bit 0 - FlexIO Enable"]
|
||||
#[inline]
|
||||
pub fn flexen(&mut self) -> _FLEXENW {
|
||||
_FLEXENW { w: self }
|
||||
}
|
||||
#[doc = "Bit 1 - Software Reset"]
|
||||
#[inline]
|
||||
pub fn swrst(&mut self) -> _SWRSTW {
|
||||
_SWRSTW { w: self }
|
||||
}
|
||||
#[doc = "Bit 2 - Fast Access"]
|
||||
#[inline]
|
||||
pub fn fastacc(&mut self) -> _FASTACCW {
|
||||
_FASTACCW { w: self }
|
||||
}
|
||||
#[doc = "Bit 30 - Debug Enable"]
|
||||
#[inline]
|
||||
pub fn dbge(&mut self) -> _DBGEW {
|
||||
_DBGEW { w: self }
|
||||
}
|
||||
#[doc = "Bit 31 - Doze Enable"]
|
||||
#[inline]
|
||||
pub fn dozen(&mut self) -> _DOZENW {
|
||||
_DOZENW { w: self }
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user