xobs/s32k118.rs
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Regenerate crate with svd2rust v0.14.0

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This commit is contained in:
Tmplt
2019-01-16 15:39:25 +01:00
parent e96ee18df6
commit e0ddb38a51
2821 changed files with 598414 additions and 601164 deletions
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4
src/can0/cbt/mod.rs → src/can0/cbt.rs
View File

@ -22,9 +22,7 @@ impl super::CBT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/crcr/mod.rs → src/can0/crcr.rs
View File

@ -6,9 +6,7 @@ impl super::CRCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/ctrl1/mod.rs → src/can0/ctrl1.rs
View File

@ -22,9 +22,7 @@ impl super::CTRL1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/ctrl1_pn/mod.rs → src/can0/ctrl1_pn.rs
View File

@ -22,9 +22,7 @@ impl super::CTRL1_PN {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/ctrl2/mod.rs → src/can0/ctrl2.rs
View File

@ -22,9 +22,7 @@ impl super::CTRL2 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/ctrl2_pn/mod.rs → src/can0/ctrl2_pn.rs
View File

@ -22,9 +22,7 @@ impl super::CTRL2_PN {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/ecr/mod.rs → src/can0/ecr.rs
View File

@ -22,9 +22,7 @@ impl super::ECR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/embedded_ram/mod.rs → src/can0/embedded_ram.rs
View File

@ -22,9 +22,7 @@ impl super::EMBEDDEDRAM {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/esr1/mod.rs → src/can0/esr1.rs
View File

@ -22,9 +22,7 @@ impl super::ESR1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

8
src/can0/esr2/mod.rs → src/can0/esr2.rs
View File

@ -6,17 +6,15 @@ impl super::ESR2 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = "Possible values of the field `IMB`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IMBR {
#[doc = "If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox."]
#[doc = "If ESR2\\[VPS\\] is asserted, the ESR2\\[LPTM\\] is not an inactive Mailbox."]
_0,
#[doc = "If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one."]
#[doc = "If ESR2\\[VPS\\] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one."]
_1,
}
impl IMBR {

4
src/can0/fdcbt/mod.rs → src/can0/fdcbt.rs
View File

@ -22,9 +22,7 @@ impl super::FDCBT {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/fdcrc/mod.rs → src/can0/fdcrc.rs
View File

@ -6,9 +6,7 @@ impl super::FDCRC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/fdctrl/mod.rs → src/can0/fdctrl.rs
View File

@ -22,9 +22,7 @@ impl super::FDCTRL {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/flt_dlc/mod.rs → src/can0/flt_dlc.rs
View File

@ -22,9 +22,7 @@ impl super::FLT_DLC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/flt_id1/mod.rs → src/can0/flt_id1.rs
View File

@ -22,9 +22,7 @@ impl super::FLT_ID1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/flt_id2_idmask/mod.rs → src/can0/flt_id2_idmask.rs
View File

@ -22,9 +22,7 @@ impl super::FLT_ID2_IDMASK {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

52
src/can0/iflag1/mod.rs → src/can0/iflag1.rs
View File

@ -22,9 +22,7 @@ impl super::IFLAG1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
@ -45,9 +43,9 @@ impl super::IFLAG1 {
#[doc = "Possible values of the field `BUF0I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BUF0IR {
#[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0."]
#[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR\\[RFEN\\]=0."]
_0,
#[doc = "The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0."]
#[doc = "The corresponding buffer has successfully completed transmission or reception when MCR\\[RFEN\\]=0."]
_1,
}
impl BUF0IR {
@ -103,9 +101,9 @@ impl BUF4TO1IR {
#[doc = "Possible values of the field `BUF5I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BUF5IR {
#[doc = "No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1"]
#[doc = "No occurrence of MB5 completing transmission/reception when MCR\\[RFEN\\]=0, or of frame(s) available in the FIFO, when MCR\\[RFEN\\]=1"]
_0,
#[doc = "MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled."]
#[doc = "MB5 completed transmission/reception when MCR\\[RFEN\\]=0, or frame(s) available in the Rx FIFO when MCR\\[RFEN\\]=1. It generates a DMA request in case of MCR\\[RFEN\\] and MCR\\[DMA\\] are enabled."]
_1,
}
impl BUF5IR {
@ -150,9 +148,9 @@ impl BUF5IR {
#[doc = "Possible values of the field `BUF6I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BUF6IR {
#[doc = "No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1"]
#[doc = "No occurrence of MB6 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO almost full when MCR\\[RFEN\\]=1"]
_0,
#[doc = "MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1"]
#[doc = "MB6 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO almost full when MCR\\[RFEN\\]=1"]
_1,
}
impl BUF6IR {
@ -197,9 +195,9 @@ impl BUF6IR {
#[doc = "Possible values of the field `BUF7I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BUF7IR {
#[doc = "No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1"]
#[doc = "No occurrence of MB7 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO overflow when MCR\\[RFEN\\]=1"]
_0,
#[doc = "MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1"]
#[doc = "MB7 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO overflow when MCR\\[RFEN\\]=1"]
_1,
}
impl BUF7IR {
@ -254,9 +252,9 @@ impl BUF31TO8IR {
}
#[doc = "Values that can be written to the field `BUF0I`"]
pub enum BUF0IW {
#[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0."]
#[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR\\[RFEN\\]=0."]
_0,
#[doc = "The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0."]
#[doc = "The corresponding buffer has successfully completed transmission or reception when MCR\\[RFEN\\]=0."]
_1,
}
impl BUF0IW {
@ -282,12 +280,12 @@ impl<'a> _BUF0IW<'a> {
self.bit(variant._bits())
}
}
#[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0."]
#[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR\\[RFEN\\]=0."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(BUF0IW::_0)
}
#[doc = "The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0."]
#[doc = "The corresponding buffer has successfully completed transmission or reception when MCR\\[RFEN\\]=0."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(BUF0IW::_1)
@ -327,9 +325,9 @@ impl<'a> _BUF4TO1IW<'a> {
}
#[doc = "Values that can be written to the field `BUF5I`"]
pub enum BUF5IW {
#[doc = "No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1"]
#[doc = "No occurrence of MB5 completing transmission/reception when MCR\\[RFEN\\]=0, or of frame(s) available in the FIFO, when MCR\\[RFEN\\]=1"]
_0,
#[doc = "MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled."]
#[doc = "MB5 completed transmission/reception when MCR\\[RFEN\\]=0, or frame(s) available in the Rx FIFO when MCR\\[RFEN\\]=1. It generates a DMA request in case of MCR\\[RFEN\\] and MCR\\[DMA\\] are enabled."]
_1,
}
impl BUF5IW {
@ -355,12 +353,12 @@ impl<'a> _BUF5IW<'a> {
self.bit(variant._bits())
}
}
#[doc = "No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1"]
#[doc = "No occurrence of MB5 completing transmission/reception when MCR\\[RFEN\\]=0, or of frame(s) available in the FIFO, when MCR\\[RFEN\\]=1"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(BUF5IW::_0)
}
#[doc = "MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled."]
#[doc = "MB5 completed transmission/reception when MCR\\[RFEN\\]=0, or frame(s) available in the Rx FIFO when MCR\\[RFEN\\]=1. It generates a DMA request in case of MCR\\[RFEN\\] and MCR\\[DMA\\] are enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(BUF5IW::_1)
@ -385,9 +383,9 @@ impl<'a> _BUF5IW<'a> {
}
#[doc = "Values that can be written to the field `BUF6I`"]
pub enum BUF6IW {
#[doc = "No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1"]
#[doc = "No occurrence of MB6 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO almost full when MCR\\[RFEN\\]=1"]
_0,
#[doc = "MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1"]
#[doc = "MB6 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO almost full when MCR\\[RFEN\\]=1"]
_1,
}
impl BUF6IW {
@ -413,12 +411,12 @@ impl<'a> _BUF6IW<'a> {
self.bit(variant._bits())
}
}
#[doc = "No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1"]
#[doc = "No occurrence of MB6 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO almost full when MCR\\[RFEN\\]=1"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(BUF6IW::_0)
}
#[doc = "MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1"]
#[doc = "MB6 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO almost full when MCR\\[RFEN\\]=1"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(BUF6IW::_1)
@ -443,9 +441,9 @@ impl<'a> _BUF6IW<'a> {
}
#[doc = "Values that can be written to the field `BUF7I`"]
pub enum BUF7IW {
#[doc = "No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1"]
#[doc = "No occurrence of MB7 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO overflow when MCR\\[RFEN\\]=1"]
_0,
#[doc = "MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1"]
#[doc = "MB7 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO overflow when MCR\\[RFEN\\]=1"]
_1,
}
impl BUF7IW {
@ -471,12 +469,12 @@ impl<'a> _BUF7IW<'a> {
self.bit(variant._bits())
}
}
#[doc = "No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1"]
#[doc = "No occurrence of MB7 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO overflow when MCR\\[RFEN\\]=1"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(BUF7IW::_0)
}
#[doc = "MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1"]
#[doc = "MB7 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO overflow when MCR\\[RFEN\\]=1"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(BUF7IW::_1)

4
src/can0/imask1/mod.rs → src/can0/imask1.rs
View File

@ -22,9 +22,7 @@ impl super::IMASK1 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/mcr/mod.rs → src/can0/mcr.rs
View File

@ -22,9 +22,7 @@ impl super::MCR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

390
src/can0/mod.rs
View File

@ -1,390 +0,0 @@
use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Module Configuration Register"]
pub mcr: MCR,
#[doc = "0x04 - Control 1 register"]
pub ctrl1: CTRL1,
#[doc = "0x08 - Free Running Timer"]
pub timer: TIMER,
_reserved0: [u8; 4usize],
#[doc = "0x10 - Rx Mailboxes Global Mask Register"]
pub rxmgmask: RXMGMASK,
#[doc = "0x14 - Rx 14 Mask register"]
pub rx14mask: RX14MASK,
#[doc = "0x18 - Rx 15 Mask register"]
pub rx15mask: RX15MASK,
#[doc = "0x1c - Error Counter"]
pub ecr: ECR,
#[doc = "0x20 - Error and Status 1 register"]
pub esr1: ESR1,
_reserved1: [u8; 4usize],
#[doc = "0x28 - Interrupt Masks 1 register"]
pub imask1: IMASK1,
_reserved2: [u8; 4usize],
#[doc = "0x30 - Interrupt Flags 1 register"]
pub iflag1: IFLAG1,
#[doc = "0x34 - Control 2 register"]
pub ctrl2: CTRL2,
#[doc = "0x38 - Error and Status 2 register"]
pub esr2: ESR2,
_reserved3: [u8; 8usize],
#[doc = "0x44 - CRC Register"]
pub crcr: CRCR,
#[doc = "0x48 - Rx FIFO Global Mask register"]
pub rxfgmask: RXFGMASK,
#[doc = "0x4c - Rx FIFO Information Register"]
pub rxfir: RXFIR,
#[doc = "0x50 - CAN Bit Timing Register"]
pub cbt: CBT,
_reserved4: [u8; 44usize],
#[doc = "0x80 - Embedded RAM"]
pub embedded_ram: [EMBEDDEDRAM; 128],
_reserved5: [u8; 1536usize],
#[doc = "0x880 - Rx Individual Mask Registers"]
pub rximr: [RXIMR; 16],
_reserved6: [u8; 576usize],
#[doc = "0xb00 - Pretended Networking Control 1 Register"]
pub ctrl1_pn: CTRL1_PN,
#[doc = "0xb04 - Pretended Networking Control 2 Register"]
pub ctrl2_pn: CTRL2_PN,
#[doc = "0xb08 - Pretended Networking Wake Up Match Register"]
pub wu_mtc: WU_MTC,
#[doc = "0xb0c - Pretended Networking ID Filter 1 Register"]
pub flt_id1: FLT_ID1,
#[doc = "0xb10 - Pretended Networking DLC Filter Register"]
pub flt_dlc: FLT_DLC,
#[doc = "0xb14 - Pretended Networking Payload Low Filter 1 Register"]
pub pl1_lo: PL1_LO,
#[doc = "0xb18 - Pretended Networking Payload High Filter 1 Register"]
pub pl1_hi: PL1_HI,
#[doc = "0xb1c - Pretended Networking ID Filter 2 Register / ID Mask Register"]
pub flt_id2_idmask: FLT_ID2_IDMASK,
#[doc = "0xb20 - Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"]
pub pl2_plmask_lo: PL2_PLMASK_LO,
#[doc = "0xb24 - Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"]
pub pl2_plmask_hi: PL2_PLMASK_HI,
_reserved7: [u8; 24usize],
#[doc = "0xb40 - Wake Up Message Buffer Register for C/S"]
pub wmb0_cs: WMB0_CS,
#[doc = "0xb44 - Wake Up Message Buffer Register for ID"]
pub wmb0_id: WMB0_ID,
#[doc = "0xb48 - Wake Up Message Buffer Register for Data 0-3"]
pub wmb0_d03: WMB0_D03,
#[doc = "0xb4c - Wake Up Message Buffer Register Data 4-7"]
pub wmb0_d47: WMB0_D47,
#[doc = "0xb50 - Wake Up Message Buffer Register for C/S"]
pub wmb1_cs: WMB1_CS,
#[doc = "0xb54 - Wake Up Message Buffer Register for ID"]
pub wmb1_id: WMB1_ID,
#[doc = "0xb58 - Wake Up Message Buffer Register for Data 0-3"]
pub wmb1_d03: WMB1_D03,
#[doc = "0xb5c - Wake Up Message Buffer Register Data 4-7"]
pub wmb1_d47: WMB1_D47,
#[doc = "0xb60 - Wake Up Message Buffer Register for C/S"]
pub wmb2_cs: WMB2_CS,
#[doc = "0xb64 - Wake Up Message Buffer Register for ID"]
pub wmb2_id: WMB2_ID,
#[doc = "0xb68 - Wake Up Message Buffer Register for Data 0-3"]
pub wmb2_d03: WMB2_D03,
#[doc = "0xb6c - Wake Up Message Buffer Register Data 4-7"]
pub wmb2_d47: WMB2_D47,
#[doc = "0xb70 - Wake Up Message Buffer Register for C/S"]
pub wmb3_cs: WMB3_CS,
#[doc = "0xb74 - Wake Up Message Buffer Register for ID"]
pub wmb3_id: WMB3_ID,
#[doc = "0xb78 - Wake Up Message Buffer Register for Data 0-3"]
pub wmb3_d03: WMB3_D03,
#[doc = "0xb7c - Wake Up Message Buffer Register Data 4-7"]
pub wmb3_d47: WMB3_D47,
_reserved8: [u8; 128usize],
#[doc = "0xc00 - CAN FD Control Register"]
pub fdctrl: FDCTRL,
#[doc = "0xc04 - CAN FD Bit Timing Register"]
pub fdcbt: FDCBT,
#[doc = "0xc08 - CAN FD CRC Register"]
pub fdcrc: FDCRC,
}
#[doc = "Module Configuration Register"]
pub struct MCR {
register: VolatileCell<u32>,
}
#[doc = "Module Configuration Register"]
pub mod mcr;
#[doc = "Control 1 register"]
pub struct CTRL1 {
register: VolatileCell<u32>,
}
#[doc = "Control 1 register"]
pub mod ctrl1;
#[doc = "Free Running Timer"]
pub struct TIMER {
register: VolatileCell<u32>,
}
#[doc = "Free Running Timer"]
pub mod timer;
#[doc = "Rx Mailboxes Global Mask Register"]
pub struct RXMGMASK {
register: VolatileCell<u32>,
}
#[doc = "Rx Mailboxes Global Mask Register"]
pub mod rxmgmask;
#[doc = "Rx 14 Mask register"]
pub struct RX14MASK {
register: VolatileCell<u32>,
}
#[doc = "Rx 14 Mask register"]
pub mod rx14mask;
#[doc = "Rx 15 Mask register"]
pub struct RX15MASK {
register: VolatileCell<u32>,
}
#[doc = "Rx 15 Mask register"]
pub mod rx15mask;
#[doc = "Error Counter"]
pub struct ECR {
register: VolatileCell<u32>,
}
#[doc = "Error Counter"]
pub mod ecr;
#[doc = "Error and Status 1 register"]
pub struct ESR1 {
register: VolatileCell<u32>,
}
#[doc = "Error and Status 1 register"]
pub mod esr1;
#[doc = "Interrupt Masks 1 register"]
pub struct IMASK1 {
register: VolatileCell<u32>,
}
#[doc = "Interrupt Masks 1 register"]
pub mod imask1;
#[doc = "Interrupt Flags 1 register"]
pub struct IFLAG1 {
register: VolatileCell<u32>,
}
#[doc = "Interrupt Flags 1 register"]
pub mod iflag1;
#[doc = "Control 2 register"]
pub struct CTRL2 {
register: VolatileCell<u32>,
}
#[doc = "Control 2 register"]
pub mod ctrl2;
#[doc = "Error and Status 2 register"]
pub struct ESR2 {
register: VolatileCell<u32>,
}
#[doc = "Error and Status 2 register"]
pub mod esr2;
#[doc = "CRC Register"]
pub struct CRCR {
register: VolatileCell<u32>,
}
#[doc = "CRC Register"]
pub mod crcr;
#[doc = "Rx FIFO Global Mask register"]
pub struct RXFGMASK {
register: VolatileCell<u32>,
}
#[doc = "Rx FIFO Global Mask register"]
pub mod rxfgmask;
#[doc = "Rx FIFO Information Register"]
pub struct RXFIR {
register: VolatileCell<u32>,
}
#[doc = "Rx FIFO Information Register"]
pub mod rxfir;
#[doc = "CAN Bit Timing Register"]
pub struct CBT {
register: VolatileCell<u32>,
}
#[doc = "CAN Bit Timing Register"]
pub mod cbt;
#[doc = "Embedded RAM"]
pub struct EMBEDDEDRAM {
register: VolatileCell<u32>,
}
#[doc = "Embedded RAM"]
pub mod embedded_ram;
#[doc = "Rx Individual Mask Registers"]
pub struct RXIMR {
register: VolatileCell<u32>,
}
#[doc = "Rx Individual Mask Registers"]
pub mod rximr;
#[doc = "Pretended Networking Control 1 Register"]
pub struct CTRL1_PN {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Control 1 Register"]
pub mod ctrl1_pn;
#[doc = "Pretended Networking Control 2 Register"]
pub struct CTRL2_PN {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Control 2 Register"]
pub mod ctrl2_pn;
#[doc = "Pretended Networking Wake Up Match Register"]
pub struct WU_MTC {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Wake Up Match Register"]
pub mod wu_mtc;
#[doc = "Pretended Networking ID Filter 1 Register"]
pub struct FLT_ID1 {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking ID Filter 1 Register"]
pub mod flt_id1;
#[doc = "Pretended Networking DLC Filter Register"]
pub struct FLT_DLC {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking DLC Filter Register"]
pub mod flt_dlc;
#[doc = "Pretended Networking Payload Low Filter 1 Register"]
pub struct PL1_LO {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Payload Low Filter 1 Register"]
pub mod pl1_lo;
#[doc = "Pretended Networking Payload High Filter 1 Register"]
pub struct PL1_HI {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Payload High Filter 1 Register"]
pub mod pl1_hi;
#[doc = "Pretended Networking ID Filter 2 Register / ID Mask Register"]
pub struct FLT_ID2_IDMASK {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking ID Filter 2 Register / ID Mask Register"]
pub mod flt_id2_idmask;
#[doc = "Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"]
pub struct PL2_PLMASK_LO {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"]
pub mod pl2_plmask_lo;
#[doc = "Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"]
pub struct PL2_PLMASK_HI {
register: VolatileCell<u32>,
}
#[doc = "Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"]
pub mod pl2_plmask_hi;
#[doc = "Wake Up Message Buffer Register for C/S"]
pub struct WMB0_CS {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for C/S"]
pub mod wmb0_cs;
#[doc = "Wake Up Message Buffer Register for ID"]
pub struct WMB0_ID {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for ID"]
pub mod wmb0_id;
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub struct WMB0_D03 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub mod wmb0_d03;
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub struct WMB0_D47 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub mod wmb0_d47;
#[doc = "Wake Up Message Buffer Register for C/S"]
pub struct WMB1_CS {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for C/S"]
pub mod wmb1_cs;
#[doc = "Wake Up Message Buffer Register for ID"]
pub struct WMB1_ID {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for ID"]
pub mod wmb1_id;
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub struct WMB1_D03 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub mod wmb1_d03;
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub struct WMB1_D47 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub mod wmb1_d47;
#[doc = "Wake Up Message Buffer Register for C/S"]
pub struct WMB2_CS {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for C/S"]
pub mod wmb2_cs;
#[doc = "Wake Up Message Buffer Register for ID"]
pub struct WMB2_ID {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for ID"]
pub mod wmb2_id;
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub struct WMB2_D03 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub mod wmb2_d03;
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub struct WMB2_D47 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub mod wmb2_d47;
#[doc = "Wake Up Message Buffer Register for C/S"]
pub struct WMB3_CS {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for C/S"]
pub mod wmb3_cs;
#[doc = "Wake Up Message Buffer Register for ID"]
pub struct WMB3_ID {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for ID"]
pub mod wmb3_id;
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub struct WMB3_D03 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register for Data 0-3"]
pub mod wmb3_d03;
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub struct WMB3_D47 {
register: VolatileCell<u32>,
}
#[doc = "Wake Up Message Buffer Register Data 4-7"]
pub mod wmb3_d47;
#[doc = "CAN FD Control Register"]
pub struct FDCTRL {
register: VolatileCell<u32>,
}
#[doc = "CAN FD Control Register"]
pub mod fdctrl;
#[doc = "CAN FD Bit Timing Register"]
pub struct FDCBT {
register: VolatileCell<u32>,
}
#[doc = "CAN FD Bit Timing Register"]
pub mod fdcbt;
#[doc = "CAN FD CRC Register"]
pub struct FDCRC {
register: VolatileCell<u32>,
}
#[doc = "CAN FD CRC Register"]
pub mod fdcrc;

4
src/can0/pl1_hi/mod.rs → src/can0/pl1_hi.rs
View File

@ -22,9 +22,7 @@ impl super::PL1_HI {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/pl1_lo/mod.rs → src/can0/pl1_lo.rs
View File

@ -22,9 +22,7 @@ impl super::PL1_LO {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/pl2_plmask_hi/mod.rs → src/can0/pl2_plmask_hi.rs
View File

@ -22,9 +22,7 @@ impl super::PL2_PLMASK_HI {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/pl2_plmask_lo/mod.rs → src/can0/pl2_plmask_lo.rs
View File

@ -22,9 +22,7 @@ impl super::PL2_PLMASK_LO {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rx14mask/mod.rs → src/can0/rx14mask.rs
View File

@ -22,9 +22,7 @@ impl super::RX14MASK {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rx15mask/mod.rs → src/can0/rx15mask.rs
View File

@ -22,9 +22,7 @@ impl super::RX15MASK {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rxfgmask/mod.rs → src/can0/rxfgmask.rs
View File

@ -22,9 +22,7 @@ impl super::RXFGMASK {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rxfir/mod.rs → src/can0/rxfir.rs
View File

@ -6,9 +6,7 @@ impl super::RXFIR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/rximr/mod.rs → src/can0/rximr.rs
View File

@ -22,9 +22,7 @@ impl super::RXIMR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/rxmgmask/mod.rs → src/can0/rxmgmask.rs
View File

@ -22,9 +22,7 @@ impl super::RXMGMASK {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/timer/mod.rs → src/can0/timer.rs
View File

@ -22,9 +22,7 @@ impl super::TIMER {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]

4
src/can0/wmb0_cs/mod.rs → src/can0/wmb0_cs.rs
View File

@ -6,9 +6,7 @@ impl super::WMB0_CS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb0_d03/mod.rs → src/can0/wmb0_d03.rs
View File

@ -6,9 +6,7 @@ impl super::WMB0_D03 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb0_d47/mod.rs → src/can0/wmb0_d47.rs
View File

@ -6,9 +6,7 @@ impl super::WMB0_D47 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb0_id/mod.rs → src/can0/wmb0_id.rs
View File

@ -6,9 +6,7 @@ impl super::WMB0_ID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb1_cs/mod.rs → src/can0/wmb1_cs.rs
View File

@ -6,9 +6,7 @@ impl super::WMB1_CS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb1_d03/mod.rs → src/can0/wmb1_d03.rs
View File

@ -6,9 +6,7 @@ impl super::WMB1_D03 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb1_d47/mod.rs → src/can0/wmb1_d47.rs
View File

@ -6,9 +6,7 @@ impl super::WMB1_D47 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb1_id/mod.rs → src/can0/wmb1_id.rs
View File

@ -6,9 +6,7 @@ impl super::WMB1_ID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb2_cs/mod.rs → src/can0/wmb2_cs.rs
View File

@ -6,9 +6,7 @@ impl super::WMB2_CS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb2_d03/mod.rs → src/can0/wmb2_d03.rs
View File

@ -6,9 +6,7 @@ impl super::WMB2_D03 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb2_d47/mod.rs → src/can0/wmb2_d47.rs
View File

@ -6,9 +6,7 @@ impl super::WMB2_D47 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb2_id/mod.rs → src/can0/wmb2_id.rs
View File

@ -6,9 +6,7 @@ impl super::WMB2_ID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb3_cs/mod.rs → src/can0/wmb3_cs.rs
View File

@ -6,9 +6,7 @@ impl super::WMB3_CS {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb3_d03/mod.rs → src/can0/wmb3_d03.rs
View File

@ -6,9 +6,7 @@ impl super::WMB3_D03 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb3_d47/mod.rs → src/can0/wmb3_d47.rs
View File

@ -6,9 +6,7 @@ impl super::WMB3_D47 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wmb3_id/mod.rs → src/can0/wmb3_id.rs
View File

@ -6,9 +6,7 @@ impl super::WMB3_ID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]

4
src/can0/wu_mtc/mod.rs → src/can0/wu_mtc.rs
View File

@ -22,9 +22,7 @@ impl super::WU_MTC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]