Regenerate crate with svd2rust v0.14.0
This commit is contained in:
Tmplt
@ -22,9 +22,7 @@ impl super::BASE_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CFG1 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CFG2 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLP0 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLP0_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLP1 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLP1_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLP2 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLP2_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLP3 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLP3_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLP9 {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLP9_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLPS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLPS_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLPX {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CLPX_OFS {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::CV {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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@ -22,9 +22,7 @@ impl super::G {
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R {
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bits: self.register.get(),
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}
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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291
src/adc0/mod.rs
291
src/adc0/mod.rs
@ -1,291 +0,0 @@
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use vcell::VolatileCell;
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#[doc = r" Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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#[doc = "0x00 - ADC Status and Control Register 1"]
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pub sc1a: SC1,
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#[doc = "0x04 - ADC Status and Control Register 1"]
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pub sc1b: SC1,
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#[doc = "0x08 - ADC Status and Control Register 1"]
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pub sc1c: SC1,
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#[doc = "0x0c - ADC Status and Control Register 1"]
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pub sc1d: SC1,
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#[doc = "0x10 - ADC Status and Control Register 1"]
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pub sc1e: SC1,
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#[doc = "0x14 - ADC Status and Control Register 1"]
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pub sc1f: SC1,
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#[doc = "0x18 - ADC Status and Control Register 1"]
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pub sc1g: SC1,
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#[doc = "0x1c - ADC Status and Control Register 1"]
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pub sc1h: SC1,
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#[doc = "0x20 - ADC Status and Control Register 1"]
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pub sc1i: SC1,
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#[doc = "0x24 - ADC Status and Control Register 1"]
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pub sc1j: SC1,
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#[doc = "0x28 - ADC Status and Control Register 1"]
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pub sc1k: SC1,
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#[doc = "0x2c - ADC Status and Control Register 1"]
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pub sc1l: SC1,
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#[doc = "0x30 - ADC Status and Control Register 1"]
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pub sc1m: SC1,
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#[doc = "0x34 - ADC Status and Control Register 1"]
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pub sc1n: SC1,
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#[doc = "0x38 - ADC Status and Control Register 1"]
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pub sc1o: SC1,
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#[doc = "0x3c - ADC Status and Control Register 1"]
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pub sc1p: SC1,
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#[doc = "0x40 - ADC Configuration Register 1"]
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pub cfg1: CFG1,
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#[doc = "0x44 - ADC Configuration Register 2"]
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pub cfg2: CFG2,
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#[doc = "0x48 - ADC Data Result Registers"]
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pub ra: R,
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#[doc = "0x4c - ADC Data Result Registers"]
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pub rb: R,
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#[doc = "0x50 - ADC Data Result Registers"]
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pub rc: R,
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#[doc = "0x54 - ADC Data Result Registers"]
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pub rd: R,
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#[doc = "0x58 - ADC Data Result Registers"]
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pub re: R,
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#[doc = "0x5c - ADC Data Result Registers"]
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pub rf: R,
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#[doc = "0x60 - ADC Data Result Registers"]
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pub rg: R,
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#[doc = "0x64 - ADC Data Result Registers"]
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pub rh: R,
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#[doc = "0x68 - ADC Data Result Registers"]
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pub ri: R,
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#[doc = "0x6c - ADC Data Result Registers"]
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pub rj: R,
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#[doc = "0x70 - ADC Data Result Registers"]
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pub rk: R,
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#[doc = "0x74 - ADC Data Result Registers"]
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pub rl: R,
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#[doc = "0x78 - ADC Data Result Registers"]
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pub rm: R,
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#[doc = "0x7c - ADC Data Result Registers"]
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pub rn: R,
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#[doc = "0x80 - ADC Data Result Registers"]
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pub ro: R,
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#[doc = "0x84 - ADC Data Result Registers"]
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pub rp: R,
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#[doc = "0x88 - Compare Value Registers"]
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pub cv1: CV,
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#[doc = "0x8c - Compare Value Registers"]
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pub cv2: CV,
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#[doc = "0x90 - Status and Control Register 2"]
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pub sc2: SC2,
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#[doc = "0x94 - Status and Control Register 3"]
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pub sc3: SC3,
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#[doc = "0x98 - BASE Offset Register"]
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pub base_ofs: BASE_OFS,
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#[doc = "0x9c - ADC Offset Correction Register"]
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pub ofs: OFS,
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#[doc = "0xa0 - USER Offset Correction Register"]
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pub usr_ofs: USR_OFS,
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#[doc = "0xa4 - ADC X Offset Correction Register"]
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pub xofs: XOFS,
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#[doc = "0xa8 - ADC Y Offset Correction Register"]
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pub yofs: YOFS,
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#[doc = "0xac - ADC Gain Register"]
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pub g: G,
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#[doc = "0xb0 - ADC User Gain Register"]
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pub ug: UG,
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#[doc = "0xb4 - ADC General Calibration Value Register S"]
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pub clps: CLPS,
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#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
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pub clp3: CLP3,
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#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
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pub clp2: CLP2,
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#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
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pub clp1: CLP1,
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#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
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pub clp0: CLP0,
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#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
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pub clpx: CLPX,
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#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
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pub clp9: CLP9,
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#[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
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pub clps_ofs: CLPS_OFS,
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#[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
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pub clp3_ofs: CLP3_OFS,
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#[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
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pub clp2_ofs: CLP2_OFS,
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#[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
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pub clp1_ofs: CLP1_OFS,
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#[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
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pub clp0_ofs: CLP0_OFS,
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#[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
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pub clpx_ofs: CLPX_OFS,
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#[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
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pub clp9_ofs: CLP9_OFS,
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}
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#[doc = "ADC Status and Control Register 1"]
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pub struct SC1 {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC Status and Control Register 1"]
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pub mod sc1;
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#[doc = "ADC Configuration Register 1"]
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pub struct CFG1 {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC Configuration Register 1"]
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pub mod cfg1;
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#[doc = "ADC Configuration Register 2"]
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pub struct CFG2 {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC Configuration Register 2"]
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pub mod cfg2;
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#[doc = "ADC Data Result Registers"]
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pub struct R {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC Data Result Registers"]
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pub mod r;
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#[doc = "Compare Value Registers"]
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pub struct CV {
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register: VolatileCell<u32>,
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}
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#[doc = "Compare Value Registers"]
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pub mod cv;
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#[doc = "Status and Control Register 2"]
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pub struct SC2 {
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register: VolatileCell<u32>,
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}
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#[doc = "Status and Control Register 2"]
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pub mod sc2;
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#[doc = "Status and Control Register 3"]
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pub struct SC3 {
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register: VolatileCell<u32>,
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}
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#[doc = "Status and Control Register 3"]
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pub mod sc3;
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#[doc = "BASE Offset Register"]
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pub struct BASE_OFS {
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register: VolatileCell<u32>,
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}
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#[doc = "BASE Offset Register"]
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pub mod base_ofs;
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#[doc = "ADC Offset Correction Register"]
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pub struct OFS {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC Offset Correction Register"]
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pub mod ofs;
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#[doc = "USER Offset Correction Register"]
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pub struct USR_OFS {
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register: VolatileCell<u32>,
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}
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#[doc = "USER Offset Correction Register"]
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pub mod usr_ofs;
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#[doc = "ADC X Offset Correction Register"]
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pub struct XOFS {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC X Offset Correction Register"]
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pub mod xofs;
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#[doc = "ADC Y Offset Correction Register"]
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pub struct YOFS {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC Y Offset Correction Register"]
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pub mod yofs;
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#[doc = "ADC Gain Register"]
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pub struct G {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC Gain Register"]
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pub mod g;
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#[doc = "ADC User Gain Register"]
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pub struct UG {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC User Gain Register"]
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pub mod ug;
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#[doc = "ADC General Calibration Value Register S"]
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pub struct CLPS {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC General Calibration Value Register S"]
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pub mod clps;
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#[doc = "ADC Plus-Side General Calibration Value Register 3"]
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pub struct CLP3 {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 3"]
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pub mod clp3;
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#[doc = "ADC Plus-Side General Calibration Value Register 2"]
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pub struct CLP2 {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 2"]
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pub mod clp2;
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#[doc = "ADC Plus-Side General Calibration Value Register 1"]
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pub struct CLP1 {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 1"]
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pub mod clp1;
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#[doc = "ADC Plus-Side General Calibration Value Register 0"]
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pub struct CLP0 {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 0"]
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pub mod clp0;
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#[doc = "ADC Plus-Side General Calibration Value Register X"]
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pub struct CLPX {
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register: VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register X"]
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pub mod clpx;
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#[doc = "ADC Plus-Side General Calibration Value Register 9"]
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pub struct CLP9 {
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register: VolatileCell<u32>,
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}
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||||
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
|
||||
pub mod clp9;
|
||||
#[doc = "ADC General Calibration Offset Value Register S"]
|
||||
pub struct CLPS_OFS {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC General Calibration Offset Value Register S"]
|
||||
pub mod clps_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub struct CLP3_OFS {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub mod clp3_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub struct CLP2_OFS {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub mod clp2_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub struct CLP1_OFS {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub mod clp1_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub struct CLP0_OFS {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub mod clp0_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub struct CLPX_OFS {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub mod clpx_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub struct CLP9_OFS {
|
||||
register: VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub mod clp9_ofs;
|
||||
@ -22,9 +22,7 @@ impl super::OFS {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -6,9 +6,7 @@ impl super::R {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
@ -22,9 +22,7 @@ impl super::SC1 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -93,9 +91,9 @@ pub enum ADCHR {
|
||||
_11011,
|
||||
#[doc = "Internal channel 3 is selected as input."]
|
||||
_11100,
|
||||
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
|
||||
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
|
||||
_11101,
|
||||
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
|
||||
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
|
||||
_11110,
|
||||
#[doc = "Module is disabled"]
|
||||
_11111,
|
||||
@ -452,9 +450,9 @@ pub enum ADCHW {
|
||||
_11011,
|
||||
#[doc = "Internal channel 3 is selected as input."]
|
||||
_11100,
|
||||
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
|
||||
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
|
||||
_11101,
|
||||
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
|
||||
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
|
||||
_11110,
|
||||
#[doc = "Module is disabled"]
|
||||
_11111,
|
||||
@ -625,12 +623,12 @@ impl<'a> _ADCHW<'a> {
|
||||
pub fn _11100(self) -> &'a mut W {
|
||||
self.variant(ADCHW::_11100)
|
||||
}
|
||||
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
|
||||
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
|
||||
#[inline]
|
||||
pub fn _11101(self) -> &'a mut W {
|
||||
self.variant(ADCHW::_11101)
|
||||
}
|
||||
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]."]
|
||||
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
|
||||
#[inline]
|
||||
pub fn _11110(self) -> &'a mut W {
|
||||
self.variant(ADCHW::_11110)
|
||||
@ -22,9 +22,7 @@ impl super::SC2 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -88,7 +86,7 @@ impl REFSELR {
|
||||
pub enum DMAENR {
|
||||
#[doc = "DMA is disabled."]
|
||||
_0,
|
||||
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
|
||||
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n\\[COCO\\] flag is asserted."]
|
||||
_1,
|
||||
}
|
||||
impl DMAENR {
|
||||
@ -458,7 +456,7 @@ impl<'a> _REFSELW<'a> {
|
||||
pub enum DMAENW {
|
||||
#[doc = "DMA is disabled."]
|
||||
_0,
|
||||
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
|
||||
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n\\[COCO\\] flag is asserted."]
|
||||
_1,
|
||||
}
|
||||
impl DMAENW {
|
||||
@ -489,7 +487,7 @@ impl<'a> _DMAENW<'a> {
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(DMAENW::_0)
|
||||
}
|
||||
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n[COCO] flag is asserted."]
|
||||
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n\\[COCO\\] flag is asserted."]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(DMAENW::_1)
|
||||
@ -22,9 +22,7 @@ impl super::SC3 {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -22,9 +22,7 @@ impl super::UG {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -22,9 +22,7 @@ impl super::USR_OFS {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -22,9 +22,7 @@ impl super::XOFS {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
@ -22,9 +22,7 @@ impl super::YOFS {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
}
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
Reference in New Issue
Block a user