xobs/s32k118.rs
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Ran with svd2rust 0.12.0

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This commit is contained in:
Kjetil Kjeka
2018-02-06 15:15:10 +01:00
parent 60604bcb5d
commit dd21201e79
801 changed files with 38573 additions and 19346 deletions
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162
src/sim/adcopt/mod.rs
View File

@ -45,8 +45,10 @@ impl super::ADCOPT {
#[doc = "Possible values of the field `ADC0TRGSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC0TRGSELR {
#[doc = "PDB output"] _0,
#[doc = "TRGMUX output"] _1,
#[doc = "PDB output"]
_0,
#[doc = "TRGMUX output"]
_1,
}
impl ADC0TRGSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,14 +92,22 @@ impl ADC0TRGSELR {
#[doc = "Possible values of the field `ADC0SWPRETRG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC0SWPRETRGR {
#[doc = "Software pretrigger disabled"] _000,
#[doc = "Reserved (do not use)"] _001,
#[doc = "Reserved (do not use)"] _010,
#[doc = "Reserved (do not use)"] _011,
#[doc = "Software pretrigger 0"] _100,
#[doc = "Software pretrigger 1"] _101,
#[doc = "Software pretrigger 2"] _110,
#[doc = "Software pretrigger 3"] _111,
#[doc = "Software pretrigger disabled"]
_000,
#[doc = "Reserved (do not use)"]
_001,
#[doc = "Reserved (do not use)"]
_010,
#[doc = "Reserved (do not use)"]
_011,
#[doc = "Software pretrigger 0"]
_100,
#[doc = "Software pretrigger 1"]
_101,
#[doc = "Software pretrigger 2"]
_110,
#[doc = "Software pretrigger 3"]
_111,
}
impl ADC0SWPRETRGR {
#[doc = r" Value of the field as raw bits"]
@ -174,10 +184,14 @@ impl ADC0SWPRETRGR {
#[doc = "Possible values of the field `ADC0PRETRGSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC0PRETRGSELR {
#[doc = "PDB pretrigger (default)"] _00,
#[doc = "TRGMUX pretrigger"] _01,
#[doc = "Software pretrigger"] _10,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "PDB pretrigger (default)"]
_00,
#[doc = "TRGMUX pretrigger"]
_01,
#[doc = "Software pretrigger"]
_10,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl ADC0PRETRGSELR {
#[doc = r" Value of the field as raw bits"]
@ -220,8 +234,10 @@ impl ADC0PRETRGSELR {
#[doc = "Possible values of the field `ADC1TRGSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC1TRGSELR {
#[doc = "PDB output"] _0,
#[doc = "TRGMUX output"] _1,
#[doc = "PDB output"]
_0,
#[doc = "TRGMUX output"]
_1,
}
impl ADC1TRGSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -265,14 +281,22 @@ impl ADC1TRGSELR {
#[doc = "Possible values of the field `ADC1SWPRETRG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC1SWPRETRGR {
#[doc = "Software pretrigger disabled"] _000,
#[doc = "Reserved (do not use)"] _001,
#[doc = "Reserved (do not use)"] _010,
#[doc = "Reserved (do not use)"] _011,
#[doc = "Software pretrigger 0"] _100,
#[doc = "Software pretrigger 1"] _101,
#[doc = "Software pretrigger 2"] _110,
#[doc = "Software pretrigger 3"] _111,
#[doc = "Software pretrigger disabled"]
_000,
#[doc = "Reserved (do not use)"]
_001,
#[doc = "Reserved (do not use)"]
_010,
#[doc = "Reserved (do not use)"]
_011,
#[doc = "Software pretrigger 0"]
_100,
#[doc = "Software pretrigger 1"]
_101,
#[doc = "Software pretrigger 2"]
_110,
#[doc = "Software pretrigger 3"]
_111,
}
impl ADC1SWPRETRGR {
#[doc = r" Value of the field as raw bits"]
@ -349,10 +373,14 @@ impl ADC1SWPRETRGR {
#[doc = "Possible values of the field `ADC1PRETRGSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC1PRETRGSELR {
#[doc = "PDB pretrigger (default)"] _00,
#[doc = "TRGMUX pretrigger"] _01,
#[doc = "Software pretrigger"] _10,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "PDB pretrigger (default)"]
_00,
#[doc = "TRGMUX pretrigger"]
_01,
#[doc = "Software pretrigger"]
_10,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl ADC1PRETRGSELR {
#[doc = r" Value of the field as raw bits"]
@ -394,8 +422,10 @@ impl ADC1PRETRGSELR {
}
#[doc = "Values that can be written to the field `ADC0TRGSEL`"]
pub enum ADC0TRGSELW {
#[doc = "PDB output"] _0,
#[doc = "TRGMUX output"] _1,
#[doc = "PDB output"]
_0,
#[doc = "TRGMUX output"]
_1,
}
impl ADC0TRGSELW {
#[allow(missing_docs)]
@ -450,14 +480,22 @@ impl<'a> _ADC0TRGSELW<'a> {
}
#[doc = "Values that can be written to the field `ADC0SWPRETRG`"]
pub enum ADC0SWPRETRGW {
#[doc = "Software pretrigger disabled"] _000,
#[doc = "Reserved (do not use)"] _001,
#[doc = "Reserved (do not use)"] _010,
#[doc = "Reserved (do not use)"] _011,
#[doc = "Software pretrigger 0"] _100,
#[doc = "Software pretrigger 1"] _101,
#[doc = "Software pretrigger 2"] _110,
#[doc = "Software pretrigger 3"] _111,
#[doc = "Software pretrigger disabled"]
_000,
#[doc = "Reserved (do not use)"]
_001,
#[doc = "Reserved (do not use)"]
_010,
#[doc = "Reserved (do not use)"]
_011,
#[doc = "Software pretrigger 0"]
_100,
#[doc = "Software pretrigger 1"]
_101,
#[doc = "Software pretrigger 2"]
_110,
#[doc = "Software pretrigger 3"]
_111,
}
impl ADC0SWPRETRGW {
#[allow(missing_docs)]
@ -540,9 +578,12 @@ impl<'a> _ADC0SWPRETRGW<'a> {
}
#[doc = "Values that can be written to the field `ADC0PRETRGSEL`"]
pub enum ADC0PRETRGSELW {
#[doc = "PDB pretrigger (default)"] _00,
#[doc = "TRGMUX pretrigger"] _01,
#[doc = "Software pretrigger"] _10,
#[doc = "PDB pretrigger (default)"]
_00,
#[doc = "TRGMUX pretrigger"]
_01,
#[doc = "Software pretrigger"]
_10,
}
impl ADC0PRETRGSELW {
#[allow(missing_docs)]
@ -593,8 +634,10 @@ impl<'a> _ADC0PRETRGSELW<'a> {
}
#[doc = "Values that can be written to the field `ADC1TRGSEL`"]
pub enum ADC1TRGSELW {
#[doc = "PDB output"] _0,
#[doc = "TRGMUX output"] _1,
#[doc = "PDB output"]
_0,
#[doc = "TRGMUX output"]
_1,
}
impl ADC1TRGSELW {
#[allow(missing_docs)]
@ -649,14 +692,22 @@ impl<'a> _ADC1TRGSELW<'a> {
}
#[doc = "Values that can be written to the field `ADC1SWPRETRG`"]
pub enum ADC1SWPRETRGW {
#[doc = "Software pretrigger disabled"] _000,
#[doc = "Reserved (do not use)"] _001,
#[doc = "Reserved (do not use)"] _010,
#[doc = "Reserved (do not use)"] _011,
#[doc = "Software pretrigger 0"] _100,
#[doc = "Software pretrigger 1"] _101,
#[doc = "Software pretrigger 2"] _110,
#[doc = "Software pretrigger 3"] _111,
#[doc = "Software pretrigger disabled"]
_000,
#[doc = "Reserved (do not use)"]
_001,
#[doc = "Reserved (do not use)"]
_010,
#[doc = "Reserved (do not use)"]
_011,
#[doc = "Software pretrigger 0"]
_100,
#[doc = "Software pretrigger 1"]
_101,
#[doc = "Software pretrigger 2"]
_110,
#[doc = "Software pretrigger 3"]
_111,
}
impl ADC1SWPRETRGW {
#[allow(missing_docs)]
@ -739,9 +790,12 @@ impl<'a> _ADC1SWPRETRGW<'a> {
}
#[doc = "Values that can be written to the field `ADC1PRETRGSEL`"]
pub enum ADC1PRETRGSELW {
#[doc = "PDB pretrigger (default)"] _00,
#[doc = "TRGMUX pretrigger"] _01,
#[doc = "Software pretrigger"] _10,
#[doc = "PDB pretrigger (default)"]
_00,
#[doc = "TRGMUX pretrigger"]
_01,
#[doc = "Software pretrigger"]
_10,
}
impl ADC1PRETRGSELW {
#[allow(missing_docs)]

261
src/sim/chipctl/mod.rs
View File

@ -47,11 +47,16 @@ impl super::CHIPCTL {
pub enum ADC_INTERLEAVE_ENR {
#[doc = "Interleaving disabled. No channel pair interleaved. Interleaved channels are individually connected to pins. PTC0 is connected to ADC0_SE8. PTC1 is connected to ADC0_SE9. PTB15 is connected to ADC1_SE14. PTB16 is connected to ADC1_SE15. PTB0 is connected to ADC0_SE4. PTB1 is connected to ADC0_SE5. PTB13 is connected to ADC1_SE8. PTB14 is connected to ADC1_SE9."]
_0000,
#[doc = "PTB14 to ADC1_SE9 and ADC0_SE9"] _1XXX,
#[doc = "PTB13 to ADC1_SE8 and ADC0_SE8"] X1XX,
#[doc = "PTB1 to ADC0_SE5 and ADC1_SE15"] XX1X,
#[doc = "PTB0 to ADC0_SE4 and ADC1_SE14"] XXX1,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "PTB14 to ADC1_SE9 and ADC0_SE9"]
_1XXX,
#[doc = "PTB13 to ADC1_SE8 and ADC0_SE8"]
X1XX,
#[doc = "PTB1 to ADC0_SE5 and ADC1_SE15"]
XX1X,
#[doc = "PTB0 to ADC0_SE4 and ADC1_SE14"]
XXX1,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl ADC_INTERLEAVE_ENR {
#[doc = r" Value of the field as raw bits"]
@ -108,22 +113,36 @@ impl ADC_INTERLEAVE_ENR {
#[doc = "Possible values of the field `CLKOUTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLKOUTSELR {
#[doc = "SCG CLKOUT"] _0000,
#[doc = "SOSC DIV2 CLK"] _0010,
#[doc = "SIRC DIV2 CLK"] _0100,
#[doc = "SCG CLKOUT"]
_0000,
#[doc = "SOSC DIV2 CLK"]
_0010,
#[doc = "SIRC DIV2 CLK"]
_0100,
#[doc = "For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved"]
_0101,
#[doc = "FIRC DIV2 CLK"] _0110,
#[doc = "HCLK"] _0111,
#[doc = "SPLL DIV2 CLK"] _1000,
#[doc = "BUS_CLK"] _1001,
#[doc = "LPO128K_CLK"] _1010,
#[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"] _1011,
#[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"] _1100,
#[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"] _1101,
#[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"] _1110,
#[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"] _1111,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "FIRC DIV2 CLK"]
_0110,
#[doc = "HCLK"]
_0111,
#[doc = "SPLL DIV2 CLK"]
_1000,
#[doc = "BUS_CLK"]
_1001,
#[doc = "LPO128K_CLK"]
_1010,
#[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"]
_1011,
#[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"]
_1100,
#[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"]
_1101,
#[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"]
_1110,
#[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"]
_1111,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl CLKOUTSELR {
#[doc = r" Value of the field as raw bits"]
@ -243,14 +262,22 @@ impl CLKOUTSELR {
#[doc = "Possible values of the field `CLKOUTDIV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLKOUTDIVR {
#[doc = "Divide by 1"] _000,
#[doc = "Divide by 2"] _001,
#[doc = "Divide by 3"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 5"] _100,
#[doc = "Divide by 6"] _101,
#[doc = "Divide by 7"] _110,
#[doc = "Divide by 8"] _111,
#[doc = "Divide by 1"]
_000,
#[doc = "Divide by 2"]
_001,
#[doc = "Divide by 3"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 5"]
_100,
#[doc = "Divide by 6"]
_101,
#[doc = "Divide by 7"]
_110,
#[doc = "Divide by 8"]
_111,
}
impl CLKOUTDIVR {
#[doc = r" Value of the field as raw bits"]
@ -327,8 +354,10 @@ impl CLKOUTDIVR {
#[doc = "Possible values of the field `CLKOUTEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLKOUTENR {
#[doc = "Clockout disable"] _0,
#[doc = "Clockout enable"] _1,
#[doc = "Clockout disable"]
_0,
#[doc = "Clockout enable"]
_1,
}
impl CLKOUTENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -372,8 +401,10 @@ impl CLKOUTENR {
#[doc = "Possible values of the field `TRACECLK_SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRACECLK_SELR {
#[doc = "Core clock"] _0,
#[doc = "Platform clock"] _1,
#[doc = "Core clock"]
_0,
#[doc = "Platform clock"]
_1,
}
impl TRACECLK_SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -419,7 +450,8 @@ impl TRACECLK_SELR {
pub enum PDB_BB_SELR {
#[doc = "PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0]"]
_0,
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."] _1,
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."]
_1,
}
impl PDB_BB_SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -463,13 +495,20 @@ impl PDB_BB_SELR {
#[doc = "Possible values of the field `ADC_SUPPLY`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC_SUPPLYR {
#[doc = "5 V input VDD supply (VDD)"] _000,
#[doc = "5 V input analog supply (VDDA)"] _001,
#[doc = "ADC Reference Supply (VREFH)"] _010,
#[doc = "3.3 V Oscillator Regulator Output (VDD_3V)"] _011,
#[doc = "3.3 V flash regulator output (VDD_flash_3V)"] _100,
#[doc = "1.2 V core regulator output (VDD_LV)"] _101,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "5 V input VDD supply (VDD)"]
_000,
#[doc = "5 V input analog supply (VDDA)"]
_001,
#[doc = "ADC Reference Supply (VREFH)"]
_010,
#[doc = "3.3 V Oscillator Regulator Output (VDD_3V)"]
_011,
#[doc = "3.3 V flash regulator output (VDD_flash_3V)"]
_100,
#[doc = "1.2 V core regulator output (VDD_LV)"]
_101,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl ADC_SUPPLYR {
#[doc = r" Value of the field as raw bits"]
@ -533,8 +572,10 @@ impl ADC_SUPPLYR {
#[doc = "Possible values of the field `ADC_SUPPLYEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADC_SUPPLYENR {
#[doc = "Disable internal supply monitoring"] _0,
#[doc = "Enable internal supply monitoring"] _1,
#[doc = "Disable internal supply monitoring"]
_0,
#[doc = "Enable internal supply monitoring"]
_1,
}
impl ADC_SUPPLYENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -578,8 +619,10 @@ impl ADC_SUPPLYENR {
#[doc = "Possible values of the field `SRAMU_RETEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SRAMU_RETENR {
#[doc = "SRAMU contents are retained across resets"] _0,
#[doc = "No SRAMU retention"] _1,
#[doc = "SRAMU contents are retained across resets"]
_0,
#[doc = "No SRAMU retention"]
_1,
}
impl SRAMU_RETENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -623,8 +666,10 @@ impl SRAMU_RETENR {
#[doc = "Possible values of the field `SRAML_RETEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SRAML_RETENR {
#[doc = "SRAML contents are retained across resets"] _0,
#[doc = "No SRAML retention"] _1,
#[doc = "SRAML contents are retained across resets"]
_0,
#[doc = "No SRAML retention"]
_1,
}
impl SRAML_RETENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -669,10 +714,14 @@ impl SRAML_RETENR {
pub enum ADC_INTERLEAVE_ENW {
#[doc = "Interleaving disabled. No channel pair interleaved. Interleaved channels are individually connected to pins. PTC0 is connected to ADC0_SE8. PTC1 is connected to ADC0_SE9. PTB15 is connected to ADC1_SE14. PTB16 is connected to ADC1_SE15. PTB0 is connected to ADC0_SE4. PTB1 is connected to ADC0_SE5. PTB13 is connected to ADC1_SE8. PTB14 is connected to ADC1_SE9."]
_0000,
#[doc = "PTB14 to ADC1_SE9 and ADC0_SE9"] _1XXX,
#[doc = "PTB13 to ADC1_SE8 and ADC0_SE8"] X1XX,
#[doc = "PTB1 to ADC0_SE5 and ADC1_SE15"] XX1X,
#[doc = "PTB0 to ADC0_SE4 and ADC1_SE14"] XXX1,
#[doc = "PTB14 to ADC1_SE9 and ADC0_SE9"]
_1XXX,
#[doc = "PTB13 to ADC1_SE8 and ADC0_SE8"]
X1XX,
#[doc = "PTB1 to ADC0_SE5 and ADC1_SE15"]
XX1X,
#[doc = "PTB0 to ADC0_SE4 and ADC1_SE14"]
XXX1,
}
impl ADC_INTERLEAVE_ENW {
#[allow(missing_docs)]
@ -735,21 +784,34 @@ impl<'a> _ADC_INTERLEAVE_ENW<'a> {
}
#[doc = "Values that can be written to the field `CLKOUTSEL`"]
pub enum CLKOUTSELW {
#[doc = "SCG CLKOUT"] _0000,
#[doc = "SOSC DIV2 CLK"] _0010,
#[doc = "SIRC DIV2 CLK"] _0100,
#[doc = "SCG CLKOUT"]
_0000,
#[doc = "SOSC DIV2 CLK"]
_0010,
#[doc = "SIRC DIV2 CLK"]
_0100,
#[doc = "For S32K148: QSPI SFIF_CLK_HYP: Divide by 2 clock (configured through SCLKCONFIG[5]) for HyperRAM going to sfif clock to QSPI; For others: Reserved"]
_0101,
#[doc = "FIRC DIV2 CLK"] _0110,
#[doc = "HCLK"] _0111,
#[doc = "SPLL DIV2 CLK"] _1000,
#[doc = "BUS_CLK"] _1001,
#[doc = "LPO128K_CLK"] _1010,
#[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"] _1011,
#[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"] _1100,
#[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"] _1101,
#[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"] _1110,
#[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"] _1111,
#[doc = "FIRC DIV2 CLK"]
_0110,
#[doc = "HCLK"]
_0111,
#[doc = "SPLL DIV2 CLK"]
_1000,
#[doc = "BUS_CLK"]
_1001,
#[doc = "LPO128K_CLK"]
_1010,
#[doc = "For S32K148: QSPI IPG_CLK; For others: Reserved"]
_1011,
#[doc = "LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL]"]
_1100,
#[doc = "For S32K148: QSPI IPG_CLK_SFIF; For others: Reserved"]
_1101,
#[doc = "RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL]"]
_1110,
#[doc = "For S32K148: QSPI IPG_CLK_2XSFIF; For others: Reserved"]
_1111,
}
impl CLKOUTSELW {
#[allow(missing_docs)]
@ -866,14 +928,22 @@ impl<'a> _CLKOUTSELW<'a> {
}
#[doc = "Values that can be written to the field `CLKOUTDIV`"]
pub enum CLKOUTDIVW {
#[doc = "Divide by 1"] _000,
#[doc = "Divide by 2"] _001,
#[doc = "Divide by 3"] _010,
#[doc = "Divide by 4"] _011,
#[doc = "Divide by 5"] _100,
#[doc = "Divide by 6"] _101,
#[doc = "Divide by 7"] _110,
#[doc = "Divide by 8"] _111,
#[doc = "Divide by 1"]
_000,
#[doc = "Divide by 2"]
_001,
#[doc = "Divide by 3"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 5"]
_100,
#[doc = "Divide by 6"]
_101,
#[doc = "Divide by 7"]
_110,
#[doc = "Divide by 8"]
_111,
}
impl CLKOUTDIVW {
#[allow(missing_docs)]
@ -956,8 +1026,10 @@ impl<'a> _CLKOUTDIVW<'a> {
}
#[doc = "Values that can be written to the field `CLKOUTEN`"]
pub enum CLKOUTENW {
#[doc = "Clockout disable"] _0,
#[doc = "Clockout enable"] _1,
#[doc = "Clockout disable"]
_0,
#[doc = "Clockout enable"]
_1,
}
impl CLKOUTENW {
#[allow(missing_docs)]
@ -1012,8 +1084,10 @@ impl<'a> _CLKOUTENW<'a> {
}
#[doc = "Values that can be written to the field `TRACECLK_SEL`"]
pub enum TRACECLK_SELW {
#[doc = "Core clock"] _0,
#[doc = "Platform clock"] _1,
#[doc = "Core clock"]
_0,
#[doc = "Platform clock"]
_1,
}
impl TRACECLK_SELW {
#[allow(missing_docs)]
@ -1070,7 +1144,8 @@ impl<'a> _TRACECLK_SELW<'a> {
pub enum PDB_BB_SELW {
#[doc = "PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0] and PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0]"]
_0,
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."] _1,
#[doc = "Channel 0 of PDB0 and PDB1 back-to-back operation with COCO[7:0] of ADC0 and ADC1."]
_1,
}
impl PDB_BB_SELW {
#[allow(missing_docs)]
@ -1125,12 +1200,18 @@ impl<'a> _PDB_BB_SELW<'a> {
}
#[doc = "Values that can be written to the field `ADC_SUPPLY`"]
pub enum ADC_SUPPLYW {
#[doc = "5 V input VDD supply (VDD)"] _000,
#[doc = "5 V input analog supply (VDDA)"] _001,
#[doc = "ADC Reference Supply (VREFH)"] _010,
#[doc = "3.3 V Oscillator Regulator Output (VDD_3V)"] _011,
#[doc = "3.3 V flash regulator output (VDD_flash_3V)"] _100,
#[doc = "1.2 V core regulator output (VDD_LV)"] _101,
#[doc = "5 V input VDD supply (VDD)"]
_000,
#[doc = "5 V input analog supply (VDDA)"]
_001,
#[doc = "ADC Reference Supply (VREFH)"]
_010,
#[doc = "3.3 V Oscillator Regulator Output (VDD_3V)"]
_011,
#[doc = "3.3 V flash regulator output (VDD_flash_3V)"]
_100,
#[doc = "1.2 V core regulator output (VDD_LV)"]
_101,
}
impl ADC_SUPPLYW {
#[allow(missing_docs)]
@ -1199,8 +1280,10 @@ impl<'a> _ADC_SUPPLYW<'a> {
}
#[doc = "Values that can be written to the field `ADC_SUPPLYEN`"]
pub enum ADC_SUPPLYENW {
#[doc = "Disable internal supply monitoring"] _0,
#[doc = "Enable internal supply monitoring"] _1,
#[doc = "Disable internal supply monitoring"]
_0,
#[doc = "Enable internal supply monitoring"]
_1,
}
impl ADC_SUPPLYENW {
#[allow(missing_docs)]
@ -1255,8 +1338,10 @@ impl<'a> _ADC_SUPPLYENW<'a> {
}
#[doc = "Values that can be written to the field `SRAMU_RETEN`"]
pub enum SRAMU_RETENW {
#[doc = "SRAMU contents are retained across resets"] _0,
#[doc = "No SRAMU retention"] _1,
#[doc = "SRAMU contents are retained across resets"]
_0,
#[doc = "No SRAMU retention"]
_1,
}
impl SRAMU_RETENW {
#[allow(missing_docs)]
@ -1311,8 +1396,10 @@ impl<'a> _SRAMU_RETENW<'a> {
}
#[doc = "Values that can be written to the field `SRAML_RETEN`"]
pub enum SRAML_RETENW {
#[doc = "SRAML contents are retained across resets"] _0,
#[doc = "No SRAML retention"] _1,
#[doc = "SRAML contents are retained across resets"]
_0,
#[doc = "No SRAML retention"]
_1,
}
impl SRAML_RETENW {
#[allow(missing_docs)]

12
src/sim/clkdiv4/mod.rs
View File

@ -77,8 +77,10 @@ impl TRACEDIVR {
#[doc = "Possible values of the field `TRACEDIVEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRACEDIVENR {
#[doc = "Debug trace divider disabled"] _0,
#[doc = "Debug trace divider enabled"] _1,
#[doc = "Debug trace divider disabled"]
_0,
#[doc = "Debug trace divider enabled"]
_1,
}
impl TRACEDIVENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -159,8 +161,10 @@ impl<'a> _TRACEDIVW<'a> {
}
#[doc = "Values that can be written to the field `TRACEDIVEN`"]
pub enum TRACEDIVENW {
#[doc = "Debug trace divider disabled"] _0,
#[doc = "Debug trace divider enabled"] _1,
#[doc = "Debug trace divider disabled"]
_0,
#[doc = "Debug trace divider enabled"]
_1,
}
impl TRACEDIVENW {
#[allow(missing_docs)]

30
src/sim/fcfg1/mod.rs
View File

@ -56,16 +56,26 @@ impl DEPARTR {
#[doc = "Possible values of the field `EEERAMSIZE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EEERAMSIZER {
#[doc = "4 KB"] _0010,
#[doc = "2 KB"] _0011,
#[doc = "1 KB"] _0100,
#[doc = "512 Bytes"] _0101,
#[doc = "256 Bytes"] _0110,
#[doc = "128 Bytes"] _0111,
#[doc = "64 Bytes"] _1000,
#[doc = "32 Bytes"] _1001,
#[doc = "0 Bytes"] _1111,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "4 KB"]
_0010,
#[doc = "2 KB"]
_0011,
#[doc = "1 KB"]
_0100,
#[doc = "512 Bytes"]
_0101,
#[doc = "256 Bytes"]
_0110,
#[doc = "128 Bytes"]
_0111,
#[doc = "64 Bytes"]
_1000,
#[doc = "32 Bytes"]
_1001,
#[doc = "0 Bytes"]
_1111,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl EEERAMSIZER {
#[doc = r" Value of the field as raw bits"]

156
src/sim/ftmopt0/mod.rs
View File

@ -45,9 +45,12 @@ impl super::FTMOPT0 {
#[doc = "Possible values of the field `FTM0FLTxSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM0FLTXSELR {
#[doc = "FTM0_FLTx pin"] _000,
#[doc = "TRGMUX_FTM0 out"] _001,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "FTM0_FLTx pin"]
_000,
#[doc = "TRGMUX_FTM0 out"]
_001,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl FTM0FLTXSELR {
#[doc = r" Value of the field as raw bits"]
@ -83,9 +86,12 @@ impl FTM0FLTXSELR {
#[doc = "Possible values of the field `FTM1FLTxSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM1FLTXSELR {
#[doc = "FTM1_FLTx pin"] _000,
#[doc = "TRGMUX_FTM1 out"] _001,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "FTM1_FLTx pin"]
_000,
#[doc = "TRGMUX_FTM1 out"]
_001,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl FTM1FLTXSELR {
#[doc = r" Value of the field as raw bits"]
@ -121,9 +127,12 @@ impl FTM1FLTXSELR {
#[doc = "Possible values of the field `FTM2FLTxSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM2FLTXSELR {
#[doc = "FTM2_FLTx pin"] _000,
#[doc = "TRGMUX_FTM2 out"] _001,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "FTM2_FLTx pin"]
_000,
#[doc = "TRGMUX_FTM2 out"]
_001,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl FTM2FLTXSELR {
#[doc = r" Value of the field as raw bits"]
@ -159,9 +168,12 @@ impl FTM2FLTXSELR {
#[doc = "Possible values of the field `FTM3FLTxSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM3FLTXSELR {
#[doc = "FTM3_FLTx pin"] _000,
#[doc = "TRGMUX_FTM3 out"] _001,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "FTM3_FLTx pin"]
_000,
#[doc = "TRGMUX_FTM3 out"]
_001,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl FTM3FLTXSELR {
#[doc = r" Value of the field as raw bits"]
@ -197,10 +209,14 @@ impl FTM3FLTXSELR {
#[doc = "Possible values of the field `FTM0CLKSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM0CLKSELR {
#[doc = "FTM0 external clock driven by TCLK0 pin."] _00,
#[doc = "FTM0 external clock driven by TCLK1 pin."] _01,
#[doc = "FTM0 external clock driven by TCLK2 pin."] _10,
#[doc = "No clock input"] _11,
#[doc = "FTM0 external clock driven by TCLK0 pin."]
_00,
#[doc = "FTM0 external clock driven by TCLK1 pin."]
_01,
#[doc = "FTM0 external clock driven by TCLK2 pin."]
_10,
#[doc = "No clock input"]
_11,
}
impl FTM0CLKSELR {
#[doc = r" Value of the field as raw bits"]
@ -249,10 +265,14 @@ impl FTM0CLKSELR {
#[doc = "Possible values of the field `FTM1CLKSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM1CLKSELR {
#[doc = "FTM1 external clock driven by TCLK0 pin."] _00,
#[doc = "FTM1 external clock driven by TCLK1 pin."] _01,
#[doc = "FTM1 external clock driven by TCLK2 pin."] _10,
#[doc = "No clock input"] _11,
#[doc = "FTM1 external clock driven by TCLK0 pin."]
_00,
#[doc = "FTM1 external clock driven by TCLK1 pin."]
_01,
#[doc = "FTM1 external clock driven by TCLK2 pin."]
_10,
#[doc = "No clock input"]
_11,
}
impl FTM1CLKSELR {
#[doc = r" Value of the field as raw bits"]
@ -301,10 +321,14 @@ impl FTM1CLKSELR {
#[doc = "Possible values of the field `FTM2CLKSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM2CLKSELR {
#[doc = "FTM2 external clock driven by TCLK0 pin."] _00,
#[doc = "FTM2 external clock driven by TCLK1 pin."] _01,
#[doc = "FTM2 external clock driven by TCLK2 pin."] _10,
#[doc = "No clock input"] _11,
#[doc = "FTM2 external clock driven by TCLK0 pin."]
_00,
#[doc = "FTM2 external clock driven by TCLK1 pin."]
_01,
#[doc = "FTM2 external clock driven by TCLK2 pin."]
_10,
#[doc = "No clock input"]
_11,
}
impl FTM2CLKSELR {
#[doc = r" Value of the field as raw bits"]
@ -353,10 +377,14 @@ impl FTM2CLKSELR {
#[doc = "Possible values of the field `FTM3CLKSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM3CLKSELR {
#[doc = "FTM3 external clock driven by TCLK0 pin."] _00,
#[doc = "FTM3 external clock driven by TCLK1 pin."] _01,
#[doc = "FTM3 external clock driven by TCLK2 pin."] _10,
#[doc = "No clock input"] _11,
#[doc = "FTM3 external clock driven by TCLK0 pin."]
_00,
#[doc = "FTM3 external clock driven by TCLK1 pin."]
_01,
#[doc = "FTM3 external clock driven by TCLK2 pin."]
_10,
#[doc = "No clock input"]
_11,
}
impl FTM3CLKSELR {
#[doc = r" Value of the field as raw bits"]
@ -404,8 +432,10 @@ impl FTM3CLKSELR {
}
#[doc = "Values that can be written to the field `FTM0FLTxSEL`"]
pub enum FTM0FLTXSELW {
#[doc = "FTM0_FLTx pin"] _000,
#[doc = "TRGMUX_FTM0 out"] _001,
#[doc = "FTM0_FLTx pin"]
_000,
#[doc = "TRGMUX_FTM0 out"]
_001,
}
impl FTM0FLTXSELW {
#[allow(missing_docs)]
@ -450,8 +480,10 @@ impl<'a> _FTM0FLTXSELW<'a> {
}
#[doc = "Values that can be written to the field `FTM1FLTxSEL`"]
pub enum FTM1FLTXSELW {
#[doc = "FTM1_FLTx pin"] _000,
#[doc = "TRGMUX_FTM1 out"] _001,
#[doc = "FTM1_FLTx pin"]
_000,
#[doc = "TRGMUX_FTM1 out"]
_001,
}
impl FTM1FLTXSELW {
#[allow(missing_docs)]
@ -496,8 +528,10 @@ impl<'a> _FTM1FLTXSELW<'a> {
}
#[doc = "Values that can be written to the field `FTM2FLTxSEL`"]
pub enum FTM2FLTXSELW {
#[doc = "FTM2_FLTx pin"] _000,
#[doc = "TRGMUX_FTM2 out"] _001,
#[doc = "FTM2_FLTx pin"]
_000,
#[doc = "TRGMUX_FTM2 out"]
_001,
}
impl FTM2FLTXSELW {
#[allow(missing_docs)]
@ -542,8 +576,10 @@ impl<'a> _FTM2FLTXSELW<'a> {
}
#[doc = "Values that can be written to the field `FTM3FLTxSEL`"]
pub enum FTM3FLTXSELW {
#[doc = "FTM3_FLTx pin"] _000,
#[doc = "TRGMUX_FTM3 out"] _001,
#[doc = "FTM3_FLTx pin"]
_000,
#[doc = "TRGMUX_FTM3 out"]
_001,
}
impl FTM3FLTXSELW {
#[allow(missing_docs)]
@ -588,10 +624,14 @@ impl<'a> _FTM3FLTXSELW<'a> {
}
#[doc = "Values that can be written to the field `FTM0CLKSEL`"]
pub enum FTM0CLKSELW {
#[doc = "FTM0 external clock driven by TCLK0 pin."] _00,
#[doc = "FTM0 external clock driven by TCLK1 pin."] _01,
#[doc = "FTM0 external clock driven by TCLK2 pin."] _10,
#[doc = "No clock input"] _11,
#[doc = "FTM0 external clock driven by TCLK0 pin."]
_00,
#[doc = "FTM0 external clock driven by TCLK1 pin."]
_01,
#[doc = "FTM0 external clock driven by TCLK2 pin."]
_10,
#[doc = "No clock input"]
_11,
}
impl FTM0CLKSELW {
#[allow(missing_docs)]
@ -650,10 +690,14 @@ impl<'a> _FTM0CLKSELW<'a> {
}
#[doc = "Values that can be written to the field `FTM1CLKSEL`"]
pub enum FTM1CLKSELW {
#[doc = "FTM1 external clock driven by TCLK0 pin."] _00,
#[doc = "FTM1 external clock driven by TCLK1 pin."] _01,
#[doc = "FTM1 external clock driven by TCLK2 pin."] _10,
#[doc = "No clock input"] _11,
#[doc = "FTM1 external clock driven by TCLK0 pin."]
_00,
#[doc = "FTM1 external clock driven by TCLK1 pin."]
_01,
#[doc = "FTM1 external clock driven by TCLK2 pin."]
_10,
#[doc = "No clock input"]
_11,
}
impl FTM1CLKSELW {
#[allow(missing_docs)]
@ -712,10 +756,14 @@ impl<'a> _FTM1CLKSELW<'a> {
}
#[doc = "Values that can be written to the field `FTM2CLKSEL`"]
pub enum FTM2CLKSELW {
#[doc = "FTM2 external clock driven by TCLK0 pin."] _00,
#[doc = "FTM2 external clock driven by TCLK1 pin."] _01,
#[doc = "FTM2 external clock driven by TCLK2 pin."] _10,
#[doc = "No clock input"] _11,
#[doc = "FTM2 external clock driven by TCLK0 pin."]
_00,
#[doc = "FTM2 external clock driven by TCLK1 pin."]
_01,
#[doc = "FTM2 external clock driven by TCLK2 pin."]
_10,
#[doc = "No clock input"]
_11,
}
impl FTM2CLKSELW {
#[allow(missing_docs)]
@ -774,10 +822,14 @@ impl<'a> _FTM2CLKSELW<'a> {
}
#[doc = "Values that can be written to the field `FTM3CLKSEL`"]
pub enum FTM3CLKSELW {
#[doc = "FTM3 external clock driven by TCLK0 pin."] _00,
#[doc = "FTM3 external clock driven by TCLK1 pin."] _01,
#[doc = "FTM3 external clock driven by TCLK2 pin."] _10,
#[doc = "No clock input"] _11,
#[doc = "FTM3 external clock driven by TCLK0 pin."]
_00,
#[doc = "FTM3 external clock driven by TCLK1 pin."]
_01,
#[doc = "FTM3 external clock driven by TCLK2 pin."]
_10,
#[doc = "No clock input"]
_11,
}
impl FTM3CLKSELW {
#[allow(missing_docs)]

84
src/sim/ftmopt1/mod.rs
View File

@ -129,9 +129,12 @@ impl FTM3SYNCBITR {
#[doc = "Possible values of the field `FTM1CH0SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM1CH0SELR {
#[doc = "FTM1_CH0 input"] _00,
#[doc = "CMP0 output"] _01,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "FTM1_CH0 input"]
_00,
#[doc = "CMP0 output"]
_01,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl FTM1CH0SELR {
#[doc = r" Value of the field as raw bits"]
@ -167,9 +170,12 @@ impl FTM1CH0SELR {
#[doc = "Possible values of the field `FTM2CH0SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM2CH0SELR {
#[doc = "FTM2_CH0 input"] _00,
#[doc = "CMP0 output"] _01,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "FTM2_CH0 input"]
_00,
#[doc = "CMP0 output"]
_01,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl FTM2CH0SELR {
#[doc = r" Value of the field as raw bits"]
@ -205,8 +211,10 @@ impl FTM2CH0SELR {
#[doc = "Possible values of the field `FTM2CH1SEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM2CH1SELR {
#[doc = "FTM2_CH1 input"] _0,
#[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"] _1,
#[doc = "FTM2_CH1 input"]
_0,
#[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"]
_1,
}
impl FTM2CH1SELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -250,8 +258,10 @@ impl FTM2CH1SELR {
#[doc = "Possible values of the field `FTMGLDOK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTMGLDOKR {
#[doc = "FTM Global load mechanism disabled."] _0,
#[doc = "FTM Global load mechanism enabled"] _1,
#[doc = "FTM Global load mechanism disabled."]
_0,
#[doc = "FTM Global load mechanism enabled"]
_1,
}
impl FTMGLDOKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -295,9 +305,12 @@ impl FTMGLDOKR {
#[doc = "Possible values of the field `FTM0_OUTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM0_OUTSELR {
#[doc = "No modulation with FTM1_CH1"] _00000000,
#[doc = "Modulation with FTM1_CH1"] _00000001,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "No modulation with FTM1_CH1"]
_00000000,
#[doc = "Modulation with FTM1_CH1"]
_00000001,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl FTM0_OUTSELR {
#[doc = r" Value of the field as raw bits"]
@ -333,9 +346,12 @@ impl FTM0_OUTSELR {
#[doc = "Possible values of the field `FTM3_OUTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FTM3_OUTSELR {
#[doc = "No modulation with FTM2_CH1"] _00000000,
#[doc = "Modulation with FTM2_CH1"] _00000001,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "No modulation with FTM2_CH1"]
_00000000,
#[doc = "Modulation with FTM2_CH1"]
_00000001,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl FTM3_OUTSELR {
#[doc = r" Value of the field as raw bits"]
@ -462,8 +478,10 @@ impl<'a> _FTM3SYNCBITW<'a> {
}
#[doc = "Values that can be written to the field `FTM1CH0SEL`"]
pub enum FTM1CH0SELW {
#[doc = "FTM1_CH0 input"] _00,
#[doc = "CMP0 output"] _01,
#[doc = "FTM1_CH0 input"]
_00,
#[doc = "CMP0 output"]
_01,
}
impl FTM1CH0SELW {
#[allow(missing_docs)]
@ -508,8 +526,10 @@ impl<'a> _FTM1CH0SELW<'a> {
}
#[doc = "Values that can be written to the field `FTM2CH0SEL`"]
pub enum FTM2CH0SELW {
#[doc = "FTM2_CH0 input"] _00,
#[doc = "CMP0 output"] _01,
#[doc = "FTM2_CH0 input"]
_00,
#[doc = "CMP0 output"]
_01,
}
impl FTM2CH0SELW {
#[allow(missing_docs)]
@ -554,8 +574,10 @@ impl<'a> _FTM2CH0SELW<'a> {
}
#[doc = "Values that can be written to the field `FTM2CH1SEL`"]
pub enum FTM2CH1SELW {
#[doc = "FTM2_CH1 input"] _0,
#[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"] _1,
#[doc = "FTM2_CH1 input"]
_0,
#[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"]
_1,
}
impl FTM2CH1SELW {
#[allow(missing_docs)]
@ -610,8 +632,10 @@ impl<'a> _FTM2CH1SELW<'a> {
}
#[doc = "Values that can be written to the field `FTMGLDOK`"]
pub enum FTMGLDOKW {
#[doc = "FTM Global load mechanism disabled."] _0,
#[doc = "FTM Global load mechanism enabled"] _1,
#[doc = "FTM Global load mechanism disabled."]
_0,
#[doc = "FTM Global load mechanism enabled"]
_1,
}
impl FTMGLDOKW {
#[allow(missing_docs)]
@ -666,8 +690,10 @@ impl<'a> _FTMGLDOKW<'a> {
}
#[doc = "Values that can be written to the field `FTM0_OUTSEL`"]
pub enum FTM0_OUTSELW {
#[doc = "No modulation with FTM1_CH1"] _00000000,
#[doc = "Modulation with FTM1_CH1"] _00000001,
#[doc = "No modulation with FTM1_CH1"]
_00000000,
#[doc = "Modulation with FTM1_CH1"]
_00000001,
}
impl FTM0_OUTSELW {
#[allow(missing_docs)]
@ -712,8 +738,10 @@ impl<'a> _FTM0_OUTSELW<'a> {
}
#[doc = "Values that can be written to the field `FTM3_OUTSEL`"]
pub enum FTM3_OUTSELW {
#[doc = "No modulation with FTM2_CH1"] _00000000,
#[doc = "Modulation with FTM2_CH1"] _00000001,
#[doc = "No modulation with FTM2_CH1"]
_00000000,
#[doc = "Modulation with FTM2_CH1"]
_00000001,
}
impl FTM3_OUTSELW {
#[allow(missing_docs)]

72
src/sim/lpoclks/mod.rs
View File

@ -45,8 +45,10 @@ impl super::LPOCLKS {
#[doc = "Possible values of the field `LPO1KCLKEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPO1KCLKENR {
#[doc = "Disable 1 kHz LPO_CLK output"] _0,
#[doc = "Enable 1 kHz LPO_CLK output"] _1,
#[doc = "Disable 1 kHz LPO_CLK output"]
_0,
#[doc = "Enable 1 kHz LPO_CLK output"]
_1,
}
impl LPO1KCLKENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,8 +92,10 @@ impl LPO1KCLKENR {
#[doc = "Possible values of the field `LPO32KCLKEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPO32KCLKENR {
#[doc = "Disable 32 kHz LPO_CLK output"] _0,
#[doc = "Enable 32 kHz LPO_CLK output"] _1,
#[doc = "Disable 32 kHz LPO_CLK output"]
_0,
#[doc = "Enable 32 kHz LPO_CLK output"]
_1,
}
impl LPO32KCLKENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -135,10 +139,14 @@ impl LPO32KCLKENR {
#[doc = "Possible values of the field `LPOCLKSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LPOCLKSELR {
#[doc = "128 kHz LPO_CLK"] _00,
#[doc = "No clock"] _01,
#[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] _10,
#[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] _11,
#[doc = "128 kHz LPO_CLK"]
_00,
#[doc = "No clock"]
_01,
#[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
_10,
#[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
_11,
}
impl LPOCLKSELR {
#[doc = r" Value of the field as raw bits"]
@ -187,10 +195,14 @@ impl LPOCLKSELR {
#[doc = "Possible values of the field `RTCCLKSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RTCCLKSELR {
#[doc = "SOSCDIV1_CLK"] _00,
#[doc = "32 kHz LPO_CLK"] _01,
#[doc = "RTC_CLKIN clock"] _10,
#[doc = "FIRCDIV1_CLK"] _11,
#[doc = "SOSCDIV1_CLK"]
_00,
#[doc = "32 kHz LPO_CLK"]
_01,
#[doc = "RTC_CLKIN clock"]
_10,
#[doc = "FIRCDIV1_CLK"]
_11,
}
impl RTCCLKSELR {
#[doc = r" Value of the field as raw bits"]
@ -238,8 +250,10 @@ impl RTCCLKSELR {
}
#[doc = "Values that can be written to the field `LPO1KCLKEN`"]
pub enum LPO1KCLKENW {
#[doc = "Disable 1 kHz LPO_CLK output"] _0,
#[doc = "Enable 1 kHz LPO_CLK output"] _1,
#[doc = "Disable 1 kHz LPO_CLK output"]
_0,
#[doc = "Enable 1 kHz LPO_CLK output"]
_1,
}
impl LPO1KCLKENW {
#[allow(missing_docs)]
@ -294,8 +308,10 @@ impl<'a> _LPO1KCLKENW<'a> {
}
#[doc = "Values that can be written to the field `LPO32KCLKEN`"]
pub enum LPO32KCLKENW {
#[doc = "Disable 32 kHz LPO_CLK output"] _0,
#[doc = "Enable 32 kHz LPO_CLK output"] _1,
#[doc = "Disable 32 kHz LPO_CLK output"]
_0,
#[doc = "Enable 32 kHz LPO_CLK output"]
_1,
}
impl LPO32KCLKENW {
#[allow(missing_docs)]
@ -350,10 +366,14 @@ impl<'a> _LPO32KCLKENW<'a> {
}
#[doc = "Values that can be written to the field `LPOCLKSEL`"]
pub enum LPOCLKSELW {
#[doc = "128 kHz LPO_CLK"] _00,
#[doc = "No clock"] _01,
#[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] _10,
#[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"] _11,
#[doc = "128 kHz LPO_CLK"]
_00,
#[doc = "No clock"]
_01,
#[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
_10,
#[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
_11,
}
impl LPOCLKSELW {
#[allow(missing_docs)]
@ -412,10 +432,14 @@ impl<'a> _LPOCLKSELW<'a> {
}
#[doc = "Values that can be written to the field `RTCCLKSEL`"]
pub enum RTCCLKSELW {
#[doc = "SOSCDIV1_CLK"] _00,
#[doc = "32 kHz LPO_CLK"] _01,
#[doc = "RTC_CLKIN clock"] _10,
#[doc = "FIRCDIV1_CLK"] _11,
#[doc = "SOSCDIV1_CLK"]
_00,
#[doc = "32 kHz LPO_CLK"]
_01,
#[doc = "RTC_CLKIN clock"]
_10,
#[doc = "FIRCDIV1_CLK"]
_11,
}
impl RTCCLKSELW {
#[allow(missing_docs)]

45
src/sim/mod.rs
View File

@ -3,27 +3,42 @@ use vcell::VolatileCell;
#[repr(C)]
pub struct RegisterBlock {
_reserved0: [u8; 4usize],
#[doc = "0x04 - Chip Control register"] pub chipctl: CHIPCTL,
#[doc = "0x04 - Chip Control register"]
pub chipctl: CHIPCTL,
_reserved1: [u8; 4usize],
#[doc = "0x0c - FTM Option Register 0"] pub ftmopt0: FTMOPT0,
#[doc = "0x10 - LPO Clock Select Register"] pub lpoclks: LPOCLKS,
#[doc = "0x0c - FTM Option Register 0"]
pub ftmopt0: FTMOPT0,
#[doc = "0x10 - LPO Clock Select Register"]
pub lpoclks: LPOCLKS,
_reserved2: [u8; 4usize],
#[doc = "0x18 - ADC Options Register"] pub adcopt: ADCOPT,
#[doc = "0x1c - FTM Option Register 1"] pub ftmopt1: FTMOPT1,
#[doc = "0x20 - Miscellaneous control register 0"] pub misctrl0: MISCTRL0,
#[doc = "0x24 - System Device Identification Register"] pub sdid: SDID,
#[doc = "0x18 - ADC Options Register"]
pub adcopt: ADCOPT,
#[doc = "0x1c - FTM Option Register 1"]
pub ftmopt1: FTMOPT1,
#[doc = "0x20 - Miscellaneous control register 0"]
pub misctrl0: MISCTRL0,
#[doc = "0x24 - System Device Identification Register"]
pub sdid: SDID,
_reserved3: [u8; 24usize],
#[doc = "0x40 - Platform Clock Gating Control Register"] pub platcgc: PLATCGC,
#[doc = "0x40 - Platform Clock Gating Control Register"]
pub platcgc: PLATCGC,
_reserved4: [u8; 8usize],
#[doc = "0x4c - Flash Configuration Register 1"] pub fcfg1: FCFG1,
#[doc = "0x4c - Flash Configuration Register 1"]
pub fcfg1: FCFG1,
_reserved5: [u8; 4usize],
#[doc = "0x54 - Unique Identification Register High"] pub uidh: UIDH,
#[doc = "0x58 - Unique Identification Register Mid-High"] pub uidmh: UIDMH,
#[doc = "0x5c - Unique Identification Register Mid Low"] pub uidml: UIDML,
#[doc = "0x60 - Unique Identification Register Low"] pub uidl: UIDL,
#[doc = "0x54 - Unique Identification Register High"]
pub uidh: UIDH,
#[doc = "0x58 - Unique Identification Register Mid-High"]
pub uidmh: UIDMH,
#[doc = "0x5c - Unique Identification Register Mid Low"]
pub uidml: UIDML,
#[doc = "0x60 - Unique Identification Register Low"]
pub uidl: UIDL,
_reserved6: [u8; 4usize],
#[doc = "0x68 - System Clock Divider Register 4"] pub clkdiv4: CLKDIV4,
#[doc = "0x6c - Miscellaneous Control register 1"] pub misctrl1: MISCTRL1,
#[doc = "0x68 - System Clock Divider Register 4"]
pub clkdiv4: CLKDIV4,
#[doc = "0x6c - Miscellaneous Control register 1"]
pub misctrl1: MISCTRL1,
}
#[doc = "Chip Control register"]
pub struct CHIPCTL {

60
src/sim/platcgc/mod.rs
View File

@ -45,8 +45,10 @@ impl super::PLATCGC {
#[doc = "Possible values of the field `CGCMSCM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CGCMSCMR {
#[doc = "Clock disabled"] _0,
#[doc = "Clock enabled"] _1,
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl CGCMSCMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -90,8 +92,10 @@ impl CGCMSCMR {
#[doc = "Possible values of the field `CGCMPU`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CGCMPUR {
#[doc = "Clock disabled"] _0,
#[doc = "Clock enabled"] _1,
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl CGCMPUR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -135,8 +139,10 @@ impl CGCMPUR {
#[doc = "Possible values of the field `CGCDMA`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CGCDMAR {
#[doc = "Clock disabled"] _0,
#[doc = "Clock enabled"] _1,
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl CGCDMAR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -180,8 +186,10 @@ impl CGCDMAR {
#[doc = "Possible values of the field `CGCERM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CGCERMR {
#[doc = "Clock disabled"] _0,
#[doc = "Clock enabled"] _1,
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl CGCERMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -225,8 +233,10 @@ impl CGCERMR {
#[doc = "Possible values of the field `CGCEIM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CGCEIMR {
#[doc = "Clock disabled"] _0,
#[doc = "Clock enabled"] _1,
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl CGCEIMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
@ -269,8 +279,10 @@ impl CGCEIMR {
}
#[doc = "Values that can be written to the field `CGCMSCM`"]
pub enum CGCMSCMW {
#[doc = "Clock disabled"] _0,
#[doc = "Clock enabled"] _1,
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl CGCMSCMW {
#[allow(missing_docs)]
@ -325,8 +337,10 @@ impl<'a> _CGCMSCMW<'a> {
}
#[doc = "Values that can be written to the field `CGCMPU`"]
pub enum CGCMPUW {
#[doc = "Clock disabled"] _0,
#[doc = "Clock enabled"] _1,
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl CGCMPUW {
#[allow(missing_docs)]
@ -381,8 +395,10 @@ impl<'a> _CGCMPUW<'a> {
}
#[doc = "Values that can be written to the field `CGCDMA`"]
pub enum CGCDMAW {
#[doc = "Clock disabled"] _0,
#[doc = "Clock enabled"] _1,
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl CGCDMAW {
#[allow(missing_docs)]
@ -437,8 +453,10 @@ impl<'a> _CGCDMAW<'a> {
}
#[doc = "Values that can be written to the field `CGCERM`"]
pub enum CGCERMW {
#[doc = "Clock disabled"] _0,
#[doc = "Clock enabled"] _1,
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl CGCERMW {
#[allow(missing_docs)]
@ -493,8 +511,10 @@ impl<'a> _CGCERMW<'a> {
}
#[doc = "Values that can be written to the field `CGCEIM`"]
pub enum CGCEIMW {
#[doc = "Clock disabled"] _0,
#[doc = "Clock enabled"] _1,
#[doc = "Clock disabled"]
_0,
#[doc = "Clock enabled"]
_1,
}
impl CGCEIMW {
#[allow(missing_docs)]

39
src/sim/sdid/mod.rs
View File

@ -25,13 +25,20 @@ impl FEATURESR {
#[doc = "Possible values of the field `PACKAGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PACKAGER {
#[doc = "48 LQFP"] _0010,
#[doc = "64 LQFP"] _0011,
#[doc = "100 LQFP"] _0100,
#[doc = "144 LQFP"] _0110,
#[doc = "176 LQFP"] _0111,
#[doc = "100 MAP BGA"] _1000,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "48 LQFP"]
_0010,
#[doc = "64 LQFP"]
_0011,
#[doc = "100 LQFP"]
_0100,
#[doc = "144 LQFP"]
_0110,
#[doc = "176 LQFP"]
_0111,
#[doc = "100 MAP BGA"]
_1000,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl PACKAGER {
#[doc = r" Value of the field as raw bits"]
@ -106,12 +113,18 @@ impl REVIDR {
#[doc = "Possible values of the field `RAMSIZE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RAMSIZER {
#[doc = "128 KB (S32K148), Reserved (others)"] _0111,
#[doc = "160 KB (S32K148) , Reserved (others)"] _1001,
#[doc = "192 KB (S32K148), 16 KB (S32K142), Reserved (others)"] _1011,
#[doc = "48 KB (S32K144), 24 KB (S32K142), Reserved (others)"] _1101,
#[doc = "256 KB (S32K148), 64 KB (S32K144), 32 KB (S32K142)"] _1111,
#[doc = r" Reserved"] _Reserved(u8),
#[doc = "128 KB (S32K148), Reserved (others)"]
_0111,
#[doc = "160 KB (S32K148) , Reserved (others)"]
_1001,
#[doc = "192 KB (S32K148), 16 KB (S32K142), Reserved (others)"]
_1011,
#[doc = "48 KB (S32K144), 24 KB (S32K142), Reserved (others)"]
_1101,
#[doc = "256 KB (S32K148), 64 KB (S32K144), 32 KB (S32K142)"]
_1111,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl RAMSIZER {
#[doc = r" Value of the field as raw bits"]