Ran with svd2rust 0.12.0

2018-02-06 15:15:10 +01:00
parent 60604bcb5d
commit dd21201e79
801 changed files with 38573 additions and 19346 deletions
--- a/src/rtc/cr/mod.rs
+++ b/src/rtc/cr/mod.rs
@@ -45,8 +45,10 @@ impl super::CR {
 #[doc = "Possible values of the field `SWR`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum SWRR {
-    #[doc = "No effect."] _0,
-    #[doc = r" Reserved"] _Reserved(bool),
+    #[doc = "No effect."]
+    _0,
+    #[doc = r" Reserved"]
+    _Reserved(bool),
 }
 impl SWRR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -85,8 +87,10 @@ impl SWRR {
 #[doc = "Possible values of the field `SUP`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum SUPR {
-    #[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."] _0,
-    #[doc = "Non-supervisor mode write accesses are supported."] _1,
+    #[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."]
+    _0,
+    #[doc = "Non-supervisor mode write accesses are supported."]
+    _1,
 }
 impl SUPR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -130,8 +134,10 @@ impl SUPR {
 #[doc = "Possible values of the field `UM`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum UMR {
-    #[doc = "Registers cannot be written when locked."] _0,
-    #[doc = "Registers can be written when locked under limited conditions."] _1,
+    #[doc = "Registers cannot be written when locked."]
+    _0,
+    #[doc = "Registers can be written when locked under limited conditions."]
+    _1,
 }
 impl UMR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -175,7 +181,8 @@ impl UMR {
 #[doc = "Possible values of the field `CPS`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum CPSR {
-    #[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."] _0,
+    #[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."]
+    _0,
    #[doc = "The RTC 32kHz crystal clock is output on RTC_CLKOUT, provided it is output to other peripherals."]
    _1,
 }
@@ -221,8 +228,10 @@ impl CPSR {
 #[doc = "Possible values of the field `LPOS`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum LPOSR {
-    #[doc = "RTC prescaler increments using 32kHz crystal."] _0,
-    #[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."] _1,
+    #[doc = "RTC prescaler increments using 32kHz crystal."]
+    _0,
+    #[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."]
+    _1,
 }
 impl LPOSR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -266,8 +275,10 @@ impl LPOSR {
 #[doc = "Possible values of the field `CPE`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum CPER {
-    #[doc = "Disable RTC_CLKOUT pin."] _0,
-    #[doc = "Enable RTC_CLKOUT pin."] _1,
+    #[doc = "Disable RTC_CLKOUT pin."]
+    _0,
+    #[doc = "Enable RTC_CLKOUT pin."]
+    _1,
 }
 impl CPER {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -310,7 +321,8 @@ impl CPER {
 }
 #[doc = "Values that can be written to the field `SWR`"]
 pub enum SWRW {
-    #[doc = "No effect."] _0,
+    #[doc = "No effect."]
+    _0,
 }
 impl SWRW {
    #[allow(missing_docs)]
@@ -359,8 +371,10 @@ impl<'a> _SWRW<'a> {
 }
 #[doc = "Values that can be written to the field `SUP`"]
 pub enum SUPW {
-    #[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."] _0,
-    #[doc = "Non-supervisor mode write accesses are supported."] _1,
+    #[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."]
+    _0,
+    #[doc = "Non-supervisor mode write accesses are supported."]
+    _1,
 }
 impl SUPW {
    #[allow(missing_docs)]
@@ -415,8 +429,10 @@ impl<'a> _SUPW<'a> {
 }
 #[doc = "Values that can be written to the field `UM`"]
 pub enum UMW {
-    #[doc = "Registers cannot be written when locked."] _0,
-    #[doc = "Registers can be written when locked under limited conditions."] _1,
+    #[doc = "Registers cannot be written when locked."]
+    _0,
+    #[doc = "Registers can be written when locked under limited conditions."]
+    _1,
 }
 impl UMW {
    #[allow(missing_docs)]
@@ -471,7 +487,8 @@ impl<'a> _UMW<'a> {
 }
 #[doc = "Values that can be written to the field `CPS`"]
 pub enum CPSW {
-    #[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."] _0,
+    #[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."]
+    _0,
    #[doc = "The RTC 32kHz crystal clock is output on RTC_CLKOUT, provided it is output to other peripherals."]
    _1,
 }
@@ -528,8 +545,10 @@ impl<'a> _CPSW<'a> {
 }
 #[doc = "Values that can be written to the field `LPOS`"]
 pub enum LPOSW {
-    #[doc = "RTC prescaler increments using 32kHz crystal."] _0,
-    #[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."] _1,
+    #[doc = "RTC prescaler increments using 32kHz crystal."]
+    _0,
+    #[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."]
+    _1,
 }
 impl LPOSW {
    #[allow(missing_docs)]
@@ -584,8 +603,10 @@ impl<'a> _LPOSW<'a> {
 }
 #[doc = "Values that can be written to the field `CPE`"]
 pub enum CPEW {
-    #[doc = "Disable RTC_CLKOUT pin."] _0,
-    #[doc = "Enable RTC_CLKOUT pin."] _1,
+    #[doc = "Disable RTC_CLKOUT pin."]
+    _0,
+    #[doc = "Enable RTC_CLKOUT pin."]
+    _1,
 }
 impl CPEW {
    #[allow(missing_docs)]
--- a/src/rtc/ier/mod.rs
+++ b/src/rtc/ier/mod.rs
@@ -45,8 +45,10 @@ impl super::IER {
 #[doc = "Possible values of the field `TIIE`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum TIIER {
-    #[doc = "Time invalid flag does not generate an interrupt."] _0,
-    #[doc = "Time invalid flag does generate an interrupt."] _1,
+    #[doc = "Time invalid flag does not generate an interrupt."]
+    _0,
+    #[doc = "Time invalid flag does generate an interrupt."]
+    _1,
 }
 impl TIIER {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -90,8 +92,10 @@ impl TIIER {
 #[doc = "Possible values of the field `TOIE`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum TOIER {
-    #[doc = "Time overflow flag does not generate an interrupt."] _0,
-    #[doc = "Time overflow flag does generate an interrupt."] _1,
+    #[doc = "Time overflow flag does not generate an interrupt."]
+    _0,
+    #[doc = "Time overflow flag does generate an interrupt."]
+    _1,
 }
 impl TOIER {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -135,8 +139,10 @@ impl TOIER {
 #[doc = "Possible values of the field `TAIE`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum TAIER {
-    #[doc = "Time alarm flag does not generate an interrupt."] _0,
-    #[doc = "Time alarm flag does generate an interrupt."] _1,
+    #[doc = "Time alarm flag does not generate an interrupt."]
+    _0,
+    #[doc = "Time alarm flag does generate an interrupt."]
+    _1,
 }
 impl TAIER {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -180,8 +186,10 @@ impl TAIER {
 #[doc = "Possible values of the field `TSIE`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum TSIER {
-    #[doc = "Seconds interrupt is disabled."] _0,
-    #[doc = "Seconds interrupt is enabled."] _1,
+    #[doc = "Seconds interrupt is disabled."]
+    _0,
+    #[doc = "Seconds interrupt is enabled."]
+    _1,
 }
 impl TSIER {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -225,14 +233,22 @@ impl TSIER {
 #[doc = "Possible values of the field `TSIC`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum TSICR {
-    #[doc = "1 Hz."] _000,
-    #[doc = "2 Hz."] _001,
-    #[doc = "4 Hz."] _010,
-    #[doc = "8 Hz."] _011,
-    #[doc = "16 Hz."] _100,
-    #[doc = "32 Hz."] _101,
-    #[doc = "64 Hz."] _110,
-    #[doc = "128 Hz."] _111,
+    #[doc = "1 Hz."]
+    _000,
+    #[doc = "2 Hz."]
+    _001,
+    #[doc = "4 Hz."]
+    _010,
+    #[doc = "8 Hz."]
+    _011,
+    #[doc = "16 Hz."]
+    _100,
+    #[doc = "32 Hz."]
+    _101,
+    #[doc = "64 Hz."]
+    _110,
+    #[doc = "128 Hz."]
+    _111,
 }
 impl TSICR {
    #[doc = r" Value of the field as raw bits"]
@@ -308,8 +324,10 @@ impl TSICR {
 }
 #[doc = "Values that can be written to the field `TIIE`"]
 pub enum TIIEW {
-    #[doc = "Time invalid flag does not generate an interrupt."] _0,
-    #[doc = "Time invalid flag does generate an interrupt."] _1,
+    #[doc = "Time invalid flag does not generate an interrupt."]
+    _0,
+    #[doc = "Time invalid flag does generate an interrupt."]
+    _1,
 }
 impl TIIEW {
    #[allow(missing_docs)]
@@ -364,8 +382,10 @@ impl<'a> _TIIEW<'a> {
 }
 #[doc = "Values that can be written to the field `TOIE`"]
 pub enum TOIEW {
-    #[doc = "Time overflow flag does not generate an interrupt."] _0,
-    #[doc = "Time overflow flag does generate an interrupt."] _1,
+    #[doc = "Time overflow flag does not generate an interrupt."]
+    _0,
+    #[doc = "Time overflow flag does generate an interrupt."]
+    _1,
 }
 impl TOIEW {
    #[allow(missing_docs)]
@@ -420,8 +440,10 @@ impl<'a> _TOIEW<'a> {
 }
 #[doc = "Values that can be written to the field `TAIE`"]
 pub enum TAIEW {
-    #[doc = "Time alarm flag does not generate an interrupt."] _0,
-    #[doc = "Time alarm flag does generate an interrupt."] _1,
+    #[doc = "Time alarm flag does not generate an interrupt."]
+    _0,
+    #[doc = "Time alarm flag does generate an interrupt."]
+    _1,
 }
 impl TAIEW {
    #[allow(missing_docs)]
@@ -476,8 +498,10 @@ impl<'a> _TAIEW<'a> {
 }
 #[doc = "Values that can be written to the field `TSIE`"]
 pub enum TSIEW {
-    #[doc = "Seconds interrupt is disabled."] _0,
-    #[doc = "Seconds interrupt is enabled."] _1,
+    #[doc = "Seconds interrupt is disabled."]
+    _0,
+    #[doc = "Seconds interrupt is enabled."]
+    _1,
 }
 impl TSIEW {
    #[allow(missing_docs)]
@@ -532,14 +556,22 @@ impl<'a> _TSIEW<'a> {
 }
 #[doc = "Values that can be written to the field `TSIC`"]
 pub enum TSICW {
-    #[doc = "1 Hz."] _000,
-    #[doc = "2 Hz."] _001,
-    #[doc = "4 Hz."] _010,
-    #[doc = "8 Hz."] _011,
-    #[doc = "16 Hz."] _100,
-    #[doc = "32 Hz."] _101,
-    #[doc = "64 Hz."] _110,
-    #[doc = "128 Hz."] _111,
+    #[doc = "1 Hz."]
+    _000,
+    #[doc = "2 Hz."]
+    _001,
+    #[doc = "4 Hz."]
+    _010,
+    #[doc = "8 Hz."]
+    _011,
+    #[doc = "16 Hz."]
+    _100,
+    #[doc = "32 Hz."]
+    _101,
+    #[doc = "64 Hz."]
+    _110,
+    #[doc = "128 Hz."]
+    _111,
 }
 impl TSICW {
    #[allow(missing_docs)]
--- a/src/rtc/lr/mod.rs
+++ b/src/rtc/lr/mod.rs
@@ -45,8 +45,10 @@ impl super::LR {
 #[doc = "Possible values of the field `TCL`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum TCLR {
-    #[doc = "Time Compensation Register is locked and writes are ignored."] _0,
-    #[doc = "Time Compensation Register is not locked and writes complete as normal."] _1,
+    #[doc = "Time Compensation Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Time Compensation Register is not locked and writes complete as normal."]
+    _1,
 }
 impl TCLR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -90,8 +92,10 @@ impl TCLR {
 #[doc = "Possible values of the field `CRL`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum CRLR {
-    #[doc = "Control Register is locked and writes are ignored."] _0,
-    #[doc = "Control Register is not locked and writes complete as normal."] _1,
+    #[doc = "Control Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Control Register is not locked and writes complete as normal."]
+    _1,
 }
 impl CRLR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -135,8 +139,10 @@ impl CRLR {
 #[doc = "Possible values of the field `SRL`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum SRLR {
-    #[doc = "Status Register is locked and writes are ignored."] _0,
-    #[doc = "Status Register is not locked and writes complete as normal."] _1,
+    #[doc = "Status Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Status Register is not locked and writes complete as normal."]
+    _1,
 }
 impl SRLR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -180,8 +186,10 @@ impl SRLR {
 #[doc = "Possible values of the field `LRL`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum LRLR {
-    #[doc = "Lock Register is locked and writes are ignored."] _0,
-    #[doc = "Lock Register is not locked and writes complete as normal."] _1,
+    #[doc = "Lock Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Lock Register is not locked and writes complete as normal."]
+    _1,
 }
 impl LRLR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -224,8 +232,10 @@ impl LRLR {
 }
 #[doc = "Values that can be written to the field `TCL`"]
 pub enum TCLW {
-    #[doc = "Time Compensation Register is locked and writes are ignored."] _0,
-    #[doc = "Time Compensation Register is not locked and writes complete as normal."] _1,
+    #[doc = "Time Compensation Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Time Compensation Register is not locked and writes complete as normal."]
+    _1,
 }
 impl TCLW {
    #[allow(missing_docs)]
@@ -280,8 +290,10 @@ impl<'a> _TCLW<'a> {
 }
 #[doc = "Values that can be written to the field `CRL`"]
 pub enum CRLW {
-    #[doc = "Control Register is locked and writes are ignored."] _0,
-    #[doc = "Control Register is not locked and writes complete as normal."] _1,
+    #[doc = "Control Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Control Register is not locked and writes complete as normal."]
+    _1,
 }
 impl CRLW {
    #[allow(missing_docs)]
@@ -336,8 +348,10 @@ impl<'a> _CRLW<'a> {
 }
 #[doc = "Values that can be written to the field `SRL`"]
 pub enum SRLW {
-    #[doc = "Status Register is locked and writes are ignored."] _0,
-    #[doc = "Status Register is not locked and writes complete as normal."] _1,
+    #[doc = "Status Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Status Register is not locked and writes complete as normal."]
+    _1,
 }
 impl SRLW {
    #[allow(missing_docs)]
@@ -392,8 +406,10 @@ impl<'a> _SRLW<'a> {
 }
 #[doc = "Values that can be written to the field `LRL`"]
 pub enum LRLW {
-    #[doc = "Lock Register is locked and writes are ignored."] _0,
-    #[doc = "Lock Register is not locked and writes complete as normal."] _1,
+    #[doc = "Lock Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Lock Register is not locked and writes complete as normal."]
+    _1,
 }
 impl LRLW {
    #[allow(missing_docs)]
--- a/src/rtc/mod.rs
+++ b/src/rtc/mod.rs
@@ -2,14 +2,22 @@ use vcell::VolatileCell;
 #[doc = r" Register block"]
 #[repr(C)]
 pub struct RegisterBlock {
-    #[doc = "0x00 - RTC Time Seconds Register"] pub tsr: TSR,
-    #[doc = "0x04 - RTC Time Prescaler Register"] pub tpr: TPR,
-    #[doc = "0x08 - RTC Time Alarm Register"] pub tar: TAR,
-    #[doc = "0x0c - RTC Time Compensation Register"] pub tcr: TCR,
-    #[doc = "0x10 - RTC Control Register"] pub cr: CR,
-    #[doc = "0x14 - RTC Status Register"] pub sr: SR,
-    #[doc = "0x18 - RTC Lock Register"] pub lr: LR,
-    #[doc = "0x1c - RTC Interrupt Enable Register"] pub ier: IER,
+    #[doc = "0x00 - RTC Time Seconds Register"]
+    pub tsr: TSR,
+    #[doc = "0x04 - RTC Time Prescaler Register"]
+    pub tpr: TPR,
+    #[doc = "0x08 - RTC Time Alarm Register"]
+    pub tar: TAR,
+    #[doc = "0x0c - RTC Time Compensation Register"]
+    pub tcr: TCR,
+    #[doc = "0x10 - RTC Control Register"]
+    pub cr: CR,
+    #[doc = "0x14 - RTC Status Register"]
+    pub sr: SR,
+    #[doc = "0x18 - RTC Lock Register"]
+    pub lr: LR,
+    #[doc = "0x1c - RTC Interrupt Enable Register"]
+    pub ier: IER,
 }
 #[doc = "RTC Time Seconds Register"]
 pub struct TSR {
--- a/src/rtc/sr/mod.rs
+++ b/src/rtc/sr/mod.rs
@@ -45,8 +45,10 @@ impl super::SR {
 #[doc = "Possible values of the field `TIF`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum TIFR {
-    #[doc = "Time is valid."] _0,
-    #[doc = "Time is invalid and time counter is read as zero."] _1,
+    #[doc = "Time is valid."]
+    _0,
+    #[doc = "Time is invalid and time counter is read as zero."]
+    _1,
 }
 impl TIFR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -90,8 +92,10 @@ impl TIFR {
 #[doc = "Possible values of the field `TOF`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum TOFR {
-    #[doc = "Time overflow has not occurred."] _0,
-    #[doc = "Time overflow has occurred and time counter is read as zero."] _1,
+    #[doc = "Time overflow has not occurred."]
+    _0,
+    #[doc = "Time overflow has occurred and time counter is read as zero."]
+    _1,
 }
 impl TOFR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -135,8 +139,10 @@ impl TOFR {
 #[doc = "Possible values of the field `TAF`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum TAFR {
-    #[doc = "Time alarm has not occurred."] _0,
-    #[doc = "Time alarm has occurred."] _1,
+    #[doc = "Time alarm has not occurred."]
+    _0,
+    #[doc = "Time alarm has occurred."]
+    _1,
 }
 impl TAFR {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -180,8 +186,10 @@ impl TAFR {
 #[doc = "Possible values of the field `TCE`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum TCER {
-    #[doc = "Time counter is disabled."] _0,
-    #[doc = "Time counter is enabled."] _1,
+    #[doc = "Time counter is disabled."]
+    _0,
+    #[doc = "Time counter is enabled."]
+    _1,
 }
 impl TCER {
    #[doc = r" Returns `true` if the bit is clear (0)"]
@@ -224,8 +232,10 @@ impl TCER {
 }
 #[doc = "Values that can be written to the field `TCE`"]
 pub enum TCEW {
-    #[doc = "Time counter is disabled."] _0,
-    #[doc = "Time counter is enabled."] _1,
+    #[doc = "Time counter is disabled."]
+    _0,
+    #[doc = "Time counter is enabled."]
+    _1,
 }
 impl TCEW {
    #[allow(missing_docs)]
--- a/src/rtc/tcr/mod.rs
+++ b/src/rtc/tcr/mod.rs
@@ -45,14 +45,22 @@ impl super::TCR {
 #[doc = "Possible values of the field `TCR`"]
 #[derive(Clone, Copy, Debug, PartialEq)]
 pub enum TCRR {
-    #[doc = "Time Prescaler Register overflows every 32896 clock cycles."] _10000000,
-    #[doc = "Time Prescaler Register overflows every 32895 clock cycles."] _10000001,
-    #[doc = "Time Prescaler Register overflows every 32769 clock cycles."] _11111111,
-    #[doc = "Time Prescaler Register overflows every 32768 clock cycles."] _00000000,
-    #[doc = "Time Prescaler Register overflows every 32767 clock cycles."] _00000001,
-    #[doc = "Time Prescaler Register overflows every 32642 clock cycles."] _01111110,
-    #[doc = "Time Prescaler Register overflows every 32641 clock cycles."] _01111111,
-    #[doc = r" Reserved"] _Reserved(u8),
+    #[doc = "Time Prescaler Register overflows every 32896 clock cycles."]
+    _10000000,
+    #[doc = "Time Prescaler Register overflows every 32895 clock cycles."]
+    _10000001,
+    #[doc = "Time Prescaler Register overflows every 32769 clock cycles."]
+    _11111111,
+    #[doc = "Time Prescaler Register overflows every 32768 clock cycles."]
+    _00000000,
+    #[doc = "Time Prescaler Register overflows every 32767 clock cycles."]
+    _00000001,
+    #[doc = "Time Prescaler Register overflows every 32642 clock cycles."]
+    _01111110,
+    #[doc = "Time Prescaler Register overflows every 32641 clock cycles."]
+    _01111111,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
 }
 impl TCRR {
    #[doc = r" Value of the field as raw bits"]
@@ -155,13 +163,20 @@ impl CICR {
 }
 #[doc = "Values that can be written to the field `TCR`"]
 pub enum TCRW {
-    #[doc = "Time Prescaler Register overflows every 32896 clock cycles."] _10000000,
-    #[doc = "Time Prescaler Register overflows every 32895 clock cycles."] _10000001,
-    #[doc = "Time Prescaler Register overflows every 32769 clock cycles."] _11111111,
-    #[doc = "Time Prescaler Register overflows every 32768 clock cycles."] _00000000,
-    #[doc = "Time Prescaler Register overflows every 32767 clock cycles."] _00000001,
-    #[doc = "Time Prescaler Register overflows every 32642 clock cycles."] _01111110,
-    #[doc = "Time Prescaler Register overflows every 32641 clock cycles."] _01111111,
+    #[doc = "Time Prescaler Register overflows every 32896 clock cycles."]
+    _10000000,
+    #[doc = "Time Prescaler Register overflows every 32895 clock cycles."]
+    _10000001,
+    #[doc = "Time Prescaler Register overflows every 32769 clock cycles."]
+    _11111111,
+    #[doc = "Time Prescaler Register overflows every 32768 clock cycles."]
+    _00000000,
+    #[doc = "Time Prescaler Register overflows every 32767 clock cycles."]
+    _00000001,
+    #[doc = "Time Prescaler Register overflows every 32642 clock cycles."]
+    _01111110,
+    #[doc = "Time Prescaler Register overflows every 32641 clock cycles."]
+    _01111111,
 }
 impl TCRW {
    #[allow(missing_docs)]