xobs/s32k118.rs
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s32k118: rewrite everything for s32k118

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Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2020-12-07 18:24:29 +08:00
parent 444b0e87d1
commit 96cd7368a2
1840 changed files with 339977 additions and 617779 deletions
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6
Cargo.toml
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@ -1,12 +1,12 @@
[package] [package]
authors = ["Kjetil Kjeka <kjetilkjeka@gmail.com>"] authors = ["Kjetil Kjeka <kjetilkjeka@gmail.com>"]
name = "s32k144" name = "s32k118"
version = "0.10.0" version = "0.10.0"
description = "Peripheral access API for NXP S32K144 microcontrollers (generated using svd2rust)" description = "Peripheral access API for NXP S32K118 microcontrollers (generated using svd2rust)"
repository = "https://github.com/kjetilkjeka/s32k144.rs" repository = "https://github.com/kjetilkjeka/s32k144.rs"
keywords = ["arm", "embedded", "svd2rust", "cortex-m4", "NXP"] keywords = ["arm", "embedded", "svd2rust", "cortex-m0", "NXP"]
categories = ["embedded", "hardware-support", "no-std"] categories = ["embedded", "hardware-support", "no-std"]
license = "Apache-2.0/MIT" license = "Apache-2.0/MIT"

70780
S32K144.svd → S32K118.svd
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File diff suppressed because it is too large Load Diff

96
device.x
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@ -2,88 +2,32 @@ PROVIDE(DMA0 = DefaultHandler);
PROVIDE(DMA1 = DefaultHandler); PROVIDE(DMA1 = DefaultHandler);
PROVIDE(DMA2 = DefaultHandler); PROVIDE(DMA2 = DefaultHandler);
PROVIDE(DMA3 = DefaultHandler); PROVIDE(DMA3 = DefaultHandler);
PROVIDE(DMA4 = DefaultHandler);
PROVIDE(DMA5 = DefaultHandler);
PROVIDE(DMA6 = DefaultHandler);
PROVIDE(DMA7 = DefaultHandler);
PROVIDE(DMA8 = DefaultHandler);
PROVIDE(DMA9 = DefaultHandler);
PROVIDE(DMA10 = DefaultHandler);
PROVIDE(DMA11 = DefaultHandler);
PROVIDE(DMA12 = DefaultHandler);
PROVIDE(DMA13 = DefaultHandler);
PROVIDE(DMA14 = DefaultHandler);
PROVIDE(DMA15 = DefaultHandler);
PROVIDE(DMA_ERROR = DefaultHandler); PROVIDE(DMA_ERROR = DefaultHandler);
PROVIDE(MCM = DefaultHandler); PROVIDE(ERM_FAULT = DefaultHandler);
PROVIDE(FTFC = DefaultHandler);
PROVIDE(READ_COLLISION = DefaultHandler);
PROVIDE(LVD_LVW = DefaultHandler);
PROVIDE(FTFC_FAULT = DefaultHandler);
PROVIDE(WDOG_EWM = DefaultHandler);
PROVIDE(RCM = DefaultHandler);
PROVIDE(LPI2C0_MASTER = DefaultHandler);
PROVIDE(LPI2C0_SLAVE = DefaultHandler);
PROVIDE(LPSPI0 = DefaultHandler);
PROVIDE(LPSPI1 = DefaultHandler);
PROVIDE(LPSPI2 = DefaultHandler);
PROVIDE(LPUART0_RXTX = DefaultHandler);
PROVIDE(LPUART1_RXTX = DefaultHandler);
PROVIDE(LPUART2_RXTX = DefaultHandler);
PROVIDE(ADC0 = DefaultHandler);
PROVIDE(ADC1 = DefaultHandler);
PROVIDE(CMP0 = DefaultHandler);
PROVIDE(ERM_SINGLE_FAULT = DefaultHandler);
PROVIDE(ERM_DOUBLE_FAULT = DefaultHandler);
PROVIDE(RTC = DefaultHandler); PROVIDE(RTC = DefaultHandler);
PROVIDE(RTC_SECONDS = DefaultHandler); PROVIDE(RTC_SECONDS = DefaultHandler);
PROVIDE(LPIT0_CH0 = DefaultHandler);
PROVIDE(LPIT0_CH1 = DefaultHandler);
PROVIDE(LPIT0_CH2 = DefaultHandler);
PROVIDE(LPIT0_CH3 = DefaultHandler);
PROVIDE(PDB0 = DefaultHandler);
PROVIDE(SCG = DefaultHandler);
PROVIDE(LPTMR0 = DefaultHandler); PROVIDE(LPTMR0 = DefaultHandler);
PROVIDE(PORTA = DefaultHandler); PROVIDE(PORT = DefaultHandler);
PROVIDE(PORTB = DefaultHandler); PROVIDE(CAN0_ORED_ERR_WAKEUP = DefaultHandler);
PROVIDE(PORTC = DefaultHandler); PROVIDE(CAN0_ORED_0_31_MB = DefaultHandler);
PROVIDE(PORTD = DefaultHandler); PROVIDE(FTM0_CH0_7 = DefaultHandler);
PROVIDE(PORTE = DefaultHandler);
PROVIDE(PDB1 = DefaultHandler);
PROVIDE(FLEXIO = DefaultHandler);
PROVIDE(CAN0_ORED = DefaultHandler);
PROVIDE(CAN0_ERROR = DefaultHandler);
PROVIDE(CAN0_WAKE_UP = DefaultHandler);
PROVIDE(CAN0_ORED_0_15_MB = DefaultHandler);
PROVIDE(CAN0_ORED_16_31_MB = DefaultHandler);
PROVIDE(CAN1_ORED = DefaultHandler);
PROVIDE(CAN1_ERROR = DefaultHandler);
PROVIDE(CAN1_ORED_0_15_MB = DefaultHandler);
PROVIDE(CAN2_ORED = DefaultHandler);
PROVIDE(CAN2_ERROR = DefaultHandler);
PROVIDE(CAN2_ORED_0_15_MB = DefaultHandler);
PROVIDE(FTM0_CH0_CH1 = DefaultHandler);
PROVIDE(FTM0_CH2_CH3 = DefaultHandler);
PROVIDE(FTM0_CH4_CH5 = DefaultHandler);
PROVIDE(FTM0_CH6_CH7 = DefaultHandler);
PROVIDE(FTM0_FAULT = DefaultHandler); PROVIDE(FTM0_FAULT = DefaultHandler);
PROVIDE(FTM0_OVF_RELOAD = DefaultHandler); PROVIDE(FTM0_OVF_RELOAD = DefaultHandler);
PROVIDE(FTM1_CH0_CH1 = DefaultHandler); PROVIDE(FTM1_CH0_7 = DefaultHandler);
PROVIDE(FTM1_CH2_CH3 = DefaultHandler);
PROVIDE(FTM1_CH4_CH5 = DefaultHandler);
PROVIDE(FTM1_CH6_CH7 = DefaultHandler);
PROVIDE(FTM1_FAULT = DefaultHandler); PROVIDE(FTM1_FAULT = DefaultHandler);
PROVIDE(FTM1_OVF_RELOAD = DefaultHandler); PROVIDE(FTM1_OVF_RELOAD = DefaultHandler);
PROVIDE(FTM2_CH0_CH1 = DefaultHandler); PROVIDE(FTFC = DefaultHandler);
PROVIDE(FTM2_CH2_CH3 = DefaultHandler); PROVIDE(PDB0 = DefaultHandler);
PROVIDE(FTM2_CH4_CH5 = DefaultHandler); PROVIDE(LPIT0 = DefaultHandler);
PROVIDE(FTM2_CH6_CH7 = DefaultHandler); PROVIDE(SCG_CMU_LVD_LVWSCG = DefaultHandler);
PROVIDE(FTM2_FAULT = DefaultHandler); PROVIDE(WDOG = DefaultHandler);
PROVIDE(FTM2_OVF_RELOAD = DefaultHandler); PROVIDE(RCM = DefaultHandler);
PROVIDE(FTM3_CH0_CH1 = DefaultHandler); PROVIDE(LPI2C0_MASTER_SLAVE = DefaultHandler);
PROVIDE(FTM3_CH2_CH3 = DefaultHandler); PROVIDE(FLEXIO = DefaultHandler);
PROVIDE(FTM3_CH4_CH5 = DefaultHandler); PROVIDE(LPSPI0 = DefaultHandler);
PROVIDE(FTM3_CH6_CH7 = DefaultHandler); PROVIDE(LPSPI1 = DefaultHandler);
PROVIDE(FTM3_FAULT = DefaultHandler); PROVIDE(ADC0 = DefaultHandler);
PROVIDE(FTM3_OVF_RELOAD = DefaultHandler); PROVIDE(CMP0 = DefaultHandler);
PROVIDE(LPUART1_RXTX = DefaultHandler);
PROVIDE(LPUART0_RXTX = DefaultHandler);

718
src/adc0.rs
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@ -1,290 +1,428 @@
#[doc = r" Register block"] #[doc = r"Register block"]
#[repr(C)] #[repr(C)]
pub struct RegisterBlock { pub struct RegisterBlock {
#[doc = "0x00 - ADC Status and Control Register 1"] #[doc = "0x00 - ADC Status and Control Register 1"]
pub sc1a: SC1, pub sc1a: SC1,
#[doc = "0x04 - ADC Status and Control Register 1"] #[doc = "0x04 - ADC Status and Control Register 1"]
pub sc1b: SC1, pub sc1b: SC1,
#[doc = "0x08 - ADC Status and Control Register 1"] #[doc = "0x08 - ADC Status and Control Register 1"]
pub sc1c: SC1, pub sc1c: SC1,
#[doc = "0x0c - ADC Status and Control Register 1"] #[doc = "0x0c - ADC Status and Control Register 1"]
pub sc1d: SC1, pub sc1d: SC1,
#[doc = "0x10 - ADC Status and Control Register 1"] #[doc = "0x10 - ADC Status and Control Register 1"]
pub sc1e: SC1, pub sc1e: SC1,
#[doc = "0x14 - ADC Status and Control Register 1"] #[doc = "0x14 - ADC Status and Control Register 1"]
pub sc1f: SC1, pub sc1f: SC1,
#[doc = "0x18 - ADC Status and Control Register 1"] #[doc = "0x18 - ADC Status and Control Register 1"]
pub sc1g: SC1, pub sc1g: SC1,
#[doc = "0x1c - ADC Status and Control Register 1"] #[doc = "0x1c - ADC Status and Control Register 1"]
pub sc1h: SC1, pub sc1h: SC1,
#[doc = "0x20 - ADC Status and Control Register 1"] #[doc = "0x20 - ADC Status and Control Register 1"]
pub sc1i: SC1, pub sc1i: SC1,
#[doc = "0x24 - ADC Status and Control Register 1"] #[doc = "0x24 - ADC Status and Control Register 1"]
pub sc1j: SC1, pub sc1j: SC1,
#[doc = "0x28 - ADC Status and Control Register 1"] #[doc = "0x28 - ADC Status and Control Register 1"]
pub sc1k: SC1, pub sc1k: SC1,
#[doc = "0x2c - ADC Status and Control Register 1"] #[doc = "0x2c - ADC Status and Control Register 1"]
pub sc1l: SC1, pub sc1l: SC1,
#[doc = "0x30 - ADC Status and Control Register 1"] #[doc = "0x30 - ADC Status and Control Register 1"]
pub sc1m: SC1, pub sc1m: SC1,
#[doc = "0x34 - ADC Status and Control Register 1"] #[doc = "0x34 - ADC Status and Control Register 1"]
pub sc1n: SC1, pub sc1n: SC1,
#[doc = "0x38 - ADC Status and Control Register 1"] #[doc = "0x38 - ADC Status and Control Register 1"]
pub sc1o: SC1, pub sc1o: SC1,
#[doc = "0x3c - ADC Status and Control Register 1"] #[doc = "0x3c - ADC Status and Control Register 1"]
pub sc1p: SC1, pub sc1p: SC1,
#[doc = "0x40 - ADC Configuration Register 1"] #[doc = "0x40 - ADC Configuration Register 1"]
pub cfg1: CFG1, pub cfg1: CFG1,
#[doc = "0x44 - ADC Configuration Register 2"] #[doc = "0x44 - ADC Configuration Register 2"]
pub cfg2: CFG2, pub cfg2: CFG2,
#[doc = "0x48 - ADC Data Result Registers"] #[doc = "0x48 - ADC Data Result Registers"]
pub ra: R, pub ra: R,
#[doc = "0x4c - ADC Data Result Registers"] #[doc = "0x4c - ADC Data Result Registers"]
pub rb: R, pub rb: R,
#[doc = "0x50 - ADC Data Result Registers"] #[doc = "0x50 - ADC Data Result Registers"]
pub rc: R, pub rc: R,
#[doc = "0x54 - ADC Data Result Registers"] #[doc = "0x54 - ADC Data Result Registers"]
pub rd: R, pub rd: R,
#[doc = "0x58 - ADC Data Result Registers"] #[doc = "0x58 - ADC Data Result Registers"]
pub re: R, pub re: R,
#[doc = "0x5c - ADC Data Result Registers"] #[doc = "0x5c - ADC Data Result Registers"]
pub rf: R, pub rf: R,
#[doc = "0x60 - ADC Data Result Registers"] #[doc = "0x60 - ADC Data Result Registers"]
pub rg: R, pub rg: R,
#[doc = "0x64 - ADC Data Result Registers"] #[doc = "0x64 - ADC Data Result Registers"]
pub rh: R, pub rh: R,
#[doc = "0x68 - ADC Data Result Registers"] #[doc = "0x68 - ADC Data Result Registers"]
pub ri: R, pub ri: R,
#[doc = "0x6c - ADC Data Result Registers"] #[doc = "0x6c - ADC Data Result Registers"]
pub rj: R, pub rj: R,
#[doc = "0x70 - ADC Data Result Registers"] #[doc = "0x70 - ADC Data Result Registers"]
pub rk: R, pub rk: R,
#[doc = "0x74 - ADC Data Result Registers"] #[doc = "0x74 - ADC Data Result Registers"]
pub rl: R, pub rl: R,
#[doc = "0x78 - ADC Data Result Registers"] #[doc = "0x78 - ADC Data Result Registers"]
pub rm: R, pub rm: R,
#[doc = "0x7c - ADC Data Result Registers"] #[doc = "0x7c - ADC Data Result Registers"]
pub rn: R, pub rn: R,
#[doc = "0x80 - ADC Data Result Registers"] #[doc = "0x80 - ADC Data Result Registers"]
pub ro: R, pub ro: R,
#[doc = "0x84 - ADC Data Result Registers"] #[doc = "0x84 - ADC Data Result Registers"]
pub rp: R, pub rp: R,
#[doc = "0x88 - Compare Value Registers"] #[doc = "0x88 - Compare Value Registers"]
pub cv1: CV, pub cv1: CV,
#[doc = "0x8c - Compare Value Registers"] #[doc = "0x8c - Compare Value Registers"]
pub cv2: CV, pub cv2: CV,
#[doc = "0x90 - Status and Control Register 2"] #[doc = "0x90 - Status and Control Register 2"]
pub sc2: SC2, pub sc2: SC2,
#[doc = "0x94 - Status and Control Register 3"] #[doc = "0x94 - Status and Control Register 3"]
pub sc3: SC3, pub sc3: SC3,
#[doc = "0x98 - BASE Offset Register"] #[doc = "0x98 - BASE Offset Register"]
pub base_ofs: BASE_OFS, pub base_ofs: BASE_OFS,
#[doc = "0x9c - ADC Offset Correction Register"] #[doc = "0x9c - ADC Offset Correction Register"]
pub ofs: OFS, pub ofs: OFS,
#[doc = "0xa0 - USER Offset Correction Register"] #[doc = "0xa0 - USER Offset Correction Register"]
pub usr_ofs: USR_OFS, pub usr_ofs: USR_OFS,
#[doc = "0xa4 - ADC X Offset Correction Register"] #[doc = "0xa4 - ADC X Offset Correction Register"]
pub xofs: XOFS, pub xofs: XOFS,
#[doc = "0xa8 - ADC Y Offset Correction Register"] #[doc = "0xa8 - ADC Y Offset Correction Register"]
pub yofs: YOFS, pub yofs: YOFS,
#[doc = "0xac - ADC Gain Register"] #[doc = "0xac - ADC Gain Register"]
pub g: G, pub g: G,
#[doc = "0xb0 - ADC User Gain Register"] #[doc = "0xb0 - ADC User Gain Register"]
pub ug: UG, pub ug: UG,
#[doc = "0xb4 - ADC General Calibration Value Register S"] #[doc = "0xb4 - ADC General Calibration Value Register S"]
pub clps: CLPS, pub clps: CLPS,
#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"] #[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
pub clp3: CLP3, pub clp3: CLP3,
#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"] #[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
pub clp2: CLP2, pub clp2: CLP2,
#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"] #[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
pub clp1: CLP1, pub clp1: CLP1,
#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"] #[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
pub clp0: CLP0, pub clp0: CLP0,
#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"] #[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
pub clpx: CLPX, pub clpx: CLPX,
#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"] #[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
pub clp9: CLP9, pub clp9: CLP9,
#[doc = "0xd0 - ADC General Calibration Offset Value Register S"] #[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
pub clps_ofs: CLPS_OFS, pub clps_ofs: CLPS_OFS,
#[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"] #[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
pub clp3_ofs: CLP3_OFS, pub clp3_ofs: CLP3_OFS,
#[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"] #[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
pub clp2_ofs: CLP2_OFS, pub clp2_ofs: CLP2_OFS,
#[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"] #[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
pub clp1_ofs: CLP1_OFS, pub clp1_ofs: CLP1_OFS,
#[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"] #[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
pub clp0_ofs: CLP0_OFS, pub clp0_ofs: CLP0_OFS,
#[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"] #[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
pub clpx_ofs: CLPX_OFS, pub clpx_ofs: CLPX_OFS,
#[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"] #[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
pub clp9_ofs: CLP9_OFS, pub clp9_ofs: CLP9_OFS,
} }
#[doc = "ADC Status and Control Register 1"] #[doc = "ADC Status and Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sc1](sc1) module"]
pub struct SC1 { pub type SC1 = crate::Reg<u32, _SC1>;
register: ::vcell::VolatileCell<u32>, #[allow(missing_docs)]
} #[doc(hidden)]
#[doc = "ADC Status and Control Register 1"] pub struct _SC1;
pub mod sc1; #[doc = "`read()` method returns [sc1::R](sc1::R) reader structure"]
#[doc = "ADC Configuration Register 1"] impl crate::Readable for SC1 {}
pub struct CFG1 { #[doc = "`write(|w| ..)` method takes [sc1::W](sc1::W) writer structure"]
register: ::vcell::VolatileCell<u32>, impl crate::Writable for SC1 {}
} #[doc = "ADC Status and Control Register 1"]
#[doc = "ADC Configuration Register 1"] pub mod sc1;
pub mod cfg1; #[doc = "ADC Configuration Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg1](cfg1) module"]
#[doc = "ADC Configuration Register 2"] pub type CFG1 = crate::Reg<u32, _CFG1>;
pub struct CFG2 { #[allow(missing_docs)]
register: ::vcell::VolatileCell<u32>, #[doc(hidden)]
} pub struct _CFG1;
#[doc = "ADC Configuration Register 2"] #[doc = "`read()` method returns [cfg1::R](cfg1::R) reader structure"]
pub mod cfg2; impl crate::Readable for CFG1 {}
#[doc = "ADC Data Result Registers"] #[doc = "`write(|w| ..)` method takes [cfg1::W](cfg1::W) writer structure"]
pub struct R { impl crate::Writable for CFG1 {}
register: ::vcell::VolatileCell<u32>, #[doc = "ADC Configuration Register 1"]
} pub mod cfg1;
#[doc = "ADC Data Result Registers"] #[doc = "ADC Configuration Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg2](cfg2) module"]
pub mod r; pub type CFG2 = crate::Reg<u32, _CFG2>;
#[doc = "Compare Value Registers"] #[allow(missing_docs)]
pub struct CV { #[doc(hidden)]
register: ::vcell::VolatileCell<u32>, pub struct _CFG2;
} #[doc = "`read()` method returns [cfg2::R](cfg2::R) reader structure"]
#[doc = "Compare Value Registers"] impl crate::Readable for CFG2 {}
pub mod cv; #[doc = "`write(|w| ..)` method takes [cfg2::W](cfg2::W) writer structure"]
#[doc = "Status and Control Register 2"] impl crate::Writable for CFG2 {}
pub struct SC2 { #[doc = "ADC Configuration Register 2"]
register: ::vcell::VolatileCell<u32>, pub mod cfg2;
} #[doc = "ADC Data Result Registers\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r](r) module"]
#[doc = "Status and Control Register 2"] pub type R = crate::Reg<u32, _R>;
pub mod sc2; #[allow(missing_docs)]
#[doc = "Status and Control Register 3"] #[doc(hidden)]
pub struct SC3 { pub struct _R;
register: ::vcell::VolatileCell<u32>, #[doc = "`read()` method returns [r::R](r::R) reader structure"]
} impl crate::Readable for R {}
#[doc = "Status and Control Register 3"] #[doc = "ADC Data Result Registers"]
pub mod sc3; pub mod r;
#[doc = "BASE Offset Register"] #[doc = "Compare Value Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cv](cv) module"]
pub struct BASE_OFS { pub type CV = crate::Reg<u32, _CV>;
register: ::vcell::VolatileCell<u32>, #[allow(missing_docs)]
} #[doc(hidden)]
#[doc = "BASE Offset Register"] pub struct _CV;
pub mod base_ofs; #[doc = "`read()` method returns [cv::R](cv::R) reader structure"]
#[doc = "ADC Offset Correction Register"] impl crate::Readable for CV {}
pub struct OFS { #[doc = "`write(|w| ..)` method takes [cv::W](cv::W) writer structure"]
register: ::vcell::VolatileCell<u32>, impl crate::Writable for CV {}
} #[doc = "Compare Value Registers"]
#[doc = "ADC Offset Correction Register"] pub mod cv;
pub mod ofs; #[doc = "Status and Control Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sc2](sc2) module"]
#[doc = "USER Offset Correction Register"] pub type SC2 = crate::Reg<u32, _SC2>;
pub struct USR_OFS { #[allow(missing_docs)]
register: ::vcell::VolatileCell<u32>, #[doc(hidden)]
} pub struct _SC2;
#[doc = "USER Offset Correction Register"] #[doc = "`read()` method returns [sc2::R](sc2::R) reader structure"]
pub mod usr_ofs; impl crate::Readable for SC2 {}
#[doc = "ADC X Offset Correction Register"] #[doc = "`write(|w| ..)` method takes [sc2::W](sc2::W) writer structure"]
pub struct XOFS { impl crate::Writable for SC2 {}
register: ::vcell::VolatileCell<u32>, #[doc = "Status and Control Register 2"]
} pub mod sc2;
#[doc = "ADC X Offset Correction Register"] #[doc = "Status and Control Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sc3](sc3) module"]
pub mod xofs; pub type SC3 = crate::Reg<u32, _SC3>;
#[doc = "ADC Y Offset Correction Register"] #[allow(missing_docs)]
pub struct YOFS { #[doc(hidden)]
register: ::vcell::VolatileCell<u32>, pub struct _SC3;
} #[doc = "`read()` method returns [sc3::R](sc3::R) reader structure"]
#[doc = "ADC Y Offset Correction Register"] impl crate::Readable for SC3 {}
pub mod yofs; #[doc = "`write(|w| ..)` method takes [sc3::W](sc3::W) writer structure"]
#[doc = "ADC Gain Register"] impl crate::Writable for SC3 {}
pub struct G { #[doc = "Status and Control Register 3"]
register: ::vcell::VolatileCell<u32>, pub mod sc3;
} #[doc = "BASE Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base_ofs](base_ofs) module"]
#[doc = "ADC Gain Register"] pub type BASE_OFS = crate::Reg<u32, _BASE_OFS>;
pub mod g; #[allow(missing_docs)]
#[doc = "ADC User Gain Register"] #[doc(hidden)]
pub struct UG { pub struct _BASE_OFS;
register: ::vcell::VolatileCell<u32>, #[doc = "`read()` method returns [base_ofs::R](base_ofs::R) reader structure"]
} impl crate::Readable for BASE_OFS {}
#[doc = "ADC User Gain Register"] #[doc = "`write(|w| ..)` method takes [base_ofs::W](base_ofs::W) writer structure"]
pub mod ug; impl crate::Writable for BASE_OFS {}
#[doc = "ADC General Calibration Value Register S"] #[doc = "BASE Offset Register"]
pub struct CLPS { pub mod base_ofs;
register: ::vcell::VolatileCell<u32>, #[doc = "ADC Offset Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ofs](ofs) module"]
} pub type OFS = crate::Reg<u32, _OFS>;
#[doc = "ADC General Calibration Value Register S"] #[allow(missing_docs)]
pub mod clps; #[doc(hidden)]
#[doc = "ADC Plus-Side General Calibration Value Register 3"] pub struct _OFS;
pub struct CLP3 { #[doc = "`read()` method returns [ofs::R](ofs::R) reader structure"]
register: ::vcell::VolatileCell<u32>, impl crate::Readable for OFS {}
} #[doc = "`write(|w| ..)` method takes [ofs::W](ofs::W) writer structure"]
#[doc = "ADC Plus-Side General Calibration Value Register 3"] impl crate::Writable for OFS {}
pub mod clp3; #[doc = "ADC Offset Correction Register"]
#[doc = "ADC Plus-Side General Calibration Value Register 2"] pub mod ofs;
pub struct CLP2 { #[doc = "USER Offset Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usr_ofs](usr_ofs) module"]
register: ::vcell::VolatileCell<u32>, pub type USR_OFS = crate::Reg<u32, _USR_OFS>;
} #[allow(missing_docs)]
#[doc = "ADC Plus-Side General Calibration Value Register 2"] #[doc(hidden)]
pub mod clp2; pub struct _USR_OFS;
#[doc = "ADC Plus-Side General Calibration Value Register 1"] #[doc = "`read()` method returns [usr_ofs::R](usr_ofs::R) reader structure"]
pub struct CLP1 { impl crate::Readable for USR_OFS {}
register: ::vcell::VolatileCell<u32>, #[doc = "`write(|w| ..)` method takes [usr_ofs::W](usr_ofs::W) writer structure"]
} impl crate::Writable for USR_OFS {}
#[doc = "ADC Plus-Side General Calibration Value Register 1"] #[doc = "USER Offset Correction Register"]
pub mod clp1; pub mod usr_ofs;
#[doc = "ADC Plus-Side General Calibration Value Register 0"] #[doc = "ADC X Offset Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xofs](xofs) module"]
pub struct CLP0 { pub type XOFS = crate::Reg<u32, _XOFS>;
register: ::vcell::VolatileCell<u32>, #[allow(missing_docs)]
} #[doc(hidden)]
#[doc = "ADC Plus-Side General Calibration Value Register 0"] pub struct _XOFS;
pub mod clp0; #[doc = "`read()` method returns [xofs::R](xofs::R) reader structure"]
#[doc = "ADC Plus-Side General Calibration Value Register X"] impl crate::Readable for XOFS {}
pub struct CLPX { #[doc = "`write(|w| ..)` method takes [xofs::W](xofs::W) writer structure"]
register: ::vcell::VolatileCell<u32>, impl crate::Writable for XOFS {}
} #[doc = "ADC X Offset Correction Register"]
#[doc = "ADC Plus-Side General Calibration Value Register X"] pub mod xofs;
pub mod clpx; #[doc = "ADC Y Offset Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [yofs](yofs) module"]
#[doc = "ADC Plus-Side General Calibration Value Register 9"] pub type YOFS = crate::Reg<u32, _YOFS>;
pub struct CLP9 { #[allow(missing_docs)]
register: ::vcell::VolatileCell<u32>, #[doc(hidden)]
} pub struct _YOFS;
#[doc = "ADC Plus-Side General Calibration Value Register 9"] #[doc = "`read()` method returns [yofs::R](yofs::R) reader structure"]
pub mod clp9; impl crate::Readable for YOFS {}
#[doc = "ADC General Calibration Offset Value Register S"] #[doc = "`write(|w| ..)` method takes [yofs::W](yofs::W) writer structure"]
pub struct CLPS_OFS { impl crate::Writable for YOFS {}
register: ::vcell::VolatileCell<u32>, #[doc = "ADC Y Offset Correction Register"]
} pub mod yofs;
#[doc = "ADC General Calibration Offset Value Register S"] #[doc = "ADC Gain Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [g](g) module"]
pub mod clps_ofs; pub type G = crate::Reg<u32, _G>;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"] #[allow(missing_docs)]
pub struct CLP3_OFS { #[doc(hidden)]
register: ::vcell::VolatileCell<u32>, pub struct _G;
} #[doc = "`read()` method returns [g::R](g::R) reader structure"]
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"] impl crate::Readable for G {}
pub mod clp3_ofs; #[doc = "`write(|w| ..)` method takes [g::W](g::W) writer structure"]
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"] impl crate::Writable for G {}
pub struct CLP2_OFS { #[doc = "ADC Gain Register"]
register: ::vcell::VolatileCell<u32>, pub mod g;
} #[doc = "ADC User Gain Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ug](ug) module"]
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"] pub type UG = crate::Reg<u32, _UG>;
pub mod clp2_ofs; #[allow(missing_docs)]
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"] #[doc(hidden)]
pub struct CLP1_OFS { pub struct _UG;
register: ::vcell::VolatileCell<u32>, #[doc = "`read()` method returns [ug::R](ug::R) reader structure"]
} impl crate::Readable for UG {}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"] #[doc = "`write(|w| ..)` method takes [ug::W](ug::W) writer structure"]
pub mod clp1_ofs; impl crate::Writable for UG {}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"] #[doc = "ADC User Gain Register"]
pub struct CLP0_OFS { pub mod ug;
register: ::vcell::VolatileCell<u32>, #[doc = "ADC General Calibration Value Register S\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clps](clps) module"]
} pub type CLPS = crate::Reg<u32, _CLPS>;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"] #[allow(missing_docs)]
pub mod clp0_ofs; #[doc(hidden)]
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"] pub struct _CLPS;
pub struct CLPX_OFS { #[doc = "`read()` method returns [clps::R](clps::R) reader structure"]
register: ::vcell::VolatileCell<u32>, impl crate::Readable for CLPS {}
} #[doc = "`write(|w| ..)` method takes [clps::W](clps::W) writer structure"]
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"] impl crate::Writable for CLPS {}
pub mod clpx_ofs; #[doc = "ADC General Calibration Value Register S"]
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"] pub mod clps;
pub struct CLP9_OFS { #[doc = "ADC Plus-Side General Calibration Value Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp3](clp3) module"]
register: ::vcell::VolatileCell<u32>, pub type CLP3 = crate::Reg<u32, _CLP3>;
} #[allow(missing_docs)]
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"] #[doc(hidden)]
pub mod clp9_ofs; pub struct _CLP3;
#[doc = "`read()` method returns [clp3::R](clp3::R) reader structure"]
impl crate::Readable for CLP3 {}
#[doc = "`write(|w| ..)` method takes [clp3::W](clp3::W) writer structure"]
impl crate::Writable for CLP3 {}
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
pub mod clp3;
#[doc = "ADC Plus-Side General Calibration Value Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp2](clp2) module"]
pub type CLP2 = crate::Reg<u32, _CLP2>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CLP2;
#[doc = "`read()` method returns [clp2::R](clp2::R) reader structure"]
impl crate::Readable for CLP2 {}
#[doc = "`write(|w| ..)` method takes [clp2::W](clp2::W) writer structure"]
impl crate::Writable for CLP2 {}
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
pub mod clp2;
#[doc = "ADC Plus-Side General Calibration Value Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp1](clp1) module"]
pub type CLP1 = crate::Reg<u32, _CLP1>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CLP1;
#[doc = "`read()` method returns [clp1::R](clp1::R) reader structure"]
impl crate::Readable for CLP1 {}
#[doc = "`write(|w| ..)` method takes [clp1::W](clp1::W) writer structure"]
impl crate::Writable for CLP1 {}
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
pub mod clp1;
#[doc = "ADC Plus-Side General Calibration Value Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp0](clp0) module"]
pub type CLP0 = crate::Reg<u32, _CLP0>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CLP0;
#[doc = "`read()` method returns [clp0::R](clp0::R) reader structure"]
impl crate::Readable for CLP0 {}
#[doc = "`write(|w| ..)` method takes [clp0::W](clp0::W) writer structure"]
impl crate::Writable for CLP0 {}
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
pub mod clp0;
#[doc = "ADC Plus-Side General Calibration Value Register X\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clpx](clpx) module"]
pub type CLPX = crate::Reg<u32, _CLPX>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CLPX;
#[doc = "`read()` method returns [clpx::R](clpx::R) reader structure"]
impl crate::Readable for CLPX {}
#[doc = "`write(|w| ..)` method takes [clpx::W](clpx::W) writer structure"]
impl crate::Writable for CLPX {}
#[doc = "ADC Plus-Side General Calibration Value Register X"]
pub mod clpx;
#[doc = "ADC Plus-Side General Calibration Value Register 9\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp9](clp9) module"]
pub type CLP9 = crate::Reg<u32, _CLP9>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CLP9;
#[doc = "`read()` method returns [clp9::R](clp9::R) reader structure"]
impl crate::Readable for CLP9 {}
#[doc = "`write(|w| ..)` method takes [clp9::W](clp9::W) writer structure"]
impl crate::Writable for CLP9 {}
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
pub mod clp9;
#[doc = "ADC General Calibration Offset Value Register S\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clps_ofs](clps_ofs) module"]
pub type CLPS_OFS = crate::Reg<u32, _CLPS_OFS>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CLPS_OFS;
#[doc = "`read()` method returns [clps_ofs::R](clps_ofs::R) reader structure"]
impl crate::Readable for CLPS_OFS {}
#[doc = "`write(|w| ..)` method takes [clps_ofs::W](clps_ofs::W) writer structure"]
impl crate::Writable for CLPS_OFS {}
#[doc = "ADC General Calibration Offset Value Register S"]
pub mod clps_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp3_ofs](clp3_ofs) module"]
pub type CLP3_OFS = crate::Reg<u32, _CLP3_OFS>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CLP3_OFS;
#[doc = "`read()` method returns [clp3_ofs::R](clp3_ofs::R) reader structure"]
impl crate::Readable for CLP3_OFS {}
#[doc = "`write(|w| ..)` method takes [clp3_ofs::W](clp3_ofs::W) writer structure"]
impl crate::Writable for CLP3_OFS {}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
pub mod clp3_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp2_ofs](clp2_ofs) module"]
pub type CLP2_OFS = crate::Reg<u32, _CLP2_OFS>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CLP2_OFS;
#[doc = "`read()` method returns [clp2_ofs::R](clp2_ofs::R) reader structure"]
impl crate::Readable for CLP2_OFS {}
#[doc = "`write(|w| ..)` method takes [clp2_ofs::W](clp2_ofs::W) writer structure"]
impl crate::Writable for CLP2_OFS {}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
pub mod clp2_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp1_ofs](clp1_ofs) module"]
pub type CLP1_OFS = crate::Reg<u32, _CLP1_OFS>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CLP1_OFS;
#[doc = "`read()` method returns [clp1_ofs::R](clp1_ofs::R) reader structure"]
impl crate::Readable for CLP1_OFS {}
#[doc = "`write(|w| ..)` method takes [clp1_ofs::W](clp1_ofs::W) writer structure"]
impl crate::Writable for CLP1_OFS {}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
pub mod clp1_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp0_ofs](clp0_ofs) module"]
pub type CLP0_OFS = crate::Reg<u32, _CLP0_OFS>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CLP0_OFS;
#[doc = "`read()` method returns [clp0_ofs::R](clp0_ofs::R) reader structure"]
impl crate::Readable for CLP0_OFS {}
#[doc = "`write(|w| ..)` method takes [clp0_ofs::W](clp0_ofs::W) writer structure"]
impl crate::Writable for CLP0_OFS {}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
pub mod clp0_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register X\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clpx_ofs](clpx_ofs) module"]
pub type CLPX_OFS = crate::Reg<u32, _CLPX_OFS>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CLPX_OFS;
#[doc = "`read()` method returns [clpx_ofs::R](clpx_ofs::R) reader structure"]
impl crate::Readable for CLPX_OFS {}
#[doc = "`write(|w| ..)` method takes [clpx_ofs::W](clpx_ofs::W) writer structure"]
impl crate::Writable for CLPX_OFS {}
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
pub mod clpx_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp9_ofs](clp9_ofs) module"]
pub type CLP9_OFS = crate::Reg<u32, _CLP9_OFS>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _CLP9_OFS;
#[doc = "`read()` method returns [clp9_ofs::R](clp9_ofs::R) reader structure"]
impl crate::Readable for CLP9_OFS {}
#[doc = "`write(|w| ..)` method takes [clp9_ofs::W](clp9_ofs::W) writer structure"]
impl crate::Writable for CLP9_OFS {}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
pub mod clp9_ofs;

143
src/adc0/base_ofs.rs
View File

@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register BASE_OFS"]
pub struct R { pub type R = crate::R<u32, super::BASE_OFS>;
bits: u32, #[doc = "Writer for register BASE_OFS"]
} pub type W = crate::W<u32, super::BASE_OFS>;
#[doc = r" Value to write to the register"] #[doc = "Register BASE_OFS `reset()`'s with value 0x40"]
pub struct W { impl crate::ResetValue for super::BASE_OFS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::BASE_OFS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x40
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `BA_OFS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type BA_OFS_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `BA_OFS`"]
let bits = self.register.get(); pub struct BA_OFS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> BA_OFS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:7 - Base Offset Error Correction Value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn ba_ofs(&self) -> BA_OFS_R {
F: FnOnce(&mut W) -> &mut W, BA_OFS_R::new((self.bits & 0xff) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:7 - Base Offset Error Correction Value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn ba_ofs(&mut self) -> BA_OFS_W {
#[inline] BA_OFS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct BA_OFSR {
bits: u8,
}
impl BA_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _BA_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _BA_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
#[inline]
pub fn ba_ofs(&self) -> BA_OFSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
BA_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 64 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
#[inline]
pub fn ba_ofs(&mut self) -> _BA_OFSW {
_BA_OFSW { w: self }
}
}

820
src/adc0/cfg1.rs
View File

@ -1,482 +1,338 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CFG1"]
pub struct R { pub type R = crate::R<u32, super::CFG1>;
bits: u32, #[doc = "Writer for register CFG1"]
} pub type W = crate::W<u32, super::CFG1>;
#[doc = r" Value to write to the register"] #[doc = "Register CFG1 `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::CFG1 {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CFG1 { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Input Clock Select\n\nValue on reset: 0"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, #[derive(Clone, Copy, Debug, PartialEq)]
{ #[repr(u8)]
let bits = self.register.get(); pub enum ADICLK_A {
let r = R { bits: bits }; #[doc = "0: Alternate clock 1 (ADC_ALTCLK1)"]
let mut w = W { bits: bits }; _00 = 0,
f(&r, &mut w); #[doc = "1: Alternate clock 2 (ADC_ALTCLK2)"]
self.register.set(w.bits); _01 = 1,
} #[doc = "2: Alternate clock 3 (ADC_ALTCLK3)"]
#[doc = r" Reads the contents of the register"] _10 = 2,
#[inline] #[doc = "3: Alternate clock 4 (ADC_ALTCLK4)"]
pub fn read(&self) -> R { _11 = 3,
R { bits: self.register.get() } }
} impl From<ADICLK_A> for u8 {
#[doc = r" Writes to the register"] #[inline(always)]
#[inline] fn from(variant: ADICLK_A) -> Self {
pub fn write<F>(&self, f: F) variant as _
where }
F: FnOnce(&mut W) -> &mut W, }
{ #[doc = "Reader of field `ADICLK`"]
let mut w = W::reset_value(); pub type ADICLK_R = crate::R<u8, ADICLK_A>;
f(&mut w); impl ADICLK_R {
self.register.set(w.bits); #[doc = r"Get enumerated values variant"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn variant(&self) -> ADICLK_A {
#[inline] match self.bits {
pub fn reset(&self) { 0 => ADICLK_A::_00,
self.write(|w| w) 1 => ADICLK_A::_01,
} 2 => ADICLK_A::_10,
} 3 => ADICLK_A::_11,
#[doc = "Possible values of the field `ADICLK`"] _ => unreachable!(),
#[derive(Clone, Copy, Debug, PartialEq)] }
pub enum ADICLKR { }
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"] #[doc = "Checks if the value of the field is `_00`"]
_00, #[inline(always)]
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"] pub fn is_00(&self) -> bool {
_01, *self == ADICLK_A::_00
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"] }
_10, #[doc = "Checks if the value of the field is `_01`"]
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"] #[inline(always)]
_11, pub fn is_01(&self) -> bool {
} *self == ADICLK_A::_01
impl ADICLKR { }
#[doc = r" Value of the field as raw bits"] #[doc = "Checks if the value of the field is `_10`"]
#[inline] #[inline(always)]
pub fn bits(&self) -> u8 { pub fn is_10(&self) -> bool {
match *self { *self == ADICLK_A::_10
ADICLKR::_00 => 0, }
ADICLKR::_01 => 1, #[doc = "Checks if the value of the field is `_11`"]
ADICLKR::_10 => 2, #[inline(always)]
ADICLKR::_11 => 3, pub fn is_11(&self) -> bool {
} *self == ADICLK_A::_11
} }
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = "Write proxy for field `ADICLK`"]
#[inline] pub struct ADICLK_W<'a> {
pub fn _from(value: u8) -> ADICLKR { w: &'a mut W,
match value { }
0 => ADICLKR::_00, impl<'a> ADICLK_W<'a> {
1 => ADICLKR::_01, #[doc = r"Writes `variant` to the field"]
2 => ADICLKR::_10, #[inline(always)]
3 => ADICLKR::_11, pub fn variant(self, variant: ADICLK_A) -> &'a mut W {
_ => unreachable!(), {
} self.bits(variant.into())
} }
#[doc = "Checks if the value of the field is `_00`"] }
#[inline] #[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
pub fn is_00(&self) -> bool { #[inline(always)]
*self == ADICLKR::_00 pub fn _00(self) -> &'a mut W {
} self.variant(ADICLK_A::_00)
#[doc = "Checks if the value of the field is `_01`"] }
#[inline] #[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
pub fn is_01(&self) -> bool { #[inline(always)]
*self == ADICLKR::_01 pub fn _01(self) -> &'a mut W {
} self.variant(ADICLK_A::_01)
#[doc = "Checks if the value of the field is `_10`"] }
#[inline] #[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
pub fn is_10(&self) -> bool { #[inline(always)]
*self == ADICLKR::_10 pub fn _10(self) -> &'a mut W {
} self.variant(ADICLK_A::_10)
#[doc = "Checks if the value of the field is `_11`"] }
#[inline] #[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
pub fn is_11(&self) -> bool { #[inline(always)]
*self == ADICLKR::_11 pub fn _11(self) -> &'a mut W {
} self.variant(ADICLK_A::_11)
} }
#[doc = "Possible values of the field `MODE`"] #[doc = r"Writes raw bits to the field"]
#[derive(Clone, Copy, Debug, PartialEq)] #[inline(always)]
pub enum MODER { pub fn bits(self, value: u8) -> &'a mut W {
#[doc = "8-bit conversion."] self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
_00, self.w
#[doc = "12-bit conversion."] }
_01, }
#[doc = "10-bit conversion."] #[doc = "Conversion mode selection\n\nValue on reset: 0"]
_10, #[derive(Clone, Copy, Debug, PartialEq)]
#[doc = r" Reserved"] #[repr(u8)]
_Reserved(u8), pub enum MODE_A {
} #[doc = "0: 8-bit conversion."]
impl MODER { _00 = 0,
#[doc = r" Value of the field as raw bits"] #[doc = "1: 12-bit conversion."]
#[inline] _01 = 1,
pub fn bits(&self) -> u8 { #[doc = "2: 10-bit conversion."]
match *self { _10 = 2,
MODER::_00 => 0, }
MODER::_01 => 1, impl From<MODE_A> for u8 {
MODER::_10 => 2, #[inline(always)]
MODER::_Reserved(bits) => bits, fn from(variant: MODE_A) -> Self {
} variant as _
} }
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = "Reader of field `MODE`"]
#[inline] pub type MODE_R = crate::R<u8, MODE_A>;
pub fn _from(value: u8) -> MODER { impl MODE_R {
match value { #[doc = r"Get enumerated values variant"]
0 => MODER::_00, #[inline(always)]
1 => MODER::_01, pub fn variant(&self) -> crate::Variant<u8, MODE_A> {
2 => MODER::_10, use crate::Variant::*;
i => MODER::_Reserved(i), match self.bits {
} 0 => Val(MODE_A::_00),
} 1 => Val(MODE_A::_01),
#[doc = "Checks if the value of the field is `_00`"] 2 => Val(MODE_A::_10),
#[inline] i => Res(i),
pub fn is_00(&self) -> bool { }
*self == MODER::_00 }
} #[doc = "Checks if the value of the field is `_00`"]
#[doc = "Checks if the value of the field is `_01`"] #[inline(always)]
#[inline] pub fn is_00(&self) -> bool {
pub fn is_01(&self) -> bool { *self == MODE_A::_00
*self == MODER::_01 }
} #[doc = "Checks if the value of the field is `_01`"]
#[doc = "Checks if the value of the field is `_10`"] #[inline(always)]
#[inline] pub fn is_01(&self) -> bool {
pub fn is_10(&self) -> bool { *self == MODE_A::_01
*self == MODER::_10 }
} #[doc = "Checks if the value of the field is `_10`"]
} #[inline(always)]
#[doc = "Possible values of the field `ADIV`"] pub fn is_10(&self) -> bool {
#[derive(Clone, Copy, Debug, PartialEq)] *self == MODE_A::_10
pub enum ADIVR { }
#[doc = "The divide ratio is 1 and the clock rate is input clock."] }
_00, #[doc = "Write proxy for field `MODE`"]
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."] pub struct MODE_W<'a> {
_01, w: &'a mut W,
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."] }
_10, impl<'a> MODE_W<'a> {
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."] #[doc = r"Writes `variant` to the field"]
_11, #[inline(always)]
} pub fn variant(self, variant: MODE_A) -> &'a mut W {
impl ADIVR { unsafe { self.bits(variant.into()) }
#[doc = r" Value of the field as raw bits"] }
#[inline] #[doc = "8-bit conversion."]
pub fn bits(&self) -> u8 { #[inline(always)]
match *self { pub fn _00(self) -> &'a mut W {
ADIVR::_00 => 0, self.variant(MODE_A::_00)
ADIVR::_01 => 1, }
ADIVR::_10 => 2, #[doc = "12-bit conversion."]
ADIVR::_11 => 3, #[inline(always)]
} pub fn _01(self) -> &'a mut W {
} self.variant(MODE_A::_01)
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = "10-bit conversion."]
#[inline] #[inline(always)]
pub fn _from(value: u8) -> ADIVR { pub fn _10(self) -> &'a mut W {
match value { self.variant(MODE_A::_10)
0 => ADIVR::_00, }
1 => ADIVR::_01, #[doc = r"Writes raw bits to the field"]
2 => ADIVR::_10, #[inline(always)]
3 => ADIVR::_11, pub unsafe fn bits(self, value: u8) -> &'a mut W {
_ => unreachable!(), self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
} self.w
} }
#[doc = "Checks if the value of the field is `_00`"] }
#[inline] #[doc = "Clock Divide Select\n\nValue on reset: 0"]
pub fn is_00(&self) -> bool { #[derive(Clone, Copy, Debug, PartialEq)]
*self == ADIVR::_00 #[repr(u8)]
} pub enum ADIV_A {
#[doc = "Checks if the value of the field is `_01`"] #[doc = "0: The divide ratio is 1 and the clock rate is input clock."]
#[inline] _00 = 0,
pub fn is_01(&self) -> bool { #[doc = "1: The divide ratio is 2 and the clock rate is (input clock)/2."]
*self == ADIVR::_01 _01 = 1,
} #[doc = "2: The divide ratio is 4 and the clock rate is (input clock)/4."]
#[doc = "Checks if the value of the field is `_10`"] _10 = 2,
#[inline] #[doc = "3: The divide ratio is 8 and the clock rate is (input clock)/8."]
pub fn is_10(&self) -> bool { _11 = 3,
*self == ADIVR::_10 }
} impl From<ADIV_A> for u8 {
#[doc = "Checks if the value of the field is `_11`"] #[inline(always)]
#[inline] fn from(variant: ADIV_A) -> Self {
pub fn is_11(&self) -> bool { variant as _
*self == ADIVR::_11 }
} }
} #[doc = "Reader of field `ADIV`"]
#[doc = "Values that can be written to the field `ADICLK`"] pub type ADIV_R = crate::R<u8, ADIV_A>;
pub enum ADICLKW { impl ADIV_R {
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"] #[doc = r"Get enumerated values variant"]
_00, #[inline(always)]
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"] pub fn variant(&self) -> ADIV_A {
_01, match self.bits {
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"] 0 => ADIV_A::_00,
_10, 1 => ADIV_A::_01,
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"] 2 => ADIV_A::_10,
_11, 3 => ADIV_A::_11,
} _ => unreachable!(),
impl ADICLKW { }
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = "Checks if the value of the field is `_00`"]
#[inline] #[inline(always)]
pub fn _bits(&self) -> u8 { pub fn is_00(&self) -> bool {
match *self { *self == ADIV_A::_00
ADICLKW::_00 => 0, }
ADICLKW::_01 => 1, #[doc = "Checks if the value of the field is `_01`"]
ADICLKW::_10 => 2, #[inline(always)]
ADICLKW::_11 => 3, pub fn is_01(&self) -> bool {
} *self == ADIV_A::_01
} }
} #[doc = "Checks if the value of the field is `_10`"]
#[doc = r" Proxy"] #[inline(always)]
pub struct _ADICLKW<'a> { pub fn is_10(&self) -> bool {
w: &'a mut W, *self == ADIV_A::_10
} }
impl<'a> _ADICLKW<'a> { #[doc = "Checks if the value of the field is `_11`"]
#[doc = r" Writes `variant` to the field"] #[inline(always)]
#[inline] pub fn is_11(&self) -> bool {
pub fn variant(self, variant: ADICLKW) -> &'a mut W { *self == ADIV_A::_11
{ }
self.bits(variant._bits()) }
} #[doc = "Write proxy for field `ADIV`"]
} pub struct ADIV_W<'a> {
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"] w: &'a mut W,
#[inline] }
pub fn _00(self) -> &'a mut W { impl<'a> ADIV_W<'a> {
self.variant(ADICLKW::_00) #[doc = r"Writes `variant` to the field"]
} #[inline(always)]
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"] pub fn variant(self, variant: ADIV_A) -> &'a mut W {
#[inline] {
pub fn _01(self) -> &'a mut W { self.bits(variant.into())
self.variant(ADICLKW::_01) }
} }
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"] #[doc = "The divide ratio is 1 and the clock rate is input clock."]
#[inline] #[inline(always)]
pub fn _10(self) -> &'a mut W { pub fn _00(self) -> &'a mut W {
self.variant(ADICLKW::_10) self.variant(ADIV_A::_00)
} }
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"] #[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
#[inline] #[inline(always)]
pub fn _11(self) -> &'a mut W { pub fn _01(self) -> &'a mut W {
self.variant(ADICLKW::_11) self.variant(ADIV_A::_01)
} }
#[doc = r" Writes raw bits to the field"] #[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
#[inline] #[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W { pub fn _10(self) -> &'a mut W {
const MASK: u8 = 3; self.variant(ADIV_A::_10)
const OFFSET: u8 = 0; }
self.w.bits &= !((MASK as u32) << OFFSET); #[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
self.w.bits |= ((value & MASK) as u32) << OFFSET; #[inline(always)]
self.w pub fn _11(self) -> &'a mut W {
} self.variant(ADIV_A::_11)
} }
#[doc = "Values that can be written to the field `MODE`"] #[doc = r"Writes raw bits to the field"]
pub enum MODEW { #[inline(always)]
#[doc = "8-bit conversion."] pub fn bits(self, value: u8) -> &'a mut W {
_00, self.w.bits = (self.w.bits & !(0x03 << 5)) | (((value as u32) & 0x03) << 5);
#[doc = "12-bit conversion."] self.w
_01, }
#[doc = "10-bit conversion."] }
_10, #[doc = "Write proxy for field `CLRLTRG`"]
} pub struct CLRLTRG_W<'a> {
impl MODEW { w: &'a mut W,
#[allow(missing_docs)] }
#[doc(hidden)] impl<'a> CLRLTRG_W<'a> {
#[inline] #[doc = r"Sets the field bit"]
pub fn _bits(&self) -> u8 { #[inline(always)]
match *self { pub fn set_bit(self) -> &'a mut W {
MODEW::_00 => 0, self.bit(true)
MODEW::_01 => 1, }
MODEW::_10 => 2, #[doc = r"Clears the field bit"]
} #[inline(always)]
} pub fn clear_bit(self) -> &'a mut W {
} self.bit(false)
#[doc = r" Proxy"] }
pub struct _MODEW<'a> { #[doc = r"Writes raw bits to the field"]
w: &'a mut W, #[inline(always)]
} pub fn bit(self, value: bool) -> &'a mut W {
impl<'a> _MODEW<'a> { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
#[doc = r" Writes `variant` to the field"] self.w
#[inline] }
pub fn variant(self, variant: MODEW) -> &'a mut W { }
unsafe { self.bits(variant._bits()) } impl R {
} #[doc = "Bits 0:1 - Input Clock Select"]
#[doc = "8-bit conversion."] #[inline(always)]
#[inline] pub fn adiclk(&self) -> ADICLK_R {
pub fn _00(self) -> &'a mut W { ADICLK_R::new((self.bits & 0x03) as u8)
self.variant(MODEW::_00) }
} #[doc = "Bits 2:3 - Conversion mode selection"]
#[doc = "12-bit conversion."] #[inline(always)]
#[inline] pub fn mode(&self) -> MODE_R {
pub fn _01(self) -> &'a mut W { MODE_R::new(((self.bits >> 2) & 0x03) as u8)
self.variant(MODEW::_01) }
} #[doc = "Bits 5:6 - Clock Divide Select"]
#[doc = "10-bit conversion."] #[inline(always)]
#[inline] pub fn adiv(&self) -> ADIV_R {
pub fn _10(self) -> &'a mut W { ADIV_R::new(((self.bits >> 5) & 0x03) as u8)
self.variant(MODEW::_10) }
} }
#[doc = r" Writes raw bits to the field"] impl W {
#[inline] #[doc = "Bits 0:1 - Input Clock Select"]
pub unsafe fn bits(self, value: u8) -> &'a mut W { #[inline(always)]
const MASK: u8 = 3; pub fn adiclk(&mut self) -> ADICLK_W {
const OFFSET: u8 = 2; ADICLK_W { w: self }
self.w.bits &= !((MASK as u32) << OFFSET); }
self.w.bits |= ((value & MASK) as u32) << OFFSET; #[doc = "Bits 2:3 - Conversion mode selection"]
self.w #[inline(always)]
} pub fn mode(&mut self) -> MODE_W {
} MODE_W { w: self }
#[doc = "Values that can be written to the field `ADIV`"] }
pub enum ADIVW { #[doc = "Bits 5:6 - Clock Divide Select"]
#[doc = "The divide ratio is 1 and the clock rate is input clock."] #[inline(always)]
_00, pub fn adiv(&mut self) -> ADIV_W {
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."] ADIV_W { w: self }
_01, }
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."] #[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
_10, #[inline(always)]
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."] pub fn clrltrg(&mut self) -> CLRLTRG_W {
_11, CLRLTRG_W { w: self }
} }
impl ADIVW { }
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
ADIVW::_00 => 0,
ADIVW::_01 => 1,
ADIVW::_10 => 2,
ADIVW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _ADIVW<'a> {
w: &'a mut W,
}
impl<'a> _ADIVW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADIVW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(ADIVW::_00)
}
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(ADIVW::_01)
}
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(ADIVW::_10)
}
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(ADIVW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CLRLTRGW<'a> {
w: &'a mut W,
}
impl<'a> _CLRLTRGW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Input Clock Select"]
#[inline]
pub fn adiclk(&self) -> ADICLKR {
ADICLKR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Conversion mode selection"]
#[inline]
pub fn mode(&self) -> MODER {
MODER::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 5:6 - Clock Divide Select"]
#[inline]
pub fn adiv(&self) -> ADIVR {
ADIVR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Input Clock Select"]
#[inline]
pub fn adiclk(&mut self) -> _ADICLKW {
_ADICLKW { w: self }
}
#[doc = "Bits 2:3 - Conversion mode selection"]
#[inline]
pub fn mode(&mut self) -> _MODEW {
_MODEW { w: self }
}
#[doc = "Bits 5:6 - Clock Divide Select"]
#[inline]
pub fn adiv(&mut self) -> _ADIVW {
_ADIVW { w: self }
}
#[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
#[inline]
pub fn clrltrg(&mut self) -> _CLRLTRGW {
_CLRLTRGW { w: self }
}
}

143
src/adc0/cfg2.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CFG2"]
pub struct R { pub type R = crate::R<u32, super::CFG2>;
bits: u32, #[doc = "Writer for register CFG2"]
} pub type W = crate::W<u32, super::CFG2>;
#[doc = r" Value to write to the register"] #[doc = "Register CFG2 `reset()`'s with value 0x0c"]
pub struct W { impl crate::ResetValue for super::CFG2 {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CFG2 { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x0c
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `SMPLTS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type SMPLTS_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `SMPLTS`"]
let bits = self.register.get(); pub struct SMPLTS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> SMPLTS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:7 - Sample Time Select"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn smplts(&self) -> SMPLTS_R {
F: FnOnce(&mut W) -> &mut W, SMPLTS_R::new((self.bits & 0xff) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:7 - Sample Time Select"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn smplts(&mut self) -> SMPLTS_W {
#[inline] SMPLTS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct SMPLTSR {
bits: u8,
}
impl SMPLTSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SMPLTSW<'a> {
w: &'a mut W,
}
impl<'a> _SMPLTSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Sample Time Select"]
#[inline]
pub fn smplts(&self) -> SMPLTSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SMPLTSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 12 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Sample Time Select"]
#[inline]
pub fn smplts(&mut self) -> _SMPLTSW {
_SMPLTSW { w: self }
}
}

143
src/adc0/clp0.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLP0"]
pub struct R { pub type R = crate::R<u32, super::CLP0>;
bits: u32, #[doc = "Writer for register CLP0"]
} pub type W = crate::W<u32, super::CLP0>;
#[doc = r" Value to write to the register"] #[doc = "Register CLP0 `reset()`'s with value 0x2e"]
pub struct W { impl crate::ResetValue for super::CLP0 {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLP0 { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x2e
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLP0`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLP0_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `CLP0`"]
let bits = self.register.get(); pub struct CLP0_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLP0_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:7 - Calibration Value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clp0(&self) -> CLP0_R {
F: FnOnce(&mut W) -> &mut W, CLP0_R::new((self.bits & 0xff) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:7 - Calibration Value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clp0(&mut self) -> CLP0_W {
#[inline] CLP0_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLP0R {
bits: u8,
}
impl CLP0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP0W<'a> {
w: &'a mut W,
}
impl<'a> _CLP0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Calibration Value"]
#[inline]
pub fn clp0(&self) -> CLP0R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 46 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Calibration Value"]
#[inline]
pub fn clp0(&mut self) -> _CLP0W {
_CLP0W { w: self }
}
}

143
src/adc0/clp0_ofs.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLP0_OFS"]
pub struct R { pub type R = crate::R<u32, super::CLP0_OFS>;
bits: u32, #[doc = "Writer for register CLP0_OFS"]
} pub type W = crate::W<u32, super::CLP0_OFS>;
#[doc = r" Value to write to the register"] #[doc = "Register CLP0_OFS `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::CLP0_OFS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLP0_OFS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLP0_OFS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLP0_OFS_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `CLP0_OFS`"]
let bits = self.register.get(); pub struct CLP0_OFS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLP0_OFS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:3 - CLP0 Offset"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clp0_ofs(&self) -> CLP0_OFS_R {
F: FnOnce(&mut W) -> &mut W, CLP0_OFS_R::new((self.bits & 0x0f) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:3 - CLP0 Offset"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clp0_ofs(&mut self) -> CLP0_OFS_W {
#[inline] CLP0_OFS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLP0_OFSR {
bits: u8,
}
impl CLP0_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP0_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP0_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP0 Offset"]
#[inline]
pub fn clp0_ofs(&self) -> CLP0_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP0_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP0 Offset"]
#[inline]
pub fn clp0_ofs(&mut self) -> _CLP0_OFSW {
_CLP0_OFSW { w: self }
}
}

143
src/adc0/clp1.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLP1"]
pub struct R { pub type R = crate::R<u32, super::CLP1>;
bits: u32, #[doc = "Writer for register CLP1"]
} pub type W = crate::W<u32, super::CLP1>;
#[doc = r" Value to write to the register"] #[doc = "Register CLP1 `reset()`'s with value 0x5c"]
pub struct W { impl crate::ResetValue for super::CLP1 {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLP1 { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x5c
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLP1`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLP1_R = crate::R<u16, u16>;
{ #[doc = "Write proxy for field `CLP1`"]
let bits = self.register.get(); pub struct CLP1_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLP1_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u16) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x01ff) | ((value as u32) & 0x01ff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:8 - Calibration Value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clp1(&self) -> CLP1_R {
F: FnOnce(&mut W) -> &mut W, CLP1_R::new((self.bits & 0x01ff) as u16)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:8 - Calibration Value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clp1(&mut self) -> CLP1_W {
#[inline] CLP1_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLP1R {
bits: u16,
}
impl CLP1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP1W<'a> {
w: &'a mut W,
}
impl<'a> _CLP1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 511;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:8 - Calibration Value"]
#[inline]
pub fn clp1(&self) -> CLP1R {
let bits = {
const MASK: u16 = 511;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP1R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 92 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:8 - Calibration Value"]
#[inline]
pub fn clp1(&mut self) -> _CLP1W {
_CLP1W { w: self }
}
}

143
src/adc0/clp1_ofs.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLP1_OFS"]
pub struct R { pub type R = crate::R<u32, super::CLP1_OFS>;
bits: u32, #[doc = "Writer for register CLP1_OFS"]
} pub type W = crate::W<u32, super::CLP1_OFS>;
#[doc = r" Value to write to the register"] #[doc = "Register CLP1_OFS `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::CLP1_OFS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLP1_OFS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLP1_OFS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLP1_OFS_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `CLP1_OFS`"]
let bits = self.register.get(); pub struct CLP1_OFS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLP1_OFS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:3 - CLP1 Offset"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clp1_ofs(&self) -> CLP1_OFS_R {
F: FnOnce(&mut W) -> &mut W, CLP1_OFS_R::new((self.bits & 0x0f) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:3 - CLP1 Offset"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clp1_ofs(&mut self) -> CLP1_OFS_W {
#[inline] CLP1_OFS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLP1_OFSR {
bits: u8,
}
impl CLP1_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP1_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP1_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP1 Offset"]
#[inline]
pub fn clp1_ofs(&self) -> CLP1_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP1_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP1 Offset"]
#[inline]
pub fn clp1_ofs(&mut self) -> _CLP1_OFSW {
_CLP1_OFSW { w: self }
}
}

143
src/adc0/clp2.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLP2"]
pub struct R { pub type R = crate::R<u32, super::CLP2>;
bits: u32, #[doc = "Writer for register CLP2"]
} pub type W = crate::W<u32, super::CLP2>;
#[doc = r" Value to write to the register"] #[doc = "Register CLP2 `reset()`'s with value 0xb8"]
pub struct W { impl crate::ResetValue for super::CLP2 {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLP2 { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0xb8
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLP2`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLP2_R = crate::R<u16, u16>;
{ #[doc = "Write proxy for field `CLP2`"]
let bits = self.register.get(); pub struct CLP2_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLP2_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u16) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:9 - Calibration Value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clp2(&self) -> CLP2_R {
F: FnOnce(&mut W) -> &mut W, CLP2_R::new((self.bits & 0x03ff) as u16)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:9 - Calibration Value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clp2(&mut self) -> CLP2_W {
#[inline] CLP2_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLP2R {
bits: u16,
}
impl CLP2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP2W<'a> {
w: &'a mut W,
}
impl<'a> _CLP2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp2(&self) -> CLP2R {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP2R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 184 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp2(&mut self) -> _CLP2W {
_CLP2W { w: self }
}
}

143
src/adc0/clp2_ofs.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLP2_OFS"]
pub struct R { pub type R = crate::R<u32, super::CLP2_OFS>;
bits: u32, #[doc = "Writer for register CLP2_OFS"]
} pub type W = crate::W<u32, super::CLP2_OFS>;
#[doc = r" Value to write to the register"] #[doc = "Register CLP2_OFS `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::CLP2_OFS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLP2_OFS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLP2_OFS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLP2_OFS_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `CLP2_OFS`"]
let bits = self.register.get(); pub struct CLP2_OFS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLP2_OFS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:3 - CLP2 Offset"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clp2_ofs(&self) -> CLP2_OFS_R {
F: FnOnce(&mut W) -> &mut W, CLP2_OFS_R::new((self.bits & 0x0f) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:3 - CLP2 Offset"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clp2_ofs(&mut self) -> CLP2_OFS_W {
#[inline] CLP2_OFS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLP2_OFSR {
bits: u8,
}
impl CLP2_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP2_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP2_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP2 Offset"]
#[inline]
pub fn clp2_ofs(&self) -> CLP2_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP2_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP2 Offset"]
#[inline]
pub fn clp2_ofs(&mut self) -> _CLP2_OFSW {
_CLP2_OFSW { w: self }
}
}

143
src/adc0/clp3.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLP3"]
pub struct R { pub type R = crate::R<u32, super::CLP3>;
bits: u32, #[doc = "Writer for register CLP3"]
} pub type W = crate::W<u32, super::CLP3>;
#[doc = r" Value to write to the register"] #[doc = "Register CLP3 `reset()`'s with value 0x0180"]
pub struct W { impl crate::ResetValue for super::CLP3 {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLP3 { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x0180
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLP3`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLP3_R = crate::R<u16, u16>;
{ #[doc = "Write proxy for field `CLP3`"]
let bits = self.register.get(); pub struct CLP3_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLP3_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u16) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:9 - Calibration Value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clp3(&self) -> CLP3_R {
F: FnOnce(&mut W) -> &mut W, CLP3_R::new((self.bits & 0x03ff) as u16)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:9 - Calibration Value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clp3(&mut self) -> CLP3_W {
#[inline] CLP3_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLP3R {
bits: u16,
}
impl CLP3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP3W<'a> {
w: &'a mut W,
}
impl<'a> _CLP3W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp3(&self) -> CLP3R {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP3R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 384 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp3(&mut self) -> _CLP3W {
_CLP3W { w: self }
}
}

143
src/adc0/clp3_ofs.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLP3_OFS"]
pub struct R { pub type R = crate::R<u32, super::CLP3_OFS>;
bits: u32, #[doc = "Writer for register CLP3_OFS"]
} pub type W = crate::W<u32, super::CLP3_OFS>;
#[doc = r" Value to write to the register"] #[doc = "Register CLP3_OFS `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::CLP3_OFS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLP3_OFS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLP3_OFS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLP3_OFS_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `CLP3_OFS`"]
let bits = self.register.get(); pub struct CLP3_OFS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLP3_OFS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:3 - CLP3 Offset"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clp3_ofs(&self) -> CLP3_OFS_R {
F: FnOnce(&mut W) -> &mut W, CLP3_OFS_R::new((self.bits & 0x0f) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:3 - CLP3 Offset"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clp3_ofs(&mut self) -> CLP3_OFS_W {
#[inline] CLP3_OFS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLP3_OFSR {
bits: u8,
}
impl CLP3_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP3_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP3_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP3 Offset"]
#[inline]
pub fn clp3_ofs(&self) -> CLP3_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP3_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP3 Offset"]
#[inline]
pub fn clp3_ofs(&mut self) -> _CLP3_OFSW {
_CLP3_OFSW { w: self }
}
}

143
src/adc0/clp9.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLP9"]
pub struct R { pub type R = crate::R<u32, super::CLP9>;
bits: u32, #[doc = "Writer for register CLP9"]
} pub type W = crate::W<u32, super::CLP9>;
#[doc = r" Value to write to the register"] #[doc = "Register CLP9 `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::CLP9 {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLP9 { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLP9`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLP9_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `CLP9`"]
let bits = self.register.get(); pub struct CLP9_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLP9_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:6 - Calibration Value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clp9(&self) -> CLP9_R {
F: FnOnce(&mut W) -> &mut W, CLP9_R::new((self.bits & 0x7f) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:6 - Calibration Value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clp9(&mut self) -> CLP9_W {
#[inline] CLP9_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLP9R {
bits: u8,
}
impl CLP9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP9W<'a> {
w: &'a mut W,
}
impl<'a> _CLP9W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clp9(&self) -> CLP9R {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP9R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clp9(&mut self) -> _CLP9W {
_CLP9W { w: self }
}
}

143
src/adc0/clp9_ofs.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLP9_OFS"]
pub struct R { pub type R = crate::R<u32, super::CLP9_OFS>;
bits: u32, #[doc = "Writer for register CLP9_OFS"]
} pub type W = crate::W<u32, super::CLP9_OFS>;
#[doc = r" Value to write to the register"] #[doc = "Register CLP9_OFS `reset()`'s with value 0x0240"]
pub struct W { impl crate::ResetValue for super::CLP9_OFS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLP9_OFS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x0240
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLP9_OFS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLP9_OFS_R = crate::R<u16, u16>;
{ #[doc = "Write proxy for field `CLP9_OFS`"]
let bits = self.register.get(); pub struct CLP9_OFS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLP9_OFS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u16) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:11 - CLP9 Offset"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clp9_ofs(&self) -> CLP9_OFS_R {
F: FnOnce(&mut W) -> &mut W, CLP9_OFS_R::new((self.bits & 0x0fff) as u16)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:11 - CLP9 Offset"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clp9_ofs(&mut self) -> CLP9_OFS_W {
#[inline] CLP9_OFS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLP9_OFSR {
bits: u16,
}
impl CLP9_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP9_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP9_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - CLP9 Offset"]
#[inline]
pub fn clp9_ofs(&self) -> CLP9_OFSR {
let bits = {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP9_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 576 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:11 - CLP9 Offset"]
#[inline]
pub fn clp9_ofs(&mut self) -> _CLP9_OFSW {
_CLP9_OFSW { w: self }
}
}

143
src/adc0/clps.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLPS"]
pub struct R { pub type R = crate::R<u32, super::CLPS>;
bits: u32, #[doc = "Writer for register CLPS"]
} pub type W = crate::W<u32, super::CLPS>;
#[doc = r" Value to write to the register"] #[doc = "Register CLPS `reset()`'s with value 0x2e"]
pub struct W { impl crate::ResetValue for super::CLPS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLPS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x2e
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLPS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLPS_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `CLPS`"]
let bits = self.register.get(); pub struct CLPS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLPS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:6 - Calibration Value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clps(&self) -> CLPS_R {
F: FnOnce(&mut W) -> &mut W, CLPS_R::new((self.bits & 0x7f) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:6 - Calibration Value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clps(&mut self) -> CLPS_W {
#[inline] CLPS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLPSR {
bits: u8,
}
impl CLPSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPSW<'a> {
w: &'a mut W,
}
impl<'a> _CLPSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clps(&self) -> CLPSR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLPSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 46 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clps(&mut self) -> _CLPSW {
_CLPSW { w: self }
}
}

143
src/adc0/clps_ofs.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLPS_OFS"]
pub struct R { pub type R = crate::R<u32, super::CLPS_OFS>;
bits: u32, #[doc = "Writer for register CLPS_OFS"]
} pub type W = crate::W<u32, super::CLPS_OFS>;
#[doc = r" Value to write to the register"] #[doc = "Register CLPS_OFS `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::CLPS_OFS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLPS_OFS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLPS_OFS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLPS_OFS_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `CLPS_OFS`"]
let bits = self.register.get(); pub struct CLPS_OFS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLPS_OFS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:3 - CLPS Offset"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clps_ofs(&self) -> CLPS_OFS_R {
F: FnOnce(&mut W) -> &mut W, CLPS_OFS_R::new((self.bits & 0x0f) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:3 - CLPS Offset"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clps_ofs(&mut self) -> CLPS_OFS_W {
#[inline] CLPS_OFS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLPS_OFSR {
bits: u8,
}
impl CLPS_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPS_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLPS_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLPS Offset"]
#[inline]
pub fn clps_ofs(&self) -> CLPS_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLPS_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLPS Offset"]
#[inline]
pub fn clps_ofs(&mut self) -> _CLPS_OFSW {
_CLPS_OFSW { w: self }
}
}

143
src/adc0/clpx.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLPX"]
pub struct R { pub type R = crate::R<u32, super::CLPX>;
bits: u32, #[doc = "Writer for register CLPX"]
} pub type W = crate::W<u32, super::CLPX>;
#[doc = r" Value to write to the register"] #[doc = "Register CLPX `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::CLPX {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLPX { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLPX`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLPX_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `CLPX`"]
let bits = self.register.get(); pub struct CLPX_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLPX_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:6 - Calibration Value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clpx(&self) -> CLPX_R {
F: FnOnce(&mut W) -> &mut W, CLPX_R::new((self.bits & 0x7f) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:6 - Calibration Value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clpx(&mut self) -> CLPX_W {
#[inline] CLPX_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLPXR {
bits: u8,
}
impl CLPXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPXW<'a> {
w: &'a mut W,
}
impl<'a> _CLPXW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clpx(&self) -> CLPXR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLPXR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clpx(&mut self) -> _CLPXW {
_CLPXW { w: self }
}
}

143
src/adc0/clpx_ofs.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CLPX_OFS"]
pub struct R { pub type R = crate::R<u32, super::CLPX_OFS>;
bits: u32, #[doc = "Writer for register CLPX_OFS"]
} pub type W = crate::W<u32, super::CLPX_OFS>;
#[doc = r" Value to write to the register"] #[doc = "Register CLPX_OFS `reset()`'s with value 0x0440"]
pub struct W { impl crate::ResetValue for super::CLPX_OFS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CLPX_OFS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x0440
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CLPX_OFS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CLPX_OFS_R = crate::R<u16, u16>;
{ #[doc = "Write proxy for field `CLPX_OFS`"]
let bits = self.register.get(); pub struct CLPX_OFS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CLPX_OFS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u16) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:11 - CLPX Offset"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn clpx_ofs(&self) -> CLPX_OFS_R {
F: FnOnce(&mut W) -> &mut W, CLPX_OFS_R::new((self.bits & 0x0fff) as u16)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:11 - CLPX Offset"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn clpx_ofs(&mut self) -> CLPX_OFS_W {
#[inline] CLPX_OFS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CLPX_OFSR {
bits: u16,
}
impl CLPX_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPX_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLPX_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - CLPX Offset"]
#[inline]
pub fn clpx_ofs(&self) -> CLPX_OFSR {
let bits = {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLPX_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 1088 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:11 - CLPX Offset"]
#[inline]
pub fn clpx_ofs(&mut self) -> _CLPX_OFSW {
_CLPX_OFSW { w: self }
}
}

143
src/adc0/cv.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CV%s"]
pub struct R { pub type R = crate::R<u32, super::CV>;
bits: u32, #[doc = "Writer for register CV%s"]
} pub type W = crate::W<u32, super::CV>;
#[doc = r" Value to write to the register"] #[doc = "Register CV%s `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::CV {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CV { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `CV`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type CV_R = crate::R<u16, u16>;
{ #[doc = "Write proxy for field `CV`"]
let bits = self.register.get(); pub struct CV_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> CV_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u16) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:15 - Compare Value."]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn cv(&self) -> CV_R {
F: FnOnce(&mut W) -> &mut W, CV_R::new((self.bits & 0xffff) as u16)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:15 - Compare Value."]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn cv(&mut self) -> CV_W {
#[inline] CV_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct CVR {
bits: u16,
}
impl CVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CVW<'a> {
w: &'a mut W,
}
impl<'a> _CVW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Compare Value."]
#[inline]
pub fn cv(&self) -> CVR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CVR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Compare Value."]
#[inline]
pub fn cv(&mut self) -> _CVW {
_CVW { w: self }
}
}

143
src/adc0/g.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register G"]
pub struct R { pub type R = crate::R<u32, super::G>;
bits: u32, #[doc = "Writer for register G"]
} pub type W = crate::W<u32, super::G>;
#[doc = r" Value to write to the register"] #[doc = "Register G `reset()`'s with value 0x02f0"]
pub struct W { impl crate::ResetValue for super::G {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::G { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x02f0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `G`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type G_R = crate::R<u16, u16>;
{ #[doc = "Write proxy for field `G`"]
let bits = self.register.get(); pub struct G_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> G_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u16) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x07ff) | ((value as u32) & 0x07ff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn g(&self) -> G_R {
F: FnOnce(&mut W) -> &mut W, G_R::new((self.bits & 0x07ff) as u16)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn g(&mut self) -> G_W {
#[inline] G_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct GR {
bits: u16,
}
impl GR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _GW<'a> {
w: &'a mut W,
}
impl<'a> _GW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 2047;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
#[inline]
pub fn g(&self) -> GR {
let bits = {
const MASK: u16 = 2047;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
GR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 752 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
#[inline]
pub fn g(&mut self) -> _GW {
_GW { w: self }
}
}

143
src/adc0/ofs.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register OFS"]
pub struct R { pub type R = crate::R<u32, super::OFS>;
bits: u32, #[doc = "Writer for register OFS"]
} pub type W = crate::W<u32, super::OFS>;
#[doc = r" Value to write to the register"] #[doc = "Register OFS `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::OFS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::OFS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `OFS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type OFS_R = crate::R<u16, u16>;
{ #[doc = "Write proxy for field `OFS`"]
let bits = self.register.get(); pub struct OFS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> OFS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u16) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:15 - Offset Error Correction Value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn ofs(&self) -> OFS_R {
F: FnOnce(&mut W) -> &mut W, OFS_R::new((self.bits & 0xffff) as u16)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:15 - Offset Error Correction Value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn ofs(&mut self) -> OFS_W {
#[inline] OFS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct OFSR {
bits: u16,
}
impl OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _OFSW<'a> {
w: &'a mut W,
}
impl<'a> _OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Offset Error Correction Value"]
#[inline]
pub fn ofs(&self) -> OFSR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Offset Error Correction Value"]
#[inline]
pub fn ofs(&mut self) -> _OFSW {
_OFSW { w: self }
}
}

50
src/adc0/r.rs
View File

@ -1,39 +1,11 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register R%s"]
pub struct R { pub type R = crate::R<u32, super::R>;
bits: u32, #[doc = "Reader of field `D`"]
} pub type D_R = crate::R<u16, u16>;
impl super::R { impl R {
#[doc = r" Reads the contents of the register"] #[doc = "Bits 0:11 - Data result"]
#[inline] #[inline(always)]
pub fn read(&self) -> R { pub fn d(&self) -> D_R {
R { bits: self.register.get() } D_R::new((self.bits & 0x0fff) as u16)
} }
} }
#[doc = r" Value of the field"]
pub struct DR {
bits: u16,
}
impl DR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - Data result"]
#[inline]
pub fn d(&self) -> DR {
let bits = {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DR { bits }
}
}

1308
src/adc0/sc1.rs
View File

File diff suppressed because it is too large Load Diff

1052
src/adc0/sc2.rs
View File

File diff suppressed because it is too large Load Diff

818
src/adc0/sc3.rs
View File

@ -1,495 +1,323 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register SC3"]
pub struct R { pub type R = crate::R<u32, super::SC3>;
bits: u32, #[doc = "Writer for register SC3"]
} pub type W = crate::W<u32, super::SC3>;
#[doc = r" Value to write to the register"] #[doc = "Register SC3 `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::SC3 {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::SC3 { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Hardware Average Select\n\nValue on reset: 0"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, #[derive(Clone, Copy, Debug, PartialEq)]
{ #[repr(u8)]
let bits = self.register.get(); pub enum AVGS_A {
let r = R { bits: bits }; #[doc = "0: 4 samples averaged."]
let mut w = W { bits: bits }; _00 = 0,
f(&r, &mut w); #[doc = "1: 8 samples averaged."]
self.register.set(w.bits); _01 = 1,
} #[doc = "2: 16 samples averaged."]
#[doc = r" Reads the contents of the register"] _10 = 2,
#[inline] #[doc = "3: 32 samples averaged."]
pub fn read(&self) -> R { _11 = 3,
R { bits: self.register.get() } }
} impl From<AVGS_A> for u8 {
#[doc = r" Writes to the register"] #[inline(always)]
#[inline] fn from(variant: AVGS_A) -> Self {
pub fn write<F>(&self, f: F) variant as _
where }
F: FnOnce(&mut W) -> &mut W, }
{ #[doc = "Reader of field `AVGS`"]
let mut w = W::reset_value(); pub type AVGS_R = crate::R<u8, AVGS_A>;
f(&mut w); impl AVGS_R {
self.register.set(w.bits); #[doc = r"Get enumerated values variant"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn variant(&self) -> AVGS_A {
#[inline] match self.bits {
pub fn reset(&self) { 0 => AVGS_A::_00,
self.write(|w| w) 1 => AVGS_A::_01,
} 2 => AVGS_A::_10,
} 3 => AVGS_A::_11,
#[doc = "Possible values of the field `AVGS`"] _ => unreachable!(),
#[derive(Clone, Copy, Debug, PartialEq)] }
pub enum AVGSR { }
#[doc = "4 samples averaged."] #[doc = "Checks if the value of the field is `_00`"]
_00, #[inline(always)]
#[doc = "8 samples averaged."] pub fn is_00(&self) -> bool {
_01, *self == AVGS_A::_00
#[doc = "16 samples averaged."] }
_10, #[doc = "Checks if the value of the field is `_01`"]
#[doc = "32 samples averaged."] #[inline(always)]
_11, pub fn is_01(&self) -> bool {
} *self == AVGS_A::_01
impl AVGSR { }
#[doc = r" Value of the field as raw bits"] #[doc = "Checks if the value of the field is `_10`"]
#[inline] #[inline(always)]
pub fn bits(&self) -> u8 { pub fn is_10(&self) -> bool {
match *self { *self == AVGS_A::_10
AVGSR::_00 => 0, }
AVGSR::_01 => 1, #[doc = "Checks if the value of the field is `_11`"]
AVGSR::_10 => 2, #[inline(always)]
AVGSR::_11 => 3, pub fn is_11(&self) -> bool {
} *self == AVGS_A::_11
} }
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = "Write proxy for field `AVGS`"]
#[inline] pub struct AVGS_W<'a> {
pub fn _from(value: u8) -> AVGSR { w: &'a mut W,
match value { }
0 => AVGSR::_00, impl<'a> AVGS_W<'a> {
1 => AVGSR::_01, #[doc = r"Writes `variant` to the field"]
2 => AVGSR::_10, #[inline(always)]
3 => AVGSR::_11, pub fn variant(self, variant: AVGS_A) -> &'a mut W {
_ => unreachable!(), {
} self.bits(variant.into())
} }
#[doc = "Checks if the value of the field is `_00`"] }
#[inline] #[doc = "4 samples averaged."]
pub fn is_00(&self) -> bool { #[inline(always)]
*self == AVGSR::_00 pub fn _00(self) -> &'a mut W {
} self.variant(AVGS_A::_00)
#[doc = "Checks if the value of the field is `_01`"] }
#[inline] #[doc = "8 samples averaged."]
pub fn is_01(&self) -> bool { #[inline(always)]
*self == AVGSR::_01 pub fn _01(self) -> &'a mut W {
} self.variant(AVGS_A::_01)
#[doc = "Checks if the value of the field is `_10`"] }
#[inline] #[doc = "16 samples averaged."]
pub fn is_10(&self) -> bool { #[inline(always)]
*self == AVGSR::_10 pub fn _10(self) -> &'a mut W {
} self.variant(AVGS_A::_10)
#[doc = "Checks if the value of the field is `_11`"] }
#[inline] #[doc = "32 samples averaged."]
pub fn is_11(&self) -> bool { #[inline(always)]
*self == AVGSR::_11 pub fn _11(self) -> &'a mut W {
} self.variant(AVGS_A::_11)
} }
#[doc = "Possible values of the field `AVGE`"] #[doc = r"Writes raw bits to the field"]
#[derive(Clone, Copy, Debug, PartialEq)] #[inline(always)]
pub enum AVGER { pub fn bits(self, value: u8) -> &'a mut W {
#[doc = "Hardware average function disabled."] self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
_0, self.w
#[doc = "Hardware average function enabled."] }
_1, }
} #[doc = "Hardware Average Enable\n\nValue on reset: 0"]
impl AVGER { #[derive(Clone, Copy, Debug, PartialEq)]
#[doc = r" Returns `true` if the bit is clear (0)"] pub enum AVGE_A {
#[inline] #[doc = "0: Hardware average function disabled."]
pub fn bit_is_clear(&self) -> bool { _0 = 0,
!self.bit() #[doc = "1: Hardware average function enabled."]
} _1 = 1,
#[doc = r" Returns `true` if the bit is set (1)"] }
#[inline] impl From<AVGE_A> for bool {
pub fn bit_is_set(&self) -> bool { #[inline(always)]
self.bit() fn from(variant: AVGE_A) -> Self {
} variant as u8 != 0
#[doc = r" Value of the field as raw bits"] }
#[inline] }
pub fn bit(&self) -> bool { #[doc = "Reader of field `AVGE`"]
match *self { pub type AVGE_R = crate::R<bool, AVGE_A>;
AVGER::_0 => false, impl AVGE_R {
AVGER::_1 => true, #[doc = r"Get enumerated values variant"]
} #[inline(always)]
} pub fn variant(&self) -> AVGE_A {
#[allow(missing_docs)] match self.bits {
#[doc(hidden)] false => AVGE_A::_0,
#[inline] true => AVGE_A::_1,
pub fn _from(value: bool) -> AVGER { }
match value { }
false => AVGER::_0, #[doc = "Checks if the value of the field is `_0`"]
true => AVGER::_1, #[inline(always)]
} pub fn is_0(&self) -> bool {
} *self == AVGE_A::_0
#[doc = "Checks if the value of the field is `_0`"] }
#[inline] #[doc = "Checks if the value of the field is `_1`"]
pub fn is_0(&self) -> bool { #[inline(always)]
*self == AVGER::_0 pub fn is_1(&self) -> bool {
} *self == AVGE_A::_1
#[doc = "Checks if the value of the field is `_1`"] }
#[inline] }
pub fn is_1(&self) -> bool { #[doc = "Write proxy for field `AVGE`"]
*self == AVGER::_1 pub struct AVGE_W<'a> {
} w: &'a mut W,
} }
#[doc = "Possible values of the field `ADCO`"] impl<'a> AVGE_W<'a> {
#[derive(Clone, Copy, Debug, PartialEq)] #[doc = r"Writes `variant` to the field"]
pub enum ADCOR { #[inline(always)]
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."] pub fn variant(self, variant: AVGE_A) -> &'a mut W {
_0, {
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."] self.bit(variant.into())
_1, }
} }
impl ADCOR { #[doc = "Hardware average function disabled."]
#[doc = r" Returns `true` if the bit is clear (0)"] #[inline(always)]
#[inline] pub fn _0(self) -> &'a mut W {
pub fn bit_is_clear(&self) -> bool { self.variant(AVGE_A::_0)
!self.bit() }
} #[doc = "Hardware average function enabled."]
#[doc = r" Returns `true` if the bit is set (1)"] #[inline(always)]
#[inline] pub fn _1(self) -> &'a mut W {
pub fn bit_is_set(&self) -> bool { self.variant(AVGE_A::_1)
self.bit() }
} #[doc = r"Sets the field bit"]
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] pub fn set_bit(self) -> &'a mut W {
pub fn bit(&self) -> bool { self.bit(true)
match *self { }
ADCOR::_0 => false, #[doc = r"Clears the field bit"]
ADCOR::_1 => true, #[inline(always)]
} pub fn clear_bit(self) -> &'a mut W {
} self.bit(false)
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn _from(value: bool) -> ADCOR { pub fn bit(self, value: bool) -> &'a mut W {
match value { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
false => ADCOR::_0, self.w
true => ADCOR::_1, }
} }
} #[doc = "Continuous Conversion Enable\n\nValue on reset: 0"]
#[doc = "Checks if the value of the field is `_0`"] #[derive(Clone, Copy, Debug, PartialEq)]
#[inline] pub enum ADCO_A {
pub fn is_0(&self) -> bool { #[doc = "0: One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
*self == ADCOR::_0 _0 = 0,
} #[doc = "1: Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
#[doc = "Checks if the value of the field is `_1`"] _1 = 1,
#[inline] }
pub fn is_1(&self) -> bool { impl From<ADCO_A> for bool {
*self == ADCOR::_1 #[inline(always)]
} fn from(variant: ADCO_A) -> Self {
} variant as u8 != 0
#[doc = r" Value of the field"] }
pub struct CALR { }
bits: bool, #[doc = "Reader of field `ADCO`"]
} pub type ADCO_R = crate::R<bool, ADCO_A>;
impl CALR { impl ADCO_R {
#[doc = r" Value of the field as raw bits"] #[doc = r"Get enumerated values variant"]
#[inline] #[inline(always)]
pub fn bit(&self) -> bool { pub fn variant(&self) -> ADCO_A {
self.bits match self.bits {
} false => ADCO_A::_0,
#[doc = r" Returns `true` if the bit is clear (0)"] true => ADCO_A::_1,
#[inline] }
pub fn bit_is_clear(&self) -> bool { }
!self.bit() #[doc = "Checks if the value of the field is `_0`"]
} #[inline(always)]
#[doc = r" Returns `true` if the bit is set (1)"] pub fn is_0(&self) -> bool {
#[inline] *self == ADCO_A::_0
pub fn bit_is_set(&self) -> bool { }
self.bit() #[doc = "Checks if the value of the field is `_1`"]
} #[inline(always)]
} pub fn is_1(&self) -> bool {
#[doc = "Values that can be written to the field `AVGS`"] *self == ADCO_A::_1
pub enum AVGSW { }
#[doc = "4 samples averaged."] }
_00, #[doc = "Write proxy for field `ADCO`"]
#[doc = "8 samples averaged."] pub struct ADCO_W<'a> {
_01, w: &'a mut W,
#[doc = "16 samples averaged."] }
_10, impl<'a> ADCO_W<'a> {
#[doc = "32 samples averaged."] #[doc = r"Writes `variant` to the field"]
_11, #[inline(always)]
} pub fn variant(self, variant: ADCO_A) -> &'a mut W {
impl AVGSW { {
#[allow(missing_docs)] self.bit(variant.into())
#[doc(hidden)] }
#[inline] }
pub fn _bits(&self) -> u8 { #[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
match *self { #[inline(always)]
AVGSW::_00 => 0, pub fn _0(self) -> &'a mut W {
AVGSW::_01 => 1, self.variant(ADCO_A::_0)
AVGSW::_10 => 2, }
AVGSW::_11 => 3, #[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
} #[inline(always)]
} pub fn _1(self) -> &'a mut W {
} self.variant(ADCO_A::_1)
#[doc = r" Proxy"] }
pub struct _AVGSW<'a> { #[doc = r"Sets the field bit"]
w: &'a mut W, #[inline(always)]
} pub fn set_bit(self) -> &'a mut W {
impl<'a> _AVGSW<'a> { self.bit(true)
#[doc = r" Writes `variant` to the field"] }
#[inline] #[doc = r"Clears the field bit"]
pub fn variant(self, variant: AVGSW) -> &'a mut W { #[inline(always)]
{ pub fn clear_bit(self) -> &'a mut W {
self.bits(variant._bits()) self.bit(false)
} }
} #[doc = r"Writes raw bits to the field"]
#[doc = "4 samples averaged."] #[inline(always)]
#[inline] pub fn bit(self, value: bool) -> &'a mut W {
pub fn _00(self) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
self.variant(AVGSW::_00) self.w
} }
#[doc = "8 samples averaged."] }
#[inline] #[doc = "Reader of field `CAL`"]
pub fn _01(self) -> &'a mut W { pub type CAL_R = crate::R<bool, bool>;
self.variant(AVGSW::_01) #[doc = "Write proxy for field `CAL`"]
} pub struct CAL_W<'a> {
#[doc = "16 samples averaged."] w: &'a mut W,
#[inline] }
pub fn _10(self) -> &'a mut W { impl<'a> CAL_W<'a> {
self.variant(AVGSW::_10) #[doc = r"Sets the field bit"]
} #[inline(always)]
#[doc = "32 samples averaged."] pub fn set_bit(self) -> &'a mut W {
#[inline] self.bit(true)
pub fn _11(self) -> &'a mut W { }
self.variant(AVGSW::_11) #[doc = r"Clears the field bit"]
} #[inline(always)]
#[doc = r" Writes raw bits to the field"] pub fn clear_bit(self) -> &'a mut W {
#[inline] self.bit(false)
pub fn bits(self, value: u8) -> &'a mut W { }
const MASK: u8 = 3; #[doc = r"Writes raw bits to the field"]
const OFFSET: u8 = 0; #[inline(always)]
self.w.bits &= !((MASK as u32) << OFFSET); pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
self.w self.w
} }
} }
#[doc = "Values that can be written to the field `AVGE`"] impl R {
pub enum AVGEW { #[doc = "Bits 0:1 - Hardware Average Select"]
#[doc = "Hardware average function disabled."] #[inline(always)]
_0, pub fn avgs(&self) -> AVGS_R {
#[doc = "Hardware average function enabled."] AVGS_R::new((self.bits & 0x03) as u8)
_1, }
} #[doc = "Bit 2 - Hardware Average Enable"]
impl AVGEW { #[inline(always)]
#[allow(missing_docs)] pub fn avge(&self) -> AVGE_R {
#[doc(hidden)] AVGE_R::new(((self.bits >> 2) & 0x01) != 0)
#[inline] }
pub fn _bits(&self) -> bool { #[doc = "Bit 3 - Continuous Conversion Enable"]
match *self { #[inline(always)]
AVGEW::_0 => false, pub fn adco(&self) -> ADCO_R {
AVGEW::_1 => true, ADCO_R::new(((self.bits >> 3) & 0x01) != 0)
} }
} #[doc = "Bit 7 - Calibration"]
} #[inline(always)]
#[doc = r" Proxy"] pub fn cal(&self) -> CAL_R {
pub struct _AVGEW<'a> { CAL_R::new(((self.bits >> 7) & 0x01) != 0)
w: &'a mut W, }
} }
impl<'a> _AVGEW<'a> { impl W {
#[doc = r" Writes `variant` to the field"] #[doc = "Bits 0:1 - Hardware Average Select"]
#[inline] #[inline(always)]
pub fn variant(self, variant: AVGEW) -> &'a mut W { pub fn avgs(&mut self) -> AVGS_W {
{ AVGS_W { w: self }
self.bit(variant._bits()) }
} #[doc = "Bit 2 - Hardware Average Enable"]
} #[inline(always)]
#[doc = "Hardware average function disabled."] pub fn avge(&mut self) -> AVGE_W {
#[inline] AVGE_W { w: self }
pub fn _0(self) -> &'a mut W { }
self.variant(AVGEW::_0) #[doc = "Bit 3 - Continuous Conversion Enable"]
} #[inline(always)]
#[doc = "Hardware average function enabled."] pub fn adco(&mut self) -> ADCO_W {
#[inline] ADCO_W { w: self }
pub fn _1(self) -> &'a mut W { }
self.variant(AVGEW::_1) #[doc = "Bit 7 - Calibration"]
} #[inline(always)]
#[doc = r" Sets the field bit"] pub fn cal(&mut self) -> CAL_W {
pub fn set_bit(self) -> &'a mut W { CAL_W { w: self }
self.bit(true) }
} }
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADCO`"]
pub enum ADCOW {
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
_0,
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
_1,
}
impl ADCOW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADCOW::_0 => false,
ADCOW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADCOW<'a> {
w: &'a mut W,
}
impl<'a> _ADCOW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADCOW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ADCOW::_0)
}
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ADCOW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CALW<'a> {
w: &'a mut W,
}
impl<'a> _CALW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Hardware Average Select"]
#[inline]
pub fn avgs(&self) -> AVGSR {
AVGSR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - Hardware Average Enable"]
#[inline]
pub fn avge(&self) -> AVGER {
AVGER::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Continuous Conversion Enable"]
#[inline]
pub fn adco(&self) -> ADCOR {
ADCOR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Calibration"]
#[inline]
pub fn cal(&self) -> CALR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CALR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Hardware Average Select"]
#[inline]
pub fn avgs(&mut self) -> _AVGSW {
_AVGSW { w: self }
}
#[doc = "Bit 2 - Hardware Average Enable"]
#[inline]
pub fn avge(&mut self) -> _AVGEW {
_AVGEW { w: self }
}
#[doc = "Bit 3 - Continuous Conversion Enable"]
#[inline]
pub fn adco(&mut self) -> _ADCOW {
_ADCOW { w: self }
}
#[doc = "Bit 7 - Calibration"]
#[inline]
pub fn cal(&mut self) -> _CALW {
_CALW { w: self }
}
}

143
src/adc0/ug.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register UG"]
pub struct R { pub type R = crate::R<u32, super::UG>;
bits: u32, #[doc = "Writer for register UG"]
} pub type W = crate::W<u32, super::UG>;
#[doc = r" Value to write to the register"] #[doc = "Register UG `reset()`'s with value 0x04"]
pub struct W { impl crate::ResetValue for super::UG {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::UG { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x04
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `UG`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type UG_R = crate::R<u16, u16>;
{ #[doc = "Write proxy for field `UG`"]
let bits = self.register.get(); pub struct UG_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> UG_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u16) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:9 - User gain error correction value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn ug(&self) -> UG_R {
F: FnOnce(&mut W) -> &mut W, UG_R::new((self.bits & 0x03ff) as u16)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:9 - User gain error correction value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn ug(&mut self) -> UG_W {
#[inline] UG_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct UGR {
bits: u16,
}
impl UGR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _UGW<'a> {
w: &'a mut W,
}
impl<'a> _UGW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - User gain error correction value"]
#[inline]
pub fn ug(&self) -> UGR {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
UGR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 4 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - User gain error correction value"]
#[inline]
pub fn ug(&mut self) -> _UGW {
_UGW { w: self }
}
}

143
src/adc0/usr_ofs.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register USR_OFS"]
pub struct R { pub type R = crate::R<u32, super::USR_OFS>;
bits: u32, #[doc = "Writer for register USR_OFS"]
} pub type W = crate::W<u32, super::USR_OFS>;
#[doc = r" Value to write to the register"] #[doc = "Register USR_OFS `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::USR_OFS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::USR_OFS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `USR_OFS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type USR_OFS_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `USR_OFS`"]
let bits = self.register.get(); pub struct USR_OFS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> USR_OFS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:7 - USER Offset Error Correction Value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn usr_ofs(&self) -> USR_OFS_R {
F: FnOnce(&mut W) -> &mut W, USR_OFS_R::new((self.bits & 0xff) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:7 - USER Offset Error Correction Value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn usr_ofs(&mut self) -> USR_OFS_W {
#[inline] USR_OFS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct USR_OFSR {
bits: u8,
}
impl USR_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _USR_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _USR_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - USER Offset Error Correction Value"]
#[inline]
pub fn usr_ofs(&self) -> USR_OFSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
USR_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - USER Offset Error Correction Value"]
#[inline]
pub fn usr_ofs(&mut self) -> _USR_OFSW {
_USR_OFSW { w: self }
}
}

143
src/adc0/xofs.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register XOFS"]
pub struct R { pub type R = crate::R<u32, super::XOFS>;
bits: u32, #[doc = "Writer for register XOFS"]
} pub type W = crate::W<u32, super::XOFS>;
#[doc = r" Value to write to the register"] #[doc = "Register XOFS `reset()`'s with value 0x30"]
pub struct W { impl crate::ResetValue for super::XOFS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::XOFS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x30
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `XOFS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type XOFS_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `XOFS`"]
let bits = self.register.get(); pub struct XOFS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> XOFS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x3f) | ((value as u32) & 0x3f);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:5 - X offset error correction value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn xofs(&self) -> XOFS_R {
F: FnOnce(&mut W) -> &mut W, XOFS_R::new((self.bits & 0x3f) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:5 - X offset error correction value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn xofs(&mut self) -> XOFS_W {
#[inline] XOFS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct XOFSR {
bits: u8,
}
impl XOFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _XOFSW<'a> {
w: &'a mut W,
}
impl<'a> _XOFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 63;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:5 - X offset error correction value"]
#[inline]
pub fn xofs(&self) -> XOFSR {
let bits = {
const MASK: u8 = 63;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
XOFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 48 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:5 - X offset error correction value"]
#[inline]
pub fn xofs(&mut self) -> _XOFSW {
_XOFSW { w: self }
}
}

143
src/adc0/yofs.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register YOFS"]
pub struct R { pub type R = crate::R<u32, super::YOFS>;
bits: u32, #[doc = "Writer for register YOFS"]
} pub type W = crate::W<u32, super::YOFS>;
#[doc = r" Value to write to the register"] #[doc = "Register YOFS `reset()`'s with value 0x37"]
pub struct W { impl crate::ResetValue for super::YOFS {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::YOFS { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x37
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `YOFS`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type YOFS_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `YOFS`"]
let bits = self.register.get(); pub struct YOFS_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> YOFS_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:7 - Y offset error correction value"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn yofs(&self) -> YOFS_R {
F: FnOnce(&mut W) -> &mut W, YOFS_R::new((self.bits & 0xff) as u8)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:7 - Y offset error correction value"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn yofs(&mut self) -> YOFS_W {
#[inline] YOFS_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct YOFSR {
bits: u8,
}
impl YOFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _YOFSW<'a> {
w: &'a mut W,
}
impl<'a> _YOFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Y offset error correction value"]
#[inline]
pub fn yofs(&self) -> YOFSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
YOFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 55 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Y offset error correction value"]
#[inline]
pub fn yofs(&mut self) -> _YOFSW {
_YOFSW { w: self }
}
}

290
src/adc1.rs
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@ -1,290 +0,0 @@
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - ADC Status and Control Register 1"]
pub sc1a: SC1,
#[doc = "0x04 - ADC Status and Control Register 1"]
pub sc1b: SC1,
#[doc = "0x08 - ADC Status and Control Register 1"]
pub sc1c: SC1,
#[doc = "0x0c - ADC Status and Control Register 1"]
pub sc1d: SC1,
#[doc = "0x10 - ADC Status and Control Register 1"]
pub sc1e: SC1,
#[doc = "0x14 - ADC Status and Control Register 1"]
pub sc1f: SC1,
#[doc = "0x18 - ADC Status and Control Register 1"]
pub sc1g: SC1,
#[doc = "0x1c - ADC Status and Control Register 1"]
pub sc1h: SC1,
#[doc = "0x20 - ADC Status and Control Register 1"]
pub sc1i: SC1,
#[doc = "0x24 - ADC Status and Control Register 1"]
pub sc1j: SC1,
#[doc = "0x28 - ADC Status and Control Register 1"]
pub sc1k: SC1,
#[doc = "0x2c - ADC Status and Control Register 1"]
pub sc1l: SC1,
#[doc = "0x30 - ADC Status and Control Register 1"]
pub sc1m: SC1,
#[doc = "0x34 - ADC Status and Control Register 1"]
pub sc1n: SC1,
#[doc = "0x38 - ADC Status and Control Register 1"]
pub sc1o: SC1,
#[doc = "0x3c - ADC Status and Control Register 1"]
pub sc1p: SC1,
#[doc = "0x40 - ADC Configuration Register 1"]
pub cfg1: CFG1,
#[doc = "0x44 - ADC Configuration Register 2"]
pub cfg2: CFG2,
#[doc = "0x48 - ADC Data Result Registers"]
pub ra: R,
#[doc = "0x4c - ADC Data Result Registers"]
pub rb: R,
#[doc = "0x50 - ADC Data Result Registers"]
pub rc: R,
#[doc = "0x54 - ADC Data Result Registers"]
pub rd: R,
#[doc = "0x58 - ADC Data Result Registers"]
pub re: R,
#[doc = "0x5c - ADC Data Result Registers"]
pub rf: R,
#[doc = "0x60 - ADC Data Result Registers"]
pub rg: R,
#[doc = "0x64 - ADC Data Result Registers"]
pub rh: R,
#[doc = "0x68 - ADC Data Result Registers"]
pub ri: R,
#[doc = "0x6c - ADC Data Result Registers"]
pub rj: R,
#[doc = "0x70 - ADC Data Result Registers"]
pub rk: R,
#[doc = "0x74 - ADC Data Result Registers"]
pub rl: R,
#[doc = "0x78 - ADC Data Result Registers"]
pub rm: R,
#[doc = "0x7c - ADC Data Result Registers"]
pub rn: R,
#[doc = "0x80 - ADC Data Result Registers"]
pub ro: R,
#[doc = "0x84 - ADC Data Result Registers"]
pub rp: R,
#[doc = "0x88 - Compare Value Registers"]
pub cv1: CV,
#[doc = "0x8c - Compare Value Registers"]
pub cv2: CV,
#[doc = "0x90 - Status and Control Register 2"]
pub sc2: SC2,
#[doc = "0x94 - Status and Control Register 3"]
pub sc3: SC3,
#[doc = "0x98 - BASE Offset Register"]
pub base_ofs: BASE_OFS,
#[doc = "0x9c - ADC Offset Correction Register"]
pub ofs: OFS,
#[doc = "0xa0 - USER Offset Correction Register"]
pub usr_ofs: USR_OFS,
#[doc = "0xa4 - ADC X Offset Correction Register"]
pub xofs: XOFS,
#[doc = "0xa8 - ADC Y Offset Correction Register"]
pub yofs: YOFS,
#[doc = "0xac - ADC Gain Register"]
pub g: G,
#[doc = "0xb0 - ADC User Gain Register"]
pub ug: UG,
#[doc = "0xb4 - ADC General Calibration Value Register S"]
pub clps: CLPS,
#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
pub clp3: CLP3,
#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
pub clp2: CLP2,
#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
pub clp1: CLP1,
#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
pub clp0: CLP0,
#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
pub clpx: CLPX,
#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
pub clp9: CLP9,
#[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
pub clps_ofs: CLPS_OFS,
#[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
pub clp3_ofs: CLP3_OFS,
#[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
pub clp2_ofs: CLP2_OFS,
#[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
pub clp1_ofs: CLP1_OFS,
#[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
pub clp0_ofs: CLP0_OFS,
#[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
pub clpx_ofs: CLPX_OFS,
#[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
pub clp9_ofs: CLP9_OFS,
}
#[doc = "ADC Status and Control Register 1"]
pub struct SC1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Status and Control Register 1"]
pub mod sc1;
#[doc = "ADC Configuration Register 1"]
pub struct CFG1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Configuration Register 1"]
pub mod cfg1;
#[doc = "ADC Configuration Register 2"]
pub struct CFG2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Configuration Register 2"]
pub mod cfg2;
#[doc = "ADC Data Result Registers"]
pub struct R {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Data Result Registers"]
pub mod r;
#[doc = "Compare Value Registers"]
pub struct CV {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Compare Value Registers"]
pub mod cv;
#[doc = "Status and Control Register 2"]
pub struct SC2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Status and Control Register 2"]
pub mod sc2;
#[doc = "Status and Control Register 3"]
pub struct SC3 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "Status and Control Register 3"]
pub mod sc3;
#[doc = "BASE Offset Register"]
pub struct BASE_OFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "BASE Offset Register"]
pub mod base_ofs;
#[doc = "ADC Offset Correction Register"]
pub struct OFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Offset Correction Register"]
pub mod ofs;
#[doc = "USER Offset Correction Register"]
pub struct USR_OFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "USER Offset Correction Register"]
pub mod usr_ofs;
#[doc = "ADC X Offset Correction Register"]
pub struct XOFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC X Offset Correction Register"]
pub mod xofs;
#[doc = "ADC Y Offset Correction Register"]
pub struct YOFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Y Offset Correction Register"]
pub mod yofs;
#[doc = "ADC Gain Register"]
pub struct G {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Gain Register"]
pub mod g;
#[doc = "ADC User Gain Register"]
pub struct UG {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC User Gain Register"]
pub mod ug;
#[doc = "ADC General Calibration Value Register S"]
pub struct CLPS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC General Calibration Value Register S"]
pub mod clps;
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
pub struct CLP3 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
pub mod clp3;
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
pub struct CLP2 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
pub mod clp2;
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
pub struct CLP1 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
pub mod clp1;
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
pub struct CLP0 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
pub mod clp0;
#[doc = "ADC Plus-Side General Calibration Value Register X"]
pub struct CLPX {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register X"]
pub mod clpx;
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
pub struct CLP9 {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
pub mod clp9;
#[doc = "ADC General Calibration Offset Value Register S"]
pub struct CLPS_OFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC General Calibration Offset Value Register S"]
pub mod clps_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
pub struct CLP3_OFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
pub mod clp3_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
pub struct CLP2_OFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
pub mod clp2_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
pub struct CLP1_OFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
pub mod clp1_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
pub struct CLP0_OFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
pub mod clp0_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
pub struct CLPX_OFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
pub mod clpx_ofs;
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
pub struct CLP9_OFS {
register: ::vcell::VolatileCell<u32>,
}
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
pub mod clp9_ofs;

103
src/adc1/base_ofs.rs
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@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::BASE_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct BA_OFSR {
bits: u8,
}
impl BA_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _BA_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _BA_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
#[inline]
pub fn ba_ofs(&self) -> BA_OFSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
BA_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 64 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
#[inline]
pub fn ba_ofs(&mut self) -> _BA_OFSW {
_BA_OFSW { w: self }
}
}

482
src/adc1/cfg1.rs
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@ -1,482 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFG1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `ADICLK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADICLKR {
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
_00,
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
_01,
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
_10,
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
_11,
}
impl ADICLKR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
ADICLKR::_00 => 0,
ADICLKR::_01 => 1,
ADICLKR::_10 => 2,
ADICLKR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> ADICLKR {
match value {
0 => ADICLKR::_00,
1 => ADICLKR::_01,
2 => ADICLKR::_10,
3 => ADICLKR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == ADICLKR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == ADICLKR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == ADICLKR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == ADICLKR::_11
}
}
#[doc = "Possible values of the field `MODE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MODER {
#[doc = "8-bit conversion."]
_00,
#[doc = "12-bit conversion."]
_01,
#[doc = "10-bit conversion."]
_10,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl MODER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
MODER::_00 => 0,
MODER::_01 => 1,
MODER::_10 => 2,
MODER::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> MODER {
match value {
0 => MODER::_00,
1 => MODER::_01,
2 => MODER::_10,
i => MODER::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == MODER::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == MODER::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == MODER::_10
}
}
#[doc = "Possible values of the field `ADIV`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADIVR {
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
_00,
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
_01,
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
_10,
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
_11,
}
impl ADIVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
ADIVR::_00 => 0,
ADIVR::_01 => 1,
ADIVR::_10 => 2,
ADIVR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> ADIVR {
match value {
0 => ADIVR::_00,
1 => ADIVR::_01,
2 => ADIVR::_10,
3 => ADIVR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == ADIVR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == ADIVR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == ADIVR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == ADIVR::_11
}
}
#[doc = "Values that can be written to the field `ADICLK`"]
pub enum ADICLKW {
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
_00,
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
_01,
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
_10,
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
_11,
}
impl ADICLKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
ADICLKW::_00 => 0,
ADICLKW::_01 => 1,
ADICLKW::_10 => 2,
ADICLKW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _ADICLKW<'a> {
w: &'a mut W,
}
impl<'a> _ADICLKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADICLKW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(ADICLKW::_00)
}
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(ADICLKW::_01)
}
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(ADICLKW::_10)
}
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(ADICLKW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MODE`"]
pub enum MODEW {
#[doc = "8-bit conversion."]
_00,
#[doc = "12-bit conversion."]
_01,
#[doc = "10-bit conversion."]
_10,
}
impl MODEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
MODEW::_00 => 0,
MODEW::_01 => 1,
MODEW::_10 => 2,
}
}
}
#[doc = r" Proxy"]
pub struct _MODEW<'a> {
w: &'a mut W,
}
impl<'a> _MODEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MODEW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "8-bit conversion."]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(MODEW::_00)
}
#[doc = "12-bit conversion."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(MODEW::_01)
}
#[doc = "10-bit conversion."]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(MODEW::_10)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADIV`"]
pub enum ADIVW {
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
_00,
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
_01,
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
_10,
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
_11,
}
impl ADIVW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
ADIVW::_00 => 0,
ADIVW::_01 => 1,
ADIVW::_10 => 2,
ADIVW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _ADIVW<'a> {
w: &'a mut W,
}
impl<'a> _ADIVW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADIVW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(ADIVW::_00)
}
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(ADIVW::_01)
}
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(ADIVW::_10)
}
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(ADIVW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CLRLTRGW<'a> {
w: &'a mut W,
}
impl<'a> _CLRLTRGW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Input Clock Select"]
#[inline]
pub fn adiclk(&self) -> ADICLKR {
ADICLKR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 2:3 - Conversion mode selection"]
#[inline]
pub fn mode(&self) -> MODER {
MODER::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 5:6 - Clock Divide Select"]
#[inline]
pub fn adiv(&self) -> ADIVR {
ADIVR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Input Clock Select"]
#[inline]
pub fn adiclk(&mut self) -> _ADICLKW {
_ADICLKW { w: self }
}
#[doc = "Bits 2:3 - Conversion mode selection"]
#[inline]
pub fn mode(&mut self) -> _MODEW {
_MODEW { w: self }
}
#[doc = "Bits 5:6 - Clock Divide Select"]
#[inline]
pub fn adiv(&mut self) -> _ADIVW {
_ADIVW { w: self }
}
#[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
#[inline]
pub fn clrltrg(&mut self) -> _CLRLTRGW {
_CLRLTRGW { w: self }
}
}

103
src/adc1/cfg2.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CFG2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct SMPLTSR {
bits: u8,
}
impl SMPLTSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _SMPLTSW<'a> {
w: &'a mut W,
}
impl<'a> _SMPLTSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Sample Time Select"]
#[inline]
pub fn smplts(&self) -> SMPLTSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
SMPLTSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 12 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Sample Time Select"]
#[inline]
pub fn smplts(&mut self) -> _SMPLTSW {
_SMPLTSW { w: self }
}
}

103
src/adc1/clp0.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP0 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP0R {
bits: u8,
}
impl CLP0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP0W<'a> {
w: &'a mut W,
}
impl<'a> _CLP0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Calibration Value"]
#[inline]
pub fn clp0(&self) -> CLP0R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 46 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Calibration Value"]
#[inline]
pub fn clp0(&mut self) -> _CLP0W {
_CLP0W { w: self }
}
}

103
src/adc1/clp0_ofs.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP0_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP0_OFSR {
bits: u8,
}
impl CLP0_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP0_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP0_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP0 Offset"]
#[inline]
pub fn clp0_ofs(&self) -> CLP0_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP0_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP0 Offset"]
#[inline]
pub fn clp0_ofs(&mut self) -> _CLP0_OFSW {
_CLP0_OFSW { w: self }
}
}

103
src/adc1/clp1.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP1R {
bits: u16,
}
impl CLP1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP1W<'a> {
w: &'a mut W,
}
impl<'a> _CLP1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 511;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:8 - Calibration Value"]
#[inline]
pub fn clp1(&self) -> CLP1R {
let bits = {
const MASK: u16 = 511;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP1R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 92 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:8 - Calibration Value"]
#[inline]
pub fn clp1(&mut self) -> _CLP1W {
_CLP1W { w: self }
}
}

103
src/adc1/clp1_ofs.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP1_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP1_OFSR {
bits: u8,
}
impl CLP1_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP1_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP1_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP1 Offset"]
#[inline]
pub fn clp1_ofs(&self) -> CLP1_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP1_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP1 Offset"]
#[inline]
pub fn clp1_ofs(&mut self) -> _CLP1_OFSW {
_CLP1_OFSW { w: self }
}
}

103
src/adc1/clp2.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP2R {
bits: u16,
}
impl CLP2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP2W<'a> {
w: &'a mut W,
}
impl<'a> _CLP2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp2(&self) -> CLP2R {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP2R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 184 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp2(&mut self) -> _CLP2W {
_CLP2W { w: self }
}
}

103
src/adc1/clp2_ofs.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP2_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP2_OFSR {
bits: u8,
}
impl CLP2_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP2_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP2_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP2 Offset"]
#[inline]
pub fn clp2_ofs(&self) -> CLP2_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP2_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP2 Offset"]
#[inline]
pub fn clp2_ofs(&mut self) -> _CLP2_OFSW {
_CLP2_OFSW { w: self }
}
}

103
src/adc1/clp3.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP3 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP3R {
bits: u16,
}
impl CLP3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP3W<'a> {
w: &'a mut W,
}
impl<'a> _CLP3W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp3(&self) -> CLP3R {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP3R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 384 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - Calibration Value"]
#[inline]
pub fn clp3(&mut self) -> _CLP3W {
_CLP3W { w: self }
}
}

103
src/adc1/clp3_ofs.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP3_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP3_OFSR {
bits: u8,
}
impl CLP3_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP3_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP3_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLP3 Offset"]
#[inline]
pub fn clp3_ofs(&self) -> CLP3_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP3_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLP3 Offset"]
#[inline]
pub fn clp3_ofs(&mut self) -> _CLP3_OFSW {
_CLP3_OFSW { w: self }
}
}

103
src/adc1/clp9.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP9 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP9R {
bits: u8,
}
impl CLP9R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP9W<'a> {
w: &'a mut W,
}
impl<'a> _CLP9W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clp9(&self) -> CLP9R {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLP9R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clp9(&mut self) -> _CLP9W {
_CLP9W { w: self }
}
}

103
src/adc1/clp9_ofs.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLP9_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLP9_OFSR {
bits: u16,
}
impl CLP9_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLP9_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLP9_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - CLP9 Offset"]
#[inline]
pub fn clp9_ofs(&self) -> CLP9_OFSR {
let bits = {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLP9_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 576 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:11 - CLP9 Offset"]
#[inline]
pub fn clp9_ofs(&mut self) -> _CLP9_OFSW {
_CLP9_OFSW { w: self }
}
}

103
src/adc1/clps.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLPS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLPSR {
bits: u8,
}
impl CLPSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPSW<'a> {
w: &'a mut W,
}
impl<'a> _CLPSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clps(&self) -> CLPSR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLPSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 46 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clps(&mut self) -> _CLPSW {
_CLPSW { w: self }
}
}

103
src/adc1/clps_ofs.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLPS_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLPS_OFSR {
bits: u8,
}
impl CLPS_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPS_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLPS_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - CLPS Offset"]
#[inline]
pub fn clps_ofs(&self) -> CLPS_OFSR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLPS_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - CLPS Offset"]
#[inline]
pub fn clps_ofs(&mut self) -> _CLPS_OFSW {
_CLPS_OFSW { w: self }
}
}

103
src/adc1/clpx.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLPX {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLPXR {
bits: u8,
}
impl CLPXR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPXW<'a> {
w: &'a mut W,
}
impl<'a> _CLPXW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clpx(&self) -> CLPXR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLPXR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:6 - Calibration Value"]
#[inline]
pub fn clpx(&mut self) -> _CLPXW {
_CLPXW { w: self }
}
}

103
src/adc1/clpx_ofs.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLPX_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CLPX_OFSR {
bits: u16,
}
impl CLPX_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CLPX_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _CLPX_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - CLPX Offset"]
#[inline]
pub fn clpx_ofs(&self) -> CLPX_OFSR {
let bits = {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CLPX_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 1088 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:11 - CLPX Offset"]
#[inline]
pub fn clpx_ofs(&mut self) -> _CLPX_OFSW {
_CLPX_OFSW { w: self }
}
}

103
src/adc1/cv.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CV {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct CVR {
bits: u16,
}
impl CVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _CVW<'a> {
w: &'a mut W,
}
impl<'a> _CVW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Compare Value."]
#[inline]
pub fn cv(&self) -> CVR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
CVR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Compare Value."]
#[inline]
pub fn cv(&mut self) -> _CVW {
_CVW { w: self }
}
}

103
src/adc1/g.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::G {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct GR {
bits: u16,
}
impl GR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _GW<'a> {
w: &'a mut W,
}
impl<'a> _GW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 2047;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
#[inline]
pub fn g(&self) -> GR {
let bits = {
const MASK: u16 = 2047;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
GR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 752 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
#[inline]
pub fn g(&mut self) -> _GW {
_GW { w: self }
}
}

103
src/adc1/ofs.rs
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@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct OFSR {
bits: u16,
}
impl OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _OFSW<'a> {
w: &'a mut W,
}
impl<'a> _OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Offset Error Correction Value"]
#[inline]
pub fn ofs(&self) -> OFSR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Offset Error Correction Value"]
#[inline]
pub fn ofs(&mut self) -> _OFSW {
_OFSW { w: self }
}
}

39
src/adc1/r.rs
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@ -1,39 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::R {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]
pub struct DR {
bits: u16,
}
impl DR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:11 - Data result"]
#[inline]
pub fn d(&self) -> DR {
let bits = {
const MASK: u16 = 4095;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
DR { bits }
}
}

765
src/adc1/sc1.rs
View File

@ -1,765 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SC1 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `ADCH`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADCHR {
#[doc = "Exernal channel 0 is selected as input."]
_00000,
#[doc = "Exernal channel 1 is selected as input."]
_00001,
#[doc = "Exernal channel 2 is selected as input."]
_00010,
#[doc = "Exernal channel 3 is selected as input."]
_00011,
#[doc = "Exernal channel 4 is selected as input."]
_00100,
#[doc = "Exernal channel 5 is selected as input."]
_00101,
#[doc = "Exernal channel 6 is selected as input."]
_00110,
#[doc = "Exernal channel 7 is selected as input."]
_00111,
#[doc = "Exernal channel 8 is selected as input."]
_01000,
#[doc = "Exernal channel 9 is selected as input."]
_01001,
#[doc = "Exernal channel 10 is selected as input."]
_01010,
#[doc = "Exernal channel 11 is selected as input."]
_01011,
#[doc = "Exernal channel 12 is selected as input."]
_01100,
#[doc = "Exernal channel 13 is selected as input."]
_01101,
#[doc = "Exernal channel 14 is selected as input."]
_01110,
#[doc = "Exernal channel 15 is selected as input."]
_01111,
#[doc = "Exernal channel 18 is selected as input."]
_10010,
#[doc = "Exernal channel 19 is selected as input."]
_10011,
#[doc = "Internal channel 0 is selected as input."]
_10101,
#[doc = "Internal channel 1 is selected as input."]
_10110,
#[doc = "Internal channel 2 is selected as input."]
_10111,
#[doc = "Temp Sensor"]
_11010,
#[doc = "Band Gap"]
_11011,
#[doc = "Internal channel 3 is selected as input."]
_11100,
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
_11101,
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
_11110,
#[doc = "Module is disabled"]
_11111,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl ADCHR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
ADCHR::_00000 => 0,
ADCHR::_00001 => 1,
ADCHR::_00010 => 2,
ADCHR::_00011 => 3,
ADCHR::_00100 => 4,
ADCHR::_00101 => 5,
ADCHR::_00110 => 6,
ADCHR::_00111 => 7,
ADCHR::_01000 => 8,
ADCHR::_01001 => 9,
ADCHR::_01010 => 10,
ADCHR::_01011 => 11,
ADCHR::_01100 => 12,
ADCHR::_01101 => 13,
ADCHR::_01110 => 14,
ADCHR::_01111 => 15,
ADCHR::_10010 => 18,
ADCHR::_10011 => 19,
ADCHR::_10101 => 21,
ADCHR::_10110 => 22,
ADCHR::_10111 => 23,
ADCHR::_11010 => 26,
ADCHR::_11011 => 27,
ADCHR::_11100 => 28,
ADCHR::_11101 => 29,
ADCHR::_11110 => 30,
ADCHR::_11111 => 31,
ADCHR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> ADCHR {
match value {
0 => ADCHR::_00000,
1 => ADCHR::_00001,
2 => ADCHR::_00010,
3 => ADCHR::_00011,
4 => ADCHR::_00100,
5 => ADCHR::_00101,
6 => ADCHR::_00110,
7 => ADCHR::_00111,
8 => ADCHR::_01000,
9 => ADCHR::_01001,
10 => ADCHR::_01010,
11 => ADCHR::_01011,
12 => ADCHR::_01100,
13 => ADCHR::_01101,
14 => ADCHR::_01110,
15 => ADCHR::_01111,
18 => ADCHR::_10010,
19 => ADCHR::_10011,
21 => ADCHR::_10101,
22 => ADCHR::_10110,
23 => ADCHR::_10111,
26 => ADCHR::_11010,
27 => ADCHR::_11011,
28 => ADCHR::_11100,
29 => ADCHR::_11101,
30 => ADCHR::_11110,
31 => ADCHR::_11111,
i => ADCHR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_00000`"]
#[inline]
pub fn is_00000(&self) -> bool {
*self == ADCHR::_00000
}
#[doc = "Checks if the value of the field is `_00001`"]
#[inline]
pub fn is_00001(&self) -> bool {
*self == ADCHR::_00001
}
#[doc = "Checks if the value of the field is `_00010`"]
#[inline]
pub fn is_00010(&self) -> bool {
*self == ADCHR::_00010
}
#[doc = "Checks if the value of the field is `_00011`"]
#[inline]
pub fn is_00011(&self) -> bool {
*self == ADCHR::_00011
}
#[doc = "Checks if the value of the field is `_00100`"]
#[inline]
pub fn is_00100(&self) -> bool {
*self == ADCHR::_00100
}
#[doc = "Checks if the value of the field is `_00101`"]
#[inline]
pub fn is_00101(&self) -> bool {
*self == ADCHR::_00101
}
#[doc = "Checks if the value of the field is `_00110`"]
#[inline]
pub fn is_00110(&self) -> bool {
*self == ADCHR::_00110
}
#[doc = "Checks if the value of the field is `_00111`"]
#[inline]
pub fn is_00111(&self) -> bool {
*self == ADCHR::_00111
}
#[doc = "Checks if the value of the field is `_01000`"]
#[inline]
pub fn is_01000(&self) -> bool {
*self == ADCHR::_01000
}
#[doc = "Checks if the value of the field is `_01001`"]
#[inline]
pub fn is_01001(&self) -> bool {
*self == ADCHR::_01001
}
#[doc = "Checks if the value of the field is `_01010`"]
#[inline]
pub fn is_01010(&self) -> bool {
*self == ADCHR::_01010
}
#[doc = "Checks if the value of the field is `_01011`"]
#[inline]
pub fn is_01011(&self) -> bool {
*self == ADCHR::_01011
}
#[doc = "Checks if the value of the field is `_01100`"]
#[inline]
pub fn is_01100(&self) -> bool {
*self == ADCHR::_01100
}
#[doc = "Checks if the value of the field is `_01101`"]
#[inline]
pub fn is_01101(&self) -> bool {
*self == ADCHR::_01101
}
#[doc = "Checks if the value of the field is `_01110`"]
#[inline]
pub fn is_01110(&self) -> bool {
*self == ADCHR::_01110
}
#[doc = "Checks if the value of the field is `_01111`"]
#[inline]
pub fn is_01111(&self) -> bool {
*self == ADCHR::_01111
}
#[doc = "Checks if the value of the field is `_10010`"]
#[inline]
pub fn is_10010(&self) -> bool {
*self == ADCHR::_10010
}
#[doc = "Checks if the value of the field is `_10011`"]
#[inline]
pub fn is_10011(&self) -> bool {
*self == ADCHR::_10011
}
#[doc = "Checks if the value of the field is `_10101`"]
#[inline]
pub fn is_10101(&self) -> bool {
*self == ADCHR::_10101
}
#[doc = "Checks if the value of the field is `_10110`"]
#[inline]
pub fn is_10110(&self) -> bool {
*self == ADCHR::_10110
}
#[doc = "Checks if the value of the field is `_10111`"]
#[inline]
pub fn is_10111(&self) -> bool {
*self == ADCHR::_10111
}
#[doc = "Checks if the value of the field is `_11010`"]
#[inline]
pub fn is_11010(&self) -> bool {
*self == ADCHR::_11010
}
#[doc = "Checks if the value of the field is `_11011`"]
#[inline]
pub fn is_11011(&self) -> bool {
*self == ADCHR::_11011
}
#[doc = "Checks if the value of the field is `_11100`"]
#[inline]
pub fn is_11100(&self) -> bool {
*self == ADCHR::_11100
}
#[doc = "Checks if the value of the field is `_11101`"]
#[inline]
pub fn is_11101(&self) -> bool {
*self == ADCHR::_11101
}
#[doc = "Checks if the value of the field is `_11110`"]
#[inline]
pub fn is_11110(&self) -> bool {
*self == ADCHR::_11110
}
#[doc = "Checks if the value of the field is `_11111`"]
#[inline]
pub fn is_11111(&self) -> bool {
*self == ADCHR::_11111
}
}
#[doc = "Possible values of the field `AIEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AIENR {
#[doc = "Conversion complete interrupt is disabled."]
_0,
#[doc = "Conversion complete interrupt is enabled."]
_1,
}
impl AIENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AIENR::_0 => false,
AIENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AIENR {
match value {
false => AIENR::_0,
true => AIENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == AIENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == AIENR::_1
}
}
#[doc = "Possible values of the field `COCO`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum COCOR {
#[doc = "Conversion is not completed."]
_0,
#[doc = "Conversion is completed."]
_1,
}
impl COCOR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
COCOR::_0 => false,
COCOR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> COCOR {
match value {
false => COCOR::_0,
true => COCOR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == COCOR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == COCOR::_1
}
}
#[doc = "Values that can be written to the field `ADCH`"]
pub enum ADCHW {
#[doc = "Exernal channel 0 is selected as input."]
_00000,
#[doc = "Exernal channel 1 is selected as input."]
_00001,
#[doc = "Exernal channel 2 is selected as input."]
_00010,
#[doc = "Exernal channel 3 is selected as input."]
_00011,
#[doc = "Exernal channel 4 is selected as input."]
_00100,
#[doc = "Exernal channel 5 is selected as input."]
_00101,
#[doc = "Exernal channel 6 is selected as input."]
_00110,
#[doc = "Exernal channel 7 is selected as input."]
_00111,
#[doc = "Exernal channel 8 is selected as input."]
_01000,
#[doc = "Exernal channel 9 is selected as input."]
_01001,
#[doc = "Exernal channel 10 is selected as input."]
_01010,
#[doc = "Exernal channel 11 is selected as input."]
_01011,
#[doc = "Exernal channel 12 is selected as input."]
_01100,
#[doc = "Exernal channel 13 is selected as input."]
_01101,
#[doc = "Exernal channel 14 is selected as input."]
_01110,
#[doc = "Exernal channel 15 is selected as input."]
_01111,
#[doc = "Exernal channel 18 is selected as input."]
_10010,
#[doc = "Exernal channel 19 is selected as input."]
_10011,
#[doc = "Internal channel 0 is selected as input."]
_10101,
#[doc = "Internal channel 1 is selected as input."]
_10110,
#[doc = "Internal channel 2 is selected as input."]
_10111,
#[doc = "Temp Sensor"]
_11010,
#[doc = "Band Gap"]
_11011,
#[doc = "Internal channel 3 is selected as input."]
_11100,
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
_11101,
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
_11110,
#[doc = "Module is disabled"]
_11111,
}
impl ADCHW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
ADCHW::_00000 => 0,
ADCHW::_00001 => 1,
ADCHW::_00010 => 2,
ADCHW::_00011 => 3,
ADCHW::_00100 => 4,
ADCHW::_00101 => 5,
ADCHW::_00110 => 6,
ADCHW::_00111 => 7,
ADCHW::_01000 => 8,
ADCHW::_01001 => 9,
ADCHW::_01010 => 10,
ADCHW::_01011 => 11,
ADCHW::_01100 => 12,
ADCHW::_01101 => 13,
ADCHW::_01110 => 14,
ADCHW::_01111 => 15,
ADCHW::_10010 => 18,
ADCHW::_10011 => 19,
ADCHW::_10101 => 21,
ADCHW::_10110 => 22,
ADCHW::_10111 => 23,
ADCHW::_11010 => 26,
ADCHW::_11011 => 27,
ADCHW::_11100 => 28,
ADCHW::_11101 => 29,
ADCHW::_11110 => 30,
ADCHW::_11111 => 31,
}
}
}
#[doc = r" Proxy"]
pub struct _ADCHW<'a> {
w: &'a mut W,
}
impl<'a> _ADCHW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADCHW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Exernal channel 0 is selected as input."]
#[inline]
pub fn _00000(self) -> &'a mut W {
self.variant(ADCHW::_00000)
}
#[doc = "Exernal channel 1 is selected as input."]
#[inline]
pub fn _00001(self) -> &'a mut W {
self.variant(ADCHW::_00001)
}
#[doc = "Exernal channel 2 is selected as input."]
#[inline]
pub fn _00010(self) -> &'a mut W {
self.variant(ADCHW::_00010)
}
#[doc = "Exernal channel 3 is selected as input."]
#[inline]
pub fn _00011(self) -> &'a mut W {
self.variant(ADCHW::_00011)
}
#[doc = "Exernal channel 4 is selected as input."]
#[inline]
pub fn _00100(self) -> &'a mut W {
self.variant(ADCHW::_00100)
}
#[doc = "Exernal channel 5 is selected as input."]
#[inline]
pub fn _00101(self) -> &'a mut W {
self.variant(ADCHW::_00101)
}
#[doc = "Exernal channel 6 is selected as input."]
#[inline]
pub fn _00110(self) -> &'a mut W {
self.variant(ADCHW::_00110)
}
#[doc = "Exernal channel 7 is selected as input."]
#[inline]
pub fn _00111(self) -> &'a mut W {
self.variant(ADCHW::_00111)
}
#[doc = "Exernal channel 8 is selected as input."]
#[inline]
pub fn _01000(self) -> &'a mut W {
self.variant(ADCHW::_01000)
}
#[doc = "Exernal channel 9 is selected as input."]
#[inline]
pub fn _01001(self) -> &'a mut W {
self.variant(ADCHW::_01001)
}
#[doc = "Exernal channel 10 is selected as input."]
#[inline]
pub fn _01010(self) -> &'a mut W {
self.variant(ADCHW::_01010)
}
#[doc = "Exernal channel 11 is selected as input."]
#[inline]
pub fn _01011(self) -> &'a mut W {
self.variant(ADCHW::_01011)
}
#[doc = "Exernal channel 12 is selected as input."]
#[inline]
pub fn _01100(self) -> &'a mut W {
self.variant(ADCHW::_01100)
}
#[doc = "Exernal channel 13 is selected as input."]
#[inline]
pub fn _01101(self) -> &'a mut W {
self.variant(ADCHW::_01101)
}
#[doc = "Exernal channel 14 is selected as input."]
#[inline]
pub fn _01110(self) -> &'a mut W {
self.variant(ADCHW::_01110)
}
#[doc = "Exernal channel 15 is selected as input."]
#[inline]
pub fn _01111(self) -> &'a mut W {
self.variant(ADCHW::_01111)
}
#[doc = "Exernal channel 18 is selected as input."]
#[inline]
pub fn _10010(self) -> &'a mut W {
self.variant(ADCHW::_10010)
}
#[doc = "Exernal channel 19 is selected as input."]
#[inline]
pub fn _10011(self) -> &'a mut W {
self.variant(ADCHW::_10011)
}
#[doc = "Internal channel 0 is selected as input."]
#[inline]
pub fn _10101(self) -> &'a mut W {
self.variant(ADCHW::_10101)
}
#[doc = "Internal channel 1 is selected as input."]
#[inline]
pub fn _10110(self) -> &'a mut W {
self.variant(ADCHW::_10110)
}
#[doc = "Internal channel 2 is selected as input."]
#[inline]
pub fn _10111(self) -> &'a mut W {
self.variant(ADCHW::_10111)
}
#[doc = "Temp Sensor"]
#[inline]
pub fn _11010(self) -> &'a mut W {
self.variant(ADCHW::_11010)
}
#[doc = "Band Gap"]
#[inline]
pub fn _11011(self) -> &'a mut W {
self.variant(ADCHW::_11011)
}
#[doc = "Internal channel 3 is selected as input."]
#[inline]
pub fn _11100(self) -> &'a mut W {
self.variant(ADCHW::_11100)
}
#[doc = "VREFSH is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
#[inline]
pub fn _11101(self) -> &'a mut W {
self.variant(ADCHW::_11101)
}
#[doc = "VREFSL is selected as input. Voltage reference selected is determined by SC2\\[REFSEL\\]."]
#[inline]
pub fn _11110(self) -> &'a mut W {
self.variant(ADCHW::_11110)
}
#[doc = "Module is disabled"]
#[inline]
pub fn _11111(self) -> &'a mut W {
self.variant(ADCHW::_11111)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 31;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AIEN`"]
pub enum AIENW {
#[doc = "Conversion complete interrupt is disabled."]
_0,
#[doc = "Conversion complete interrupt is enabled."]
_1,
}
impl AIENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AIENW::_0 => false,
AIENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AIENW<'a> {
w: &'a mut W,
}
impl<'a> _AIENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AIENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Conversion complete interrupt is disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(AIENW::_0)
}
#[doc = "Conversion complete interrupt is enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(AIENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - Input channel select"]
#[inline]
pub fn adch(&self) -> ADCHR {
ADCHR::_from({
const MASK: u8 = 31;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 6 - Interrupt Enable"]
#[inline]
pub fn aien(&self) -> AIENR {
AIENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Conversion Complete Flag"]
#[inline]
pub fn coco(&self) -> COCOR {
COCOR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 31 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - Input channel select"]
#[inline]
pub fn adch(&mut self) -> _ADCHW {
_ADCHW { w: self }
}
#[doc = "Bit 6 - Interrupt Enable"]
#[inline]
pub fn aien(&mut self) -> _AIENW {
_AIENW { w: self }
}
}

817
src/adc1/sc2.rs
View File

@ -1,817 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SC2 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `REFSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum REFSELR {
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
_00,
#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
_01,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl REFSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
REFSELR::_00 => 0,
REFSELR::_01 => 1,
REFSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> REFSELR {
match value {
0 => REFSELR::_00,
1 => REFSELR::_01,
i => REFSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == REFSELR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == REFSELR::_01
}
}
#[doc = "Possible values of the field `DMAEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DMAENR {
#[doc = "DMA is disabled."]
_0,
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n\\[COCO\\] flag is asserted."]
_1,
}
impl DMAENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
DMAENR::_0 => false,
DMAENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> DMAENR {
match value {
false => DMAENR::_0,
true => DMAENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == DMAENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == DMAENR::_1
}
}
#[doc = r" Value of the field"]
pub struct ACRENR {
bits: bool,
}
impl ACRENR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = r" Value of the field"]
pub struct ACFGTR {
bits: bool,
}
impl ACFGTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Possible values of the field `ACFE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ACFER {
#[doc = "Compare function disabled."]
_0,
#[doc = "Compare function enabled."]
_1,
}
impl ACFER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ACFER::_0 => false,
ACFER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ACFER {
match value {
false => ACFER::_0,
true => ACFER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ACFER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ACFER::_1
}
}
#[doc = "Possible values of the field `ADTRG`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADTRGR {
#[doc = "Software trigger selected."]
_0,
#[doc = "Hardware trigger selected."]
_1,
}
impl ADTRGR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADTRGR::_0 => false,
ADTRGR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADTRGR {
match value {
false => ADTRGR::_0,
true => ADTRGR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ADTRGR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ADTRGR::_1
}
}
#[doc = "Possible values of the field `ADACT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADACTR {
#[doc = "Conversion not in progress."]
_0,
#[doc = "Conversion in progress."]
_1,
}
impl ADACTR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADACTR::_0 => false,
ADACTR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADACTR {
match value {
false => ADACTR::_0,
true => ADACTR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ADACTR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ADACTR::_1
}
}
#[doc = r" Value of the field"]
pub struct TRGPRNUMR {
bits: u8,
}
impl TRGPRNUMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Possible values of the field `TRGSTLAT`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRGSTLATR {
#[doc = "No trigger request has been latched"]
_0,
#[doc = "A trigger request has been latched"]
_1,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl TRGSTLATR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
TRGSTLATR::_0 => 0,
TRGSTLATR::_1 => 1,
TRGSTLATR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> TRGSTLATR {
match value {
0 => TRGSTLATR::_0,
1 => TRGSTLATR::_1,
i => TRGSTLATR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TRGSTLATR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TRGSTLATR::_1
}
}
#[doc = "Possible values of the field `TRGSTERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TRGSTERRR {
#[doc = "No error has occurred"]
_0,
#[doc = "An error has occurred"]
_1,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl TRGSTERRR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
TRGSTERRR::_0 => 0,
TRGSTERRR::_1 => 1,
TRGSTERRR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> TRGSTERRR {
match value {
0 => TRGSTERRR::_0,
1 => TRGSTERRR::_1,
i => TRGSTERRR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == TRGSTERRR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == TRGSTERRR::_1
}
}
#[doc = "Values that can be written to the field `REFSEL`"]
pub enum REFSELW {
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
_00,
#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
_01,
}
impl REFSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
REFSELW::_00 => 0,
REFSELW::_01 => 1,
}
}
}
#[doc = r" Proxy"]
pub struct _REFSELW<'a> {
w: &'a mut W,
}
impl<'a> _REFSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: REFSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Default voltage reference pin pair, that is, external pins VREFH and VREFL"]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(REFSELW::_00)
}
#[doc = "Alternate reference voltage, that is, VALTH. This voltage may be additional external pin or internal source depending on the MCU configuration. See the chip configuration information for details specific to this MCU."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(REFSELW::_01)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `DMAEN`"]
pub enum DMAENW {
#[doc = "DMA is disabled."]
_0,
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n\\[COCO\\] flag is asserted."]
_1,
}
impl DMAENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
DMAENW::_0 => false,
DMAENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _DMAENW<'a> {
w: &'a mut W,
}
impl<'a> _DMAENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: DMAENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "DMA is disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(DMAENW::_0)
}
#[doc = "DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event , which is indicated when any SC1n\\[COCO\\] flag is asserted."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(DMAENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ACRENW<'a> {
w: &'a mut W,
}
impl<'a> _ACRENW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _ACFGTW<'a> {
w: &'a mut W,
}
impl<'a> _ACFGTW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ACFE`"]
pub enum ACFEW {
#[doc = "Compare function disabled."]
_0,
#[doc = "Compare function enabled."]
_1,
}
impl ACFEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ACFEW::_0 => false,
ACFEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ACFEW<'a> {
w: &'a mut W,
}
impl<'a> _ACFEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ACFEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Compare function disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ACFEW::_0)
}
#[doc = "Compare function enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ACFEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADTRG`"]
pub enum ADTRGW {
#[doc = "Software trigger selected."]
_0,
#[doc = "Hardware trigger selected."]
_1,
}
impl ADTRGW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADTRGW::_0 => false,
ADTRGW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADTRGW<'a> {
w: &'a mut W,
}
impl<'a> _ADTRGW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADTRGW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Software trigger selected."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ADTRGW::_0)
}
#[doc = "Hardware trigger selected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ADTRGW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Voltage Reference Selection"]
#[inline]
pub fn refsel(&self) -> REFSELR {
REFSELR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - DMA Enable"]
#[inline]
pub fn dmaen(&self) -> DMAENR {
DMAENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Compare Function Range Enable"]
#[inline]
pub fn acren(&self) -> ACRENR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ACRENR { bits }
}
#[doc = "Bit 4 - Compare Function Greater Than Enable"]
#[inline]
pub fn acfgt(&self) -> ACFGTR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) != 0
};
ACFGTR { bits }
}
#[doc = "Bit 5 - Compare Function Enable"]
#[inline]
pub fn acfe(&self) -> ACFER {
ACFER::_from({
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 6 - Conversion Trigger Select"]
#[inline]
pub fn adtrg(&self) -> ADTRGR {
ADTRGR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Conversion Active"]
#[inline]
pub fn adact(&self) -> ADACTR {
ADACTR::_from({
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 13:14 - Trigger Process Number"]
#[inline]
pub fn trgprnum(&self) -> TRGPRNUMR {
let bits = {
const MASK: u8 = 3;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TRGPRNUMR { bits }
}
#[doc = "Bits 16:19 - Trigger Status"]
#[inline]
pub fn trgstlat(&self) -> TRGSTLATR {
TRGSTLATR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 24:27 - Error in Multiplexed Trigger Request"]
#[inline]
pub fn trgsterr(&self) -> TRGSTERRR {
TRGSTERRR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Voltage Reference Selection"]
#[inline]
pub fn refsel(&mut self) -> _REFSELW {
_REFSELW { w: self }
}
#[doc = "Bit 2 - DMA Enable"]
#[inline]
pub fn dmaen(&mut self) -> _DMAENW {
_DMAENW { w: self }
}
#[doc = "Bit 3 - Compare Function Range Enable"]
#[inline]
pub fn acren(&mut self) -> _ACRENW {
_ACRENW { w: self }
}
#[doc = "Bit 4 - Compare Function Greater Than Enable"]
#[inline]
pub fn acfgt(&mut self) -> _ACFGTW {
_ACFGTW { w: self }
}
#[doc = "Bit 5 - Compare Function Enable"]
#[inline]
pub fn acfe(&mut self) -> _ACFEW {
_ACFEW { w: self }
}
#[doc = "Bit 6 - Conversion Trigger Select"]
#[inline]
pub fn adtrg(&mut self) -> _ADTRGW {
_ADTRGW { w: self }
}
}

495
src/adc1/sc3.rs
View File

@ -1,495 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SC3 {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `AVGS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AVGSR {
#[doc = "4 samples averaged."]
_00,
#[doc = "8 samples averaged."]
_01,
#[doc = "16 samples averaged."]
_10,
#[doc = "32 samples averaged."]
_11,
}
impl AVGSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
AVGSR::_00 => 0,
AVGSR::_01 => 1,
AVGSR::_10 => 2,
AVGSR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> AVGSR {
match value {
0 => AVGSR::_00,
1 => AVGSR::_01,
2 => AVGSR::_10,
3 => AVGSR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == AVGSR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == AVGSR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == AVGSR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == AVGSR::_11
}
}
#[doc = "Possible values of the field `AVGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum AVGER {
#[doc = "Hardware average function disabled."]
_0,
#[doc = "Hardware average function enabled."]
_1,
}
impl AVGER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
AVGER::_0 => false,
AVGER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> AVGER {
match value {
false => AVGER::_0,
true => AVGER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == AVGER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == AVGER::_1
}
}
#[doc = "Possible values of the field `ADCO`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ADCOR {
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
_0,
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
_1,
}
impl ADCOR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
ADCOR::_0 => false,
ADCOR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> ADCOR {
match value {
false => ADCOR::_0,
true => ADCOR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == ADCOR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == ADCOR::_1
}
}
#[doc = r" Value of the field"]
pub struct CALR {
bits: bool,
}
impl CALR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
self.bits
}
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = "Values that can be written to the field `AVGS`"]
pub enum AVGSW {
#[doc = "4 samples averaged."]
_00,
#[doc = "8 samples averaged."]
_01,
#[doc = "16 samples averaged."]
_10,
#[doc = "32 samples averaged."]
_11,
}
impl AVGSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
AVGSW::_00 => 0,
AVGSW::_01 => 1,
AVGSW::_10 => 2,
AVGSW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _AVGSW<'a> {
w: &'a mut W,
}
impl<'a> _AVGSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AVGSW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "4 samples averaged."]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(AVGSW::_00)
}
#[doc = "8 samples averaged."]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(AVGSW::_01)
}
#[doc = "16 samples averaged."]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(AVGSW::_10)
}
#[doc = "32 samples averaged."]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(AVGSW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `AVGE`"]
pub enum AVGEW {
#[doc = "Hardware average function disabled."]
_0,
#[doc = "Hardware average function enabled."]
_1,
}
impl AVGEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
AVGEW::_0 => false,
AVGEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _AVGEW<'a> {
w: &'a mut W,
}
impl<'a> _AVGEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: AVGEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Hardware average function disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(AVGEW::_0)
}
#[doc = "Hardware average function enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(AVGEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `ADCO`"]
pub enum ADCOW {
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
_0,
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
_1,
}
impl ADCOW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
ADCOW::_0 => false,
ADCOW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _ADCOW<'a> {
w: &'a mut W,
}
impl<'a> _ADCOW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: ADCOW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(ADCOW::_0)
}
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(ADCOW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CALW<'a> {
w: &'a mut W,
}
impl<'a> _CALW<'a> {
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Hardware Average Select"]
#[inline]
pub fn avgs(&self) -> AVGSR {
AVGSR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 2 - Hardware Average Enable"]
#[inline]
pub fn avge(&self) -> AVGER {
AVGER::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Continuous Conversion Enable"]
#[inline]
pub fn adco(&self) -> ADCOR {
ADCOR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 7 - Calibration"]
#[inline]
pub fn cal(&self) -> CALR {
let bits = {
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
};
CALR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Hardware Average Select"]
#[inline]
pub fn avgs(&mut self) -> _AVGSW {
_AVGSW { w: self }
}
#[doc = "Bit 2 - Hardware Average Enable"]
#[inline]
pub fn avge(&mut self) -> _AVGEW {
_AVGEW { w: self }
}
#[doc = "Bit 3 - Continuous Conversion Enable"]
#[inline]
pub fn adco(&mut self) -> _ADCOW {
_ADCOW { w: self }
}
#[doc = "Bit 7 - Calibration"]
#[inline]
pub fn cal(&mut self) -> _CALW {
_CALW { w: self }
}
}

103
src/adc1/ug.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::UG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct UGR {
bits: u16,
}
impl UGR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _UGW<'a> {
w: &'a mut W,
}
impl<'a> _UGW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:9 - User gain error correction value"]
#[inline]
pub fn ug(&self) -> UGR {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
UGR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 4 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:9 - User gain error correction value"]
#[inline]
pub fn ug(&mut self) -> _UGW {
_UGW { w: self }
}
}

103
src/adc1/usr_ofs.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::USR_OFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct USR_OFSR {
bits: u8,
}
impl USR_OFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _USR_OFSW<'a> {
w: &'a mut W,
}
impl<'a> _USR_OFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - USER Offset Error Correction Value"]
#[inline]
pub fn usr_ofs(&self) -> USR_OFSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
USR_OFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - USER Offset Error Correction Value"]
#[inline]
pub fn usr_ofs(&mut self) -> _USR_OFSW {
_USR_OFSW { w: self }
}
}

103
src/adc1/xofs.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::XOFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct XOFSR {
bits: u8,
}
impl XOFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _XOFSW<'a> {
w: &'a mut W,
}
impl<'a> _XOFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 63;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:5 - X offset error correction value"]
#[inline]
pub fn xofs(&self) -> XOFSR {
let bits = {
const MASK: u8 = 63;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
XOFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 48 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:5 - X offset error correction value"]
#[inline]
pub fn xofs(&mut self) -> _XOFSW {
_XOFSW { w: self }
}
}

103
src/adc1/yofs.rs
View File

@ -1,103 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::YOFS {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct YOFSR {
bits: u8,
}
impl YOFSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _YOFSW<'a> {
w: &'a mut W,
}
impl<'a> _YOFSW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Y offset error correction value"]
#[inline]
pub fn yofs(&self) -> YOFSR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
YOFSR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 55 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Y offset error correction value"]
#[inline]
pub fn yofs(&mut self) -> _YOFSW {
_YOFSW { w: self }
}
}

367
src/aips.rs
View File

@ -1,142 +1,225 @@
#[doc = r" Register block"] #[doc = r"Register block"]
#[repr(C)] #[repr(C)]
pub struct RegisterBlock { pub struct RegisterBlock {
#[doc = "0x00 - Master Privilege Register A"] #[doc = "0x00 - Master Privilege Register A"]
pub mpra: MPRA, pub mpra: MPRA,
_reserved0: [u8; 28usize], _reserved1: [u8; 28usize],
#[doc = "0x20 - Peripheral Access Control Register"] #[doc = "0x20 - Peripheral Access Control Register"]
pub pacra: PACRA, pub pacra: PACRA,
#[doc = "0x24 - Peripheral Access Control Register"] #[doc = "0x24 - Peripheral Access Control Register"]
pub pacrb: PACRB, pub pacrb: PACRB,
#[doc = "0x28 - Peripheral Access Control Register"] #[doc = "0x28 - Peripheral Access Control Register"]
pub pacrc: PACRC, pub pacrc: PACRC,
#[doc = "0x2c - Peripheral Access Control Register"] #[doc = "0x2c - Peripheral Access Control Register"]
pub pacrd: PACRD, pub pacrd: PACRD,
_reserved1: [u8; 16usize], _reserved5: [u8; 16usize],
#[doc = "0x40 - Off-Platform Peripheral Access Control Register"] #[doc = "0x40 - Off-Platform Peripheral Access Control Register"]
pub opacra: OPACRA, pub opacra: OPACRA,
#[doc = "0x44 - Off-Platform Peripheral Access Control Register"] #[doc = "0x44 - Off-Platform Peripheral Access Control Register"]
pub opacrb: OPACRB, pub opacrb: OPACRB,
#[doc = "0x48 - Off-Platform Peripheral Access Control Register"] #[doc = "0x48 - Off-Platform Peripheral Access Control Register"]
pub opacrc: OPACRC, pub opacrc: OPACRC,
#[doc = "0x4c - Off-Platform Peripheral Access Control Register"] #[doc = "0x4c - Off-Platform Peripheral Access Control Register"]
pub opacrd: OPACRD, pub opacrd: OPACRD,
#[doc = "0x50 - Off-Platform Peripheral Access Control Register"] #[doc = "0x50 - Off-Platform Peripheral Access Control Register"]
pub opacre: OPACRE, pub opacre: OPACRE,
#[doc = "0x54 - Off-Platform Peripheral Access Control Register"] #[doc = "0x54 - Off-Platform Peripheral Access Control Register"]
pub opacrf: OPACRF, pub opacrf: OPACRF,
#[doc = "0x58 - Off-Platform Peripheral Access Control Register"] #[doc = "0x58 - Off-Platform Peripheral Access Control Register"]
pub opacrg: OPACRG, pub opacrg: OPACRG,
#[doc = "0x5c - Off-Platform Peripheral Access Control Register"] #[doc = "0x5c - Off-Platform Peripheral Access Control Register"]
pub opacrh: OPACRH, pub opacrh: OPACRH,
#[doc = "0x60 - Off-Platform Peripheral Access Control Register"] #[doc = "0x60 - Off-Platform Peripheral Access Control Register"]
pub opacri: OPACRI, pub opacri: OPACRI,
#[doc = "0x64 - Off-Platform Peripheral Access Control Register"] #[doc = "0x64 - Off-Platform Peripheral Access Control Register"]
pub opacrj: OPACRJ, pub opacrj: OPACRJ,
#[doc = "0x68 - Off-Platform Peripheral Access Control Register"] #[doc = "0x68 - Off-Platform Peripheral Access Control Register"]
pub opacrk: OPACRK, pub opacrk: OPACRK,
#[doc = "0x6c - Off-Platform Peripheral Access Control Register"] #[doc = "0x6c - Off-Platform Peripheral Access Control Register"]
pub opacrl: OPACRL, pub opacrl: OPACRL,
} }
#[doc = "Master Privilege Register A"] #[doc = "Master Privilege Register A\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mpra](mpra) module"]
pub struct MPRA { pub type MPRA = crate::Reg<u32, _MPRA>;
register: ::vcell::VolatileCell<u32>, #[allow(missing_docs)]
} #[doc(hidden)]
#[doc = "Master Privilege Register A"] pub struct _MPRA;
pub mod mpra; #[doc = "`read()` method returns [mpra::R](mpra::R) reader structure"]
#[doc = "Peripheral Access Control Register"] impl crate::Readable for MPRA {}
pub struct PACRA { #[doc = "`write(|w| ..)` method takes [mpra::W](mpra::W) writer structure"]
register: ::vcell::VolatileCell<u32>, impl crate::Writable for MPRA {}
} #[doc = "Master Privilege Register A"]
#[doc = "Peripheral Access Control Register"] pub mod mpra;
pub mod pacra; #[doc = "Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pacra](pacra) module"]
#[doc = "Peripheral Access Control Register"] pub type PACRA = crate::Reg<u32, _PACRA>;
pub struct PACRB { #[allow(missing_docs)]
register: ::vcell::VolatileCell<u32>, #[doc(hidden)]
} pub struct _PACRA;
#[doc = "Peripheral Access Control Register"] #[doc = "`read()` method returns [pacra::R](pacra::R) reader structure"]
pub mod pacrb; impl crate::Readable for PACRA {}
#[doc = "Peripheral Access Control Register"] #[doc = "`write(|w| ..)` method takes [pacra::W](pacra::W) writer structure"]
pub struct PACRC { impl crate::Writable for PACRA {}
register: ::vcell::VolatileCell<u32>, #[doc = "Peripheral Access Control Register"]
} pub mod pacra;
#[doc = "Peripheral Access Control Register"] #[doc = "Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pacrb](pacrb) module"]
pub mod pacrc; pub type PACRB = crate::Reg<u32, _PACRB>;
#[doc = "Peripheral Access Control Register"] #[allow(missing_docs)]
pub struct PACRD { #[doc(hidden)]
register: ::vcell::VolatileCell<u32>, pub struct _PACRB;
} #[doc = "`read()` method returns [pacrb::R](pacrb::R) reader structure"]
#[doc = "Peripheral Access Control Register"] impl crate::Readable for PACRB {}
pub mod pacrd; #[doc = "`write(|w| ..)` method takes [pacrb::W](pacrb::W) writer structure"]
#[doc = "Off-Platform Peripheral Access Control Register"] impl crate::Writable for PACRB {}
pub struct OPACRA { #[doc = "Peripheral Access Control Register"]
register: ::vcell::VolatileCell<u32>, pub mod pacrb;
} #[doc = "Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pacrc](pacrc) module"]
#[doc = "Off-Platform Peripheral Access Control Register"] pub type PACRC = crate::Reg<u32, _PACRC>;
pub mod opacra; #[allow(missing_docs)]
#[doc = "Off-Platform Peripheral Access Control Register"] #[doc(hidden)]
pub struct OPACRB { pub struct _PACRC;
register: ::vcell::VolatileCell<u32>, #[doc = "`read()` method returns [pacrc::R](pacrc::R) reader structure"]
} impl crate::Readable for PACRC {}
#[doc = "Off-Platform Peripheral Access Control Register"] #[doc = "Peripheral Access Control Register"]
pub mod opacrb; pub mod pacrc;
#[doc = "Off-Platform Peripheral Access Control Register"] #[doc = "Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pacrd](pacrd) module"]
pub struct OPACRC { pub type PACRD = crate::Reg<u32, _PACRD>;
register: ::vcell::VolatileCell<u32>, #[allow(missing_docs)]
} #[doc(hidden)]
#[doc = "Off-Platform Peripheral Access Control Register"] pub struct _PACRD;
pub mod opacrc; #[doc = "`read()` method returns [pacrd::R](pacrd::R) reader structure"]
#[doc = "Off-Platform Peripheral Access Control Register"] impl crate::Readable for PACRD {}
pub struct OPACRD { #[doc = "`write(|w| ..)` method takes [pacrd::W](pacrd::W) writer structure"]
register: ::vcell::VolatileCell<u32>, impl crate::Writable for PACRD {}
} #[doc = "Peripheral Access Control Register"]
#[doc = "Off-Platform Peripheral Access Control Register"] pub mod pacrd;
pub mod opacrd; #[doc = "Off-Platform Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opacra](opacra) module"]
#[doc = "Off-Platform Peripheral Access Control Register"] pub type OPACRA = crate::Reg<u32, _OPACRA>;
pub struct OPACRE { #[allow(missing_docs)]
register: ::vcell::VolatileCell<u32>, #[doc(hidden)]
} pub struct _OPACRA;
#[doc = "Off-Platform Peripheral Access Control Register"] #[doc = "`read()` method returns [opacra::R](opacra::R) reader structure"]
pub mod opacre; impl crate::Readable for OPACRA {}
#[doc = "Off-Platform Peripheral Access Control Register"] #[doc = "`write(|w| ..)` method takes [opacra::W](opacra::W) writer structure"]
pub struct OPACRF { impl crate::Writable for OPACRA {}
register: ::vcell::VolatileCell<u32>, #[doc = "Off-Platform Peripheral Access Control Register"]
} pub mod opacra;
#[doc = "Off-Platform Peripheral Access Control Register"] #[doc = "Off-Platform Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opacrb](opacrb) module"]
pub mod opacrf; pub type OPACRB = crate::Reg<u32, _OPACRB>;
#[doc = "Off-Platform Peripheral Access Control Register"] #[allow(missing_docs)]
pub struct OPACRG { #[doc(hidden)]
register: ::vcell::VolatileCell<u32>, pub struct _OPACRB;
} #[doc = "`read()` method returns [opacrb::R](opacrb::R) reader structure"]
#[doc = "Off-Platform Peripheral Access Control Register"] impl crate::Readable for OPACRB {}
pub mod opacrg; #[doc = "`write(|w| ..)` method takes [opacrb::W](opacrb::W) writer structure"]
#[doc = "Off-Platform Peripheral Access Control Register"] impl crate::Writable for OPACRB {}
pub struct OPACRH { #[doc = "Off-Platform Peripheral Access Control Register"]
register: ::vcell::VolatileCell<u32>, pub mod opacrb;
} #[doc = "Off-Platform Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opacrc](opacrc) module"]
#[doc = "Off-Platform Peripheral Access Control Register"] pub type OPACRC = crate::Reg<u32, _OPACRC>;
pub mod opacrh; #[allow(missing_docs)]
#[doc = "Off-Platform Peripheral Access Control Register"] #[doc(hidden)]
pub struct OPACRI { pub struct _OPACRC;
register: ::vcell::VolatileCell<u32>, #[doc = "`read()` method returns [opacrc::R](opacrc::R) reader structure"]
} impl crate::Readable for OPACRC {}
#[doc = "Off-Platform Peripheral Access Control Register"] #[doc = "`write(|w| ..)` method takes [opacrc::W](opacrc::W) writer structure"]
pub mod opacri; impl crate::Writable for OPACRC {}
#[doc = "Off-Platform Peripheral Access Control Register"] #[doc = "Off-Platform Peripheral Access Control Register"]
pub struct OPACRJ { pub mod opacrc;
register: ::vcell::VolatileCell<u32>, #[doc = "Off-Platform Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opacrd](opacrd) module"]
} pub type OPACRD = crate::Reg<u32, _OPACRD>;
#[doc = "Off-Platform Peripheral Access Control Register"] #[allow(missing_docs)]
pub mod opacrj; #[doc(hidden)]
#[doc = "Off-Platform Peripheral Access Control Register"] pub struct _OPACRD;
pub struct OPACRK { #[doc = "`read()` method returns [opacrd::R](opacrd::R) reader structure"]
register: ::vcell::VolatileCell<u32>, impl crate::Readable for OPACRD {}
} #[doc = "`write(|w| ..)` method takes [opacrd::W](opacrd::W) writer structure"]
#[doc = "Off-Platform Peripheral Access Control Register"] impl crate::Writable for OPACRD {}
pub mod opacrk; #[doc = "Off-Platform Peripheral Access Control Register"]
#[doc = "Off-Platform Peripheral Access Control Register"] pub mod opacrd;
pub struct OPACRL { #[doc = "Off-Platform Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opacre](opacre) module"]
register: ::vcell::VolatileCell<u32>, pub type OPACRE = crate::Reg<u32, _OPACRE>;
} #[allow(missing_docs)]
#[doc = "Off-Platform Peripheral Access Control Register"] #[doc(hidden)]
pub mod opacrl; pub struct _OPACRE;
#[doc = "`read()` method returns [opacre::R](opacre::R) reader structure"]
impl crate::Readable for OPACRE {}
#[doc = "`write(|w| ..)` method takes [opacre::W](opacre::W) writer structure"]
impl crate::Writable for OPACRE {}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacre;
#[doc = "Off-Platform Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opacrf](opacrf) module"]
pub type OPACRF = crate::Reg<u32, _OPACRF>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _OPACRF;
#[doc = "`read()` method returns [opacrf::R](opacrf::R) reader structure"]
impl crate::Readable for OPACRF {}
#[doc = "`write(|w| ..)` method takes [opacrf::W](opacrf::W) writer structure"]
impl crate::Writable for OPACRF {}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrf;
#[doc = "Off-Platform Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opacrg](opacrg) module"]
pub type OPACRG = crate::Reg<u32, _OPACRG>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _OPACRG;
#[doc = "`read()` method returns [opacrg::R](opacrg::R) reader structure"]
impl crate::Readable for OPACRG {}
#[doc = "`write(|w| ..)` method takes [opacrg::W](opacrg::W) writer structure"]
impl crate::Writable for OPACRG {}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrg;
#[doc = "Off-Platform Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opacrh](opacrh) module"]
pub type OPACRH = crate::Reg<u32, _OPACRH>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _OPACRH;
#[doc = "`read()` method returns [opacrh::R](opacrh::R) reader structure"]
impl crate::Readable for OPACRH {}
#[doc = "`write(|w| ..)` method takes [opacrh::W](opacrh::W) writer structure"]
impl crate::Writable for OPACRH {}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrh;
#[doc = "Off-Platform Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opacri](opacri) module"]
pub type OPACRI = crate::Reg<u32, _OPACRI>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _OPACRI;
#[doc = "`read()` method returns [opacri::R](opacri::R) reader structure"]
impl crate::Readable for OPACRI {}
#[doc = "`write(|w| ..)` method takes [opacri::W](opacri::W) writer structure"]
impl crate::Writable for OPACRI {}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacri;
#[doc = "Off-Platform Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opacrj](opacrj) module"]
pub type OPACRJ = crate::Reg<u32, _OPACRJ>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _OPACRJ;
#[doc = "`read()` method returns [opacrj::R](opacrj::R) reader structure"]
impl crate::Readable for OPACRJ {}
#[doc = "`write(|w| ..)` method takes [opacrj::W](opacrj::W) writer structure"]
impl crate::Writable for OPACRJ {}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrj;
#[doc = "Off-Platform Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opacrk](opacrk) module"]
pub type OPACRK = crate::Reg<u32, _OPACRK>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _OPACRK;
#[doc = "`read()` method returns [opacrk::R](opacrk::R) reader structure"]
impl crate::Readable for OPACRK {}
#[doc = "`write(|w| ..)` method takes [opacrk::W](opacrk::W) writer structure"]
impl crate::Writable for OPACRK {}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrk;
#[doc = "Off-Platform Peripheral Access Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [opacrl](opacrl) module"]
pub type OPACRL = crate::Reg<u32, _OPACRL>;
#[allow(missing_docs)]
#[doc(hidden)]
pub struct _OPACRL;
#[doc = "`read()` method returns [opacrl::R](opacrl::R) reader structure"]
impl crate::Readable for OPACRL {}
#[doc = "`write(|w| ..)` method takes [opacrl::W](opacrl::W) writer structure"]
impl crate::Writable for OPACRL {}
#[doc = "Off-Platform Peripheral Access Control Register"]
pub mod opacrl;

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@ -1,419 +1,271 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register OPACRG"]
pub struct R { pub type R = crate::R<u32, super::OPACRG>;
bits: u32, #[doc = "Writer for register OPACRG"]
} pub type W = crate::W<u32, super::OPACRG>;
#[doc = r" Value to write to the register"] #[doc = "Register OPACRG `reset()`'s with value 0x0040_0000"]
pub struct W { impl crate::ResetValue for super::OPACRG {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::OPACRG { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x0040_0000
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Trusted Protect\n\nValue on reset: 0"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, #[derive(Clone, Copy, Debug, PartialEq)]
{ pub enum TP2_A {
let bits = self.register.get(); #[doc = "0: Accesses from an untrusted master are allowed."]
let r = R { bits: bits }; _0 = 0,
let mut w = W { bits: bits }; #[doc = "1: Accesses from an untrusted master are not allowed."]
f(&r, &mut w); _1 = 1,
self.register.set(w.bits); }
} impl From<TP2_A> for bool {
#[doc = r" Reads the contents of the register"] #[inline(always)]
#[inline] fn from(variant: TP2_A) -> Self {
pub fn read(&self) -> R { variant as u8 != 0
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] #[doc = "Reader of field `TP2`"]
#[inline] pub type TP2_R = crate::R<bool, TP2_A>;
pub fn write<F>(&self, f: F) impl TP2_R {
where #[doc = r"Get enumerated values variant"]
F: FnOnce(&mut W) -> &mut W, #[inline(always)]
{ pub fn variant(&self) -> TP2_A {
let mut w = W::reset_value(); match self.bits {
f(&mut w); false => TP2_A::_0,
self.register.set(w.bits); true => TP2_A::_1,
} }
#[doc = r" Writes the reset value to the register"] }
#[inline] #[doc = "Checks if the value of the field is `_0`"]
pub fn reset(&self) { #[inline(always)]
self.write(|w| w) pub fn is_0(&self) -> bool {
} *self == TP2_A::_0
} }
#[doc = "Possible values of the field `TP2`"] #[doc = "Checks if the value of the field is `_1`"]
#[derive(Clone, Copy, Debug, PartialEq)] #[inline(always)]
pub enum TP2R { pub fn is_1(&self) -> bool {
#[doc = "Accesses from an untrusted master are allowed."] *self == TP2_A::_1
_0, }
#[doc = "Accesses from an untrusted master are not allowed."] }
_1, #[doc = "Write proxy for field `TP2`"]
} pub struct TP2_W<'a> {
impl TP2R { w: &'a mut W,
#[doc = r" Returns `true` if the bit is clear (0)"] }
#[inline] impl<'a> TP2_W<'a> {
pub fn bit_is_clear(&self) -> bool { #[doc = r"Writes `variant` to the field"]
!self.bit() #[inline(always)]
} pub fn variant(self, variant: TP2_A) -> &'a mut W {
#[doc = r" Returns `true` if the bit is set (1)"] {
#[inline] self.bit(variant.into())
pub fn bit_is_set(&self) -> bool { }
self.bit() }
} #[doc = "Accesses from an untrusted master are allowed."]
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] pub fn _0(self) -> &'a mut W {
pub fn bit(&self) -> bool { self.variant(TP2_A::_0)
match *self { }
TP2R::_0 => false, #[doc = "Accesses from an untrusted master are not allowed."]
TP2R::_1 => true, #[inline(always)]
} pub fn _1(self) -> &'a mut W {
} self.variant(TP2_A::_1)
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = r"Sets the field bit"]
#[inline] #[inline(always)]
pub fn _from(value: bool) -> TP2R { pub fn set_bit(self) -> &'a mut W {
match value { self.bit(true)
false => TP2R::_0, }
true => TP2R::_1, #[doc = r"Clears the field bit"]
} #[inline(always)]
} pub fn clear_bit(self) -> &'a mut W {
#[doc = "Checks if the value of the field is `_0`"] self.bit(false)
#[inline] }
pub fn is_0(&self) -> bool { #[doc = r"Writes raw bits to the field"]
*self == TP2R::_0 #[inline(always)]
} pub fn bit(self, value: bool) -> &'a mut W {
#[doc = "Checks if the value of the field is `_1`"] self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
#[inline] self.w
pub fn is_1(&self) -> bool { }
*self == TP2R::_1 }
} #[doc = "Write Protect\n\nValue on reset: 0"]
} #[derive(Clone, Copy, Debug, PartialEq)]
#[doc = "Possible values of the field `WP2`"] pub enum WP2_A {
#[derive(Clone, Copy, Debug, PartialEq)] #[doc = "0: This peripheral allows write accesses."]
pub enum WP2R { _0 = 0,
#[doc = "This peripheral allows write accesses."] #[doc = "1: This peripheral is write protected."]
_0, _1 = 1,
#[doc = "This peripheral is write protected."] }
_1, impl From<WP2_A> for bool {
} #[inline(always)]
impl WP2R { fn from(variant: WP2_A) -> Self {
#[doc = r" Returns `true` if the bit is clear (0)"] variant as u8 != 0
#[inline] }
pub fn bit_is_clear(&self) -> bool { }
!self.bit() #[doc = "Reader of field `WP2`"]
} pub type WP2_R = crate::R<bool, WP2_A>;
#[doc = r" Returns `true` if the bit is set (1)"] impl WP2_R {
#[inline] #[doc = r"Get enumerated values variant"]
pub fn bit_is_set(&self) -> bool { #[inline(always)]
self.bit() pub fn variant(&self) -> WP2_A {
} match self.bits {
#[doc = r" Value of the field as raw bits"] false => WP2_A::_0,
#[inline] true => WP2_A::_1,
pub fn bit(&self) -> bool { }
match *self { }
WP2R::_0 => false, #[doc = "Checks if the value of the field is `_0`"]
WP2R::_1 => true, #[inline(always)]
} pub fn is_0(&self) -> bool {
} *self == WP2_A::_0
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = "Checks if the value of the field is `_1`"]
#[inline] #[inline(always)]
pub fn _from(value: bool) -> WP2R { pub fn is_1(&self) -> bool {
match value { *self == WP2_A::_1
false => WP2R::_0, }
true => WP2R::_1, }
} #[doc = "Write proxy for field `WP2`"]
} pub struct WP2_W<'a> {
#[doc = "Checks if the value of the field is `_0`"] w: &'a mut W,
#[inline] }
pub fn is_0(&self) -> bool { impl<'a> WP2_W<'a> {
*self == WP2R::_0 #[doc = r"Writes `variant` to the field"]
} #[inline(always)]
#[doc = "Checks if the value of the field is `_1`"] pub fn variant(self, variant: WP2_A) -> &'a mut W {
#[inline] {
pub fn is_1(&self) -> bool { self.bit(variant.into())
*self == WP2R::_1 }
} }
} #[doc = "This peripheral allows write accesses."]
#[doc = "Possible values of the field `SP2`"] #[inline(always)]
#[derive(Clone, Copy, Debug, PartialEq)] pub fn _0(self) -> &'a mut W {
pub enum SP2R { self.variant(WP2_A::_0)
#[doc = "This peripheral does not require supervisor privilege level for accesses."] }
_0, #[doc = "This peripheral is write protected."]
#[doc = "This peripheral requires supervisor privilege level for accesses."] #[inline(always)]
_1, pub fn _1(self) -> &'a mut W {
} self.variant(WP2_A::_1)
impl SP2R { }
#[doc = r" Returns `true` if the bit is clear (0)"] #[doc = r"Sets the field bit"]
#[inline] #[inline(always)]
pub fn bit_is_clear(&self) -> bool { pub fn set_bit(self) -> &'a mut W {
!self.bit() self.bit(true)
} }
#[doc = r" Returns `true` if the bit is set (1)"] #[doc = r"Clears the field bit"]
#[inline] #[inline(always)]
pub fn bit_is_set(&self) -> bool { pub fn clear_bit(self) -> &'a mut W {
self.bit() self.bit(false)
} }
#[doc = r" Value of the field as raw bits"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn bit(&self) -> bool { pub fn bit(self, value: bool) -> &'a mut W {
match *self { self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
SP2R::_0 => false, self.w
SP2R::_1 => true, }
} }
} #[doc = "Supervisor Protect\n\nValue on reset: 1"]
#[allow(missing_docs)] #[derive(Clone, Copy, Debug, PartialEq)]
#[doc(hidden)] pub enum SP2_A {
#[inline] #[doc = "0: This peripheral does not require supervisor privilege level for accesses."]
pub fn _from(value: bool) -> SP2R { _0 = 0,
match value { #[doc = "1: This peripheral requires supervisor privilege level for accesses."]
false => SP2R::_0, _1 = 1,
true => SP2R::_1, }
} impl From<SP2_A> for bool {
} #[inline(always)]
#[doc = "Checks if the value of the field is `_0`"] fn from(variant: SP2_A) -> Self {
#[inline] variant as u8 != 0
pub fn is_0(&self) -> bool { }
*self == SP2R::_0 }
} #[doc = "Reader of field `SP2`"]
#[doc = "Checks if the value of the field is `_1`"] pub type SP2_R = crate::R<bool, SP2_A>;
#[inline] impl SP2_R {
pub fn is_1(&self) -> bool { #[doc = r"Get enumerated values variant"]
*self == SP2R::_1 #[inline(always)]
} pub fn variant(&self) -> SP2_A {
} match self.bits {
#[doc = "Values that can be written to the field `TP2`"] false => SP2_A::_0,
pub enum TP2W { true => SP2_A::_1,
#[doc = "Accesses from an untrusted master are allowed."] }
_0, }
#[doc = "Accesses from an untrusted master are not allowed."] #[doc = "Checks if the value of the field is `_0`"]
_1, #[inline(always)]
} pub fn is_0(&self) -> bool {
impl TP2W { *self == SP2_A::_0
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = "Checks if the value of the field is `_1`"]
#[inline] #[inline(always)]
pub fn _bits(&self) -> bool { pub fn is_1(&self) -> bool {
match *self { *self == SP2_A::_1
TP2W::_0 => false, }
TP2W::_1 => true, }
} #[doc = "Write proxy for field `SP2`"]
} pub struct SP2_W<'a> {
} w: &'a mut W,
#[doc = r" Proxy"] }
pub struct _TP2W<'a> { impl<'a> SP2_W<'a> {
w: &'a mut W, #[doc = r"Writes `variant` to the field"]
} #[inline(always)]
impl<'a> _TP2W<'a> { pub fn variant(self, variant: SP2_A) -> &'a mut W {
#[doc = r" Writes `variant` to the field"] {
#[inline] self.bit(variant.into())
pub fn variant(self, variant: TP2W) -> &'a mut W { }
{ }
self.bit(variant._bits()) #[doc = "This peripheral does not require supervisor privilege level for accesses."]
} #[inline(always)]
} pub fn _0(self) -> &'a mut W {
#[doc = "Accesses from an untrusted master are allowed."] self.variant(SP2_A::_0)
#[inline] }
pub fn _0(self) -> &'a mut W { #[doc = "This peripheral requires supervisor privilege level for accesses."]
self.variant(TP2W::_0) #[inline(always)]
} pub fn _1(self) -> &'a mut W {
#[doc = "Accesses from an untrusted master are not allowed."] self.variant(SP2_A::_1)
#[inline] }
pub fn _1(self) -> &'a mut W { #[doc = r"Sets the field bit"]
self.variant(TP2W::_1) #[inline(always)]
} pub fn set_bit(self) -> &'a mut W {
#[doc = r" Sets the field bit"] self.bit(true)
pub fn set_bit(self) -> &'a mut W { }
self.bit(true) #[doc = r"Clears the field bit"]
} #[inline(always)]
#[doc = r" Clears the field bit"] pub fn clear_bit(self) -> &'a mut W {
pub fn clear_bit(self) -> &'a mut W { self.bit(false)
self.bit(false) }
} #[doc = r"Writes raw bits to the field"]
#[doc = r" Writes raw bits to the field"] #[inline(always)]
#[inline] pub fn bit(self, value: bool) -> &'a mut W {
pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
const MASK: bool = true; self.w
const OFFSET: u8 = 20; }
self.w.bits &= !((MASK as u32) << OFFSET); }
self.w.bits |= ((value & MASK) as u32) << OFFSET; impl R {
self.w #[doc = "Bit 20 - Trusted Protect"]
} #[inline(always)]
} pub fn tp2(&self) -> TP2_R {
#[doc = "Values that can be written to the field `WP2`"] TP2_R::new(((self.bits >> 20) & 0x01) != 0)
pub enum WP2W { }
#[doc = "This peripheral allows write accesses."] #[doc = "Bit 21 - Write Protect"]
_0, #[inline(always)]
#[doc = "This peripheral is write protected."] pub fn wp2(&self) -> WP2_R {
_1, WP2_R::new(((self.bits >> 21) & 0x01) != 0)
} }
impl WP2W { #[doc = "Bit 22 - Supervisor Protect"]
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] pub fn sp2(&self) -> SP2_R {
#[inline] SP2_R::new(((self.bits >> 22) & 0x01) != 0)
pub fn _bits(&self) -> bool { }
match *self { }
WP2W::_0 => false, impl W {
WP2W::_1 => true, #[doc = "Bit 20 - Trusted Protect"]
} #[inline(always)]
} pub fn tp2(&mut self) -> TP2_W {
} TP2_W { w: self }
#[doc = r" Proxy"] }
pub struct _WP2W<'a> { #[doc = "Bit 21 - Write Protect"]
w: &'a mut W, #[inline(always)]
} pub fn wp2(&mut self) -> WP2_W {
impl<'a> _WP2W<'a> { WP2_W { w: self }
#[doc = r" Writes `variant` to the field"] }
#[inline] #[doc = "Bit 22 - Supervisor Protect"]
pub fn variant(self, variant: WP2W) -> &'a mut W { #[inline(always)]
{ pub fn sp2(&mut self) -> SP2_W {
self.bit(variant._bits()) SP2_W { w: self }
} }
} }
#[doc = "This peripheral allows write accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WP2W::_0)
}
#[doc = "This peripheral is write protected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WP2W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SP2`"]
pub enum SP2W {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SP2W::_0 => false,
SP2W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SP2W<'a> {
w: &'a mut W,
}
impl<'a> _SP2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SP2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SP2W::_0)
}
#[doc = "This peripheral requires supervisor privilege level for accesses."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SP2W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 20 - Trusted Protect"]
#[inline]
pub fn tp2(&self) -> TP2R {
TP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 21 - Write Protect"]
#[inline]
pub fn wp2(&self) -> WP2R {
WP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 22 - Supervisor Protect"]
#[inline]
pub fn sp2(&self) -> SP2R {
SP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 4194304 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 20 - Trusted Protect"]
#[inline]
pub fn tp2(&mut self) -> _TP2W {
_TP2W { w: self }
}
#[doc = "Bit 21 - Write Protect"]
#[inline]
pub fn wp2(&mut self) -> _WP2W {
_WP2W { w: self }
}
#[doc = "Bit 22 - Supervisor Protect"]
#[inline]
pub fn sp2(&mut self) -> _SP2W {
_SP2W { w: self }
}
}

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#[doc = r" Value read from the register"] #[doc = "Reader of register OPACRH"]
pub struct R { pub type R = crate::R<u32, super::OPACRH>;
bits: u32, #[doc = "Writer for register OPACRH"]
} pub type W = crate::W<u32, super::OPACRH>;
#[doc = r" Value to write to the register"] #[doc = "Register OPACRH `reset()`'s with value 0x0040_0000"]
pub struct W { impl crate::ResetValue for super::OPACRH {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::OPACRH { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x0040_0000
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Trusted Protect\n\nValue on reset: 0"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, #[derive(Clone, Copy, Debug, PartialEq)]
{ pub enum TP2_A {
let bits = self.register.get(); #[doc = "0: Accesses from an untrusted master are allowed."]
let r = R { bits: bits }; _0 = 0,
let mut w = W { bits: bits }; #[doc = "1: Accesses from an untrusted master are not allowed."]
f(&r, &mut w); _1 = 1,
self.register.set(w.bits); }
} impl From<TP2_A> for bool {
#[doc = r" Reads the contents of the register"] #[inline(always)]
#[inline] fn from(variant: TP2_A) -> Self {
pub fn read(&self) -> R { variant as u8 != 0
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] #[doc = "Reader of field `TP2`"]
#[inline] pub type TP2_R = crate::R<bool, TP2_A>;
pub fn write<F>(&self, f: F) impl TP2_R {
where #[doc = r"Get enumerated values variant"]
F: FnOnce(&mut W) -> &mut W, #[inline(always)]
{ pub fn variant(&self) -> TP2_A {
let mut w = W::reset_value(); match self.bits {
f(&mut w); false => TP2_A::_0,
self.register.set(w.bits); true => TP2_A::_1,
} }
#[doc = r" Writes the reset value to the register"] }
#[inline] #[doc = "Checks if the value of the field is `_0`"]
pub fn reset(&self) { #[inline(always)]
self.write(|w| w) pub fn is_0(&self) -> bool {
} *self == TP2_A::_0
} }
#[doc = "Possible values of the field `TP2`"] #[doc = "Checks if the value of the field is `_1`"]
#[derive(Clone, Copy, Debug, PartialEq)] #[inline(always)]
pub enum TP2R { pub fn is_1(&self) -> bool {
#[doc = "Accesses from an untrusted master are allowed."] *self == TP2_A::_1
_0, }
#[doc = "Accesses from an untrusted master are not allowed."] }
_1, #[doc = "Write proxy for field `TP2`"]
} pub struct TP2_W<'a> {
impl TP2R { w: &'a mut W,
#[doc = r" Returns `true` if the bit is clear (0)"] }
#[inline] impl<'a> TP2_W<'a> {
pub fn bit_is_clear(&self) -> bool { #[doc = r"Writes `variant` to the field"]
!self.bit() #[inline(always)]
} pub fn variant(self, variant: TP2_A) -> &'a mut W {
#[doc = r" Returns `true` if the bit is set (1)"] {
#[inline] self.bit(variant.into())
pub fn bit_is_set(&self) -> bool { }
self.bit() }
} #[doc = "Accesses from an untrusted master are allowed."]
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] pub fn _0(self) -> &'a mut W {
pub fn bit(&self) -> bool { self.variant(TP2_A::_0)
match *self { }
TP2R::_0 => false, #[doc = "Accesses from an untrusted master are not allowed."]
TP2R::_1 => true, #[inline(always)]
} pub fn _1(self) -> &'a mut W {
} self.variant(TP2_A::_1)
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = r"Sets the field bit"]
#[inline] #[inline(always)]
pub fn _from(value: bool) -> TP2R { pub fn set_bit(self) -> &'a mut W {
match value { self.bit(true)
false => TP2R::_0, }
true => TP2R::_1, #[doc = r"Clears the field bit"]
} #[inline(always)]
} pub fn clear_bit(self) -> &'a mut W {
#[doc = "Checks if the value of the field is `_0`"] self.bit(false)
#[inline] }
pub fn is_0(&self) -> bool { #[doc = r"Writes raw bits to the field"]
*self == TP2R::_0 #[inline(always)]
} pub fn bit(self, value: bool) -> &'a mut W {
#[doc = "Checks if the value of the field is `_1`"] self.w.bits = (self.w.bits & !(0x01 << 20)) | (((value as u32) & 0x01) << 20);
#[inline] self.w
pub fn is_1(&self) -> bool { }
*self == TP2R::_1 }
} #[doc = "Write Protect\n\nValue on reset: 0"]
} #[derive(Clone, Copy, Debug, PartialEq)]
#[doc = "Possible values of the field `WP2`"] pub enum WP2_A {
#[derive(Clone, Copy, Debug, PartialEq)] #[doc = "0: This peripheral allows write accesses."]
pub enum WP2R { _0 = 0,
#[doc = "This peripheral allows write accesses."] #[doc = "1: This peripheral is write protected."]
_0, _1 = 1,
#[doc = "This peripheral is write protected."] }
_1, impl From<WP2_A> for bool {
} #[inline(always)]
impl WP2R { fn from(variant: WP2_A) -> Self {
#[doc = r" Returns `true` if the bit is clear (0)"] variant as u8 != 0
#[inline] }
pub fn bit_is_clear(&self) -> bool { }
!self.bit() #[doc = "Reader of field `WP2`"]
} pub type WP2_R = crate::R<bool, WP2_A>;
#[doc = r" Returns `true` if the bit is set (1)"] impl WP2_R {
#[inline] #[doc = r"Get enumerated values variant"]
pub fn bit_is_set(&self) -> bool { #[inline(always)]
self.bit() pub fn variant(&self) -> WP2_A {
} match self.bits {
#[doc = r" Value of the field as raw bits"] false => WP2_A::_0,
#[inline] true => WP2_A::_1,
pub fn bit(&self) -> bool { }
match *self { }
WP2R::_0 => false, #[doc = "Checks if the value of the field is `_0`"]
WP2R::_1 => true, #[inline(always)]
} pub fn is_0(&self) -> bool {
} *self == WP2_A::_0
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = "Checks if the value of the field is `_1`"]
#[inline] #[inline(always)]
pub fn _from(value: bool) -> WP2R { pub fn is_1(&self) -> bool {
match value { *self == WP2_A::_1
false => WP2R::_0, }
true => WP2R::_1, }
} #[doc = "Write proxy for field `WP2`"]
} pub struct WP2_W<'a> {
#[doc = "Checks if the value of the field is `_0`"] w: &'a mut W,
#[inline] }
pub fn is_0(&self) -> bool { impl<'a> WP2_W<'a> {
*self == WP2R::_0 #[doc = r"Writes `variant` to the field"]
} #[inline(always)]
#[doc = "Checks if the value of the field is `_1`"] pub fn variant(self, variant: WP2_A) -> &'a mut W {
#[inline] {
pub fn is_1(&self) -> bool { self.bit(variant.into())
*self == WP2R::_1 }
} }
} #[doc = "This peripheral allows write accesses."]
#[doc = "Possible values of the field `SP2`"] #[inline(always)]
#[derive(Clone, Copy, Debug, PartialEq)] pub fn _0(self) -> &'a mut W {
pub enum SP2R { self.variant(WP2_A::_0)
#[doc = "This peripheral does not require supervisor privilege level for accesses."] }
_0, #[doc = "This peripheral is write protected."]
#[doc = "This peripheral requires supervisor privilege level for accesses."] #[inline(always)]
_1, pub fn _1(self) -> &'a mut W {
} self.variant(WP2_A::_1)
impl SP2R { }
#[doc = r" Returns `true` if the bit is clear (0)"] #[doc = r"Sets the field bit"]
#[inline] #[inline(always)]
pub fn bit_is_clear(&self) -> bool { pub fn set_bit(self) -> &'a mut W {
!self.bit() self.bit(true)
} }
#[doc = r" Returns `true` if the bit is set (1)"] #[doc = r"Clears the field bit"]
#[inline] #[inline(always)]
pub fn bit_is_set(&self) -> bool { pub fn clear_bit(self) -> &'a mut W {
self.bit() self.bit(false)
} }
#[doc = r" Value of the field as raw bits"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn bit(&self) -> bool { pub fn bit(self, value: bool) -> &'a mut W {
match *self { self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
SP2R::_0 => false, self.w
SP2R::_1 => true, }
} }
} #[doc = "Supervisor Protect\n\nValue on reset: 1"]
#[allow(missing_docs)] #[derive(Clone, Copy, Debug, PartialEq)]
#[doc(hidden)] pub enum SP2_A {
#[inline] #[doc = "0: This peripheral does not require supervisor privilege level for accesses."]
pub fn _from(value: bool) -> SP2R { _0 = 0,
match value { #[doc = "1: This peripheral requires supervisor privilege level for accesses."]
false => SP2R::_0, _1 = 1,
true => SP2R::_1, }
} impl From<SP2_A> for bool {
} #[inline(always)]
#[doc = "Checks if the value of the field is `_0`"] fn from(variant: SP2_A) -> Self {
#[inline] variant as u8 != 0
pub fn is_0(&self) -> bool { }
*self == SP2R::_0 }
} #[doc = "Reader of field `SP2`"]
#[doc = "Checks if the value of the field is `_1`"] pub type SP2_R = crate::R<bool, SP2_A>;
#[inline] impl SP2_R {
pub fn is_1(&self) -> bool { #[doc = r"Get enumerated values variant"]
*self == SP2R::_1 #[inline(always)]
} pub fn variant(&self) -> SP2_A {
} match self.bits {
#[doc = "Values that can be written to the field `TP2`"] false => SP2_A::_0,
pub enum TP2W { true => SP2_A::_1,
#[doc = "Accesses from an untrusted master are allowed."] }
_0, }
#[doc = "Accesses from an untrusted master are not allowed."] #[doc = "Checks if the value of the field is `_0`"]
_1, #[inline(always)]
} pub fn is_0(&self) -> bool {
impl TP2W { *self == SP2_A::_0
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = "Checks if the value of the field is `_1`"]
#[inline] #[inline(always)]
pub fn _bits(&self) -> bool { pub fn is_1(&self) -> bool {
match *self { *self == SP2_A::_1
TP2W::_0 => false, }
TP2W::_1 => true, }
} #[doc = "Write proxy for field `SP2`"]
} pub struct SP2_W<'a> {
} w: &'a mut W,
#[doc = r" Proxy"] }
pub struct _TP2W<'a> { impl<'a> SP2_W<'a> {
w: &'a mut W, #[doc = r"Writes `variant` to the field"]
} #[inline(always)]
impl<'a> _TP2W<'a> { pub fn variant(self, variant: SP2_A) -> &'a mut W {
#[doc = r" Writes `variant` to the field"] {
#[inline] self.bit(variant.into())
pub fn variant(self, variant: TP2W) -> &'a mut W { }
{ }
self.bit(variant._bits()) #[doc = "This peripheral does not require supervisor privilege level for accesses."]
} #[inline(always)]
} pub fn _0(self) -> &'a mut W {
#[doc = "Accesses from an untrusted master are allowed."] self.variant(SP2_A::_0)
#[inline] }
pub fn _0(self) -> &'a mut W { #[doc = "This peripheral requires supervisor privilege level for accesses."]
self.variant(TP2W::_0) #[inline(always)]
} pub fn _1(self) -> &'a mut W {
#[doc = "Accesses from an untrusted master are not allowed."] self.variant(SP2_A::_1)
#[inline] }
pub fn _1(self) -> &'a mut W { #[doc = r"Sets the field bit"]
self.variant(TP2W::_1) #[inline(always)]
} pub fn set_bit(self) -> &'a mut W {
#[doc = r" Sets the field bit"] self.bit(true)
pub fn set_bit(self) -> &'a mut W { }
self.bit(true) #[doc = r"Clears the field bit"]
} #[inline(always)]
#[doc = r" Clears the field bit"] pub fn clear_bit(self) -> &'a mut W {
pub fn clear_bit(self) -> &'a mut W { self.bit(false)
self.bit(false) }
} #[doc = r"Writes raw bits to the field"]
#[doc = r" Writes raw bits to the field"] #[inline(always)]
#[inline] pub fn bit(self, value: bool) -> &'a mut W {
pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
const MASK: bool = true; self.w
const OFFSET: u8 = 20; }
self.w.bits &= !((MASK as u32) << OFFSET); }
self.w.bits |= ((value & MASK) as u32) << OFFSET; impl R {
self.w #[doc = "Bit 20 - Trusted Protect"]
} #[inline(always)]
} pub fn tp2(&self) -> TP2_R {
#[doc = "Values that can be written to the field `WP2`"] TP2_R::new(((self.bits >> 20) & 0x01) != 0)
pub enum WP2W { }
#[doc = "This peripheral allows write accesses."] #[doc = "Bit 21 - Write Protect"]
_0, #[inline(always)]
#[doc = "This peripheral is write protected."] pub fn wp2(&self) -> WP2_R {
_1, WP2_R::new(((self.bits >> 21) & 0x01) != 0)
} }
impl WP2W { #[doc = "Bit 22 - Supervisor Protect"]
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] pub fn sp2(&self) -> SP2_R {
#[inline] SP2_R::new(((self.bits >> 22) & 0x01) != 0)
pub fn _bits(&self) -> bool { }
match *self { }
WP2W::_0 => false, impl W {
WP2W::_1 => true, #[doc = "Bit 20 - Trusted Protect"]
} #[inline(always)]
} pub fn tp2(&mut self) -> TP2_W {
} TP2_W { w: self }
#[doc = r" Proxy"] }
pub struct _WP2W<'a> { #[doc = "Bit 21 - Write Protect"]
w: &'a mut W, #[inline(always)]
} pub fn wp2(&mut self) -> WP2_W {
impl<'a> _WP2W<'a> { WP2_W { w: self }
#[doc = r" Writes `variant` to the field"] }
#[inline] #[doc = "Bit 22 - Supervisor Protect"]
pub fn variant(self, variant: WP2W) -> &'a mut W { #[inline(always)]
{ pub fn sp2(&mut self) -> SP2_W {
self.bit(variant._bits()) SP2_W { w: self }
} }
} }
#[doc = "This peripheral allows write accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WP2W::_0)
}
#[doc = "This peripheral is write protected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WP2W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 21;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SP2`"]
pub enum SP2W {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SP2W::_0 => false,
SP2W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SP2W<'a> {
w: &'a mut W,
}
impl<'a> _SP2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SP2W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SP2W::_0)
}
#[doc = "This peripheral requires supervisor privilege level for accesses."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SP2W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 22;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 20 - Trusted Protect"]
#[inline]
pub fn tp2(&self) -> TP2R {
TP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 21 - Write Protect"]
#[inline]
pub fn wp2(&self) -> WP2R {
WP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 22 - Supervisor Protect"]
#[inline]
pub fn sp2(&self) -> SP2R {
SP2R::_from({
const MASK: bool = true;
const OFFSET: u8 = 22;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 4194304 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 20 - Trusted Protect"]
#[inline]
pub fn tp2(&mut self) -> _TP2W {
_TP2W { w: self }
}
#[doc = "Bit 21 - Write Protect"]
#[inline]
pub fn wp2(&mut self) -> _WP2W {
_WP2W { w: self }
}
#[doc = "Bit 22 - Supervisor Protect"]
#[inline]
pub fn sp2(&mut self) -> _SP2W {
_SP2W { w: self }
}
}

3138
src/aips/opacri.rs
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1914
src/aips/opacrj.rs
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690
src/aips/opacrk.rs
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@ -1,419 +1,271 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register OPACRK"]
pub struct R { pub type R = crate::R<u32, super::OPACRK>;
bits: u32, #[doc = "Writer for register OPACRK"]
} pub type W = crate::W<u32, super::OPACRK>;
#[doc = r" Value to write to the register"] #[doc = "Register OPACRK `reset()`'s with value 0x0004_0000"]
pub struct W { impl crate::ResetValue for super::OPACRK {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::OPACRK { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x0004_0000
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Trusted Protect\n\nValue on reset: 0"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, #[derive(Clone, Copy, Debug, PartialEq)]
{ pub enum TP3_A {
let bits = self.register.get(); #[doc = "0: Accesses from an untrusted master are allowed."]
let r = R { bits: bits }; _0 = 0,
let mut w = W { bits: bits }; #[doc = "1: Accesses from an untrusted master are not allowed."]
f(&r, &mut w); _1 = 1,
self.register.set(w.bits); }
} impl From<TP3_A> for bool {
#[doc = r" Reads the contents of the register"] #[inline(always)]
#[inline] fn from(variant: TP3_A) -> Self {
pub fn read(&self) -> R { variant as u8 != 0
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] #[doc = "Reader of field `TP3`"]
#[inline] pub type TP3_R = crate::R<bool, TP3_A>;
pub fn write<F>(&self, f: F) impl TP3_R {
where #[doc = r"Get enumerated values variant"]
F: FnOnce(&mut W) -> &mut W, #[inline(always)]
{ pub fn variant(&self) -> TP3_A {
let mut w = W::reset_value(); match self.bits {
f(&mut w); false => TP3_A::_0,
self.register.set(w.bits); true => TP3_A::_1,
} }
#[doc = r" Writes the reset value to the register"] }
#[inline] #[doc = "Checks if the value of the field is `_0`"]
pub fn reset(&self) { #[inline(always)]
self.write(|w| w) pub fn is_0(&self) -> bool {
} *self == TP3_A::_0
} }
#[doc = "Possible values of the field `TP3`"] #[doc = "Checks if the value of the field is `_1`"]
#[derive(Clone, Copy, Debug, PartialEq)] #[inline(always)]
pub enum TP3R { pub fn is_1(&self) -> bool {
#[doc = "Accesses from an untrusted master are allowed."] *self == TP3_A::_1
_0, }
#[doc = "Accesses from an untrusted master are not allowed."] }
_1, #[doc = "Write proxy for field `TP3`"]
} pub struct TP3_W<'a> {
impl TP3R { w: &'a mut W,
#[doc = r" Returns `true` if the bit is clear (0)"] }
#[inline] impl<'a> TP3_W<'a> {
pub fn bit_is_clear(&self) -> bool { #[doc = r"Writes `variant` to the field"]
!self.bit() #[inline(always)]
} pub fn variant(self, variant: TP3_A) -> &'a mut W {
#[doc = r" Returns `true` if the bit is set (1)"] {
#[inline] self.bit(variant.into())
pub fn bit_is_set(&self) -> bool { }
self.bit() }
} #[doc = "Accesses from an untrusted master are allowed."]
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] pub fn _0(self) -> &'a mut W {
pub fn bit(&self) -> bool { self.variant(TP3_A::_0)
match *self { }
TP3R::_0 => false, #[doc = "Accesses from an untrusted master are not allowed."]
TP3R::_1 => true, #[inline(always)]
} pub fn _1(self) -> &'a mut W {
} self.variant(TP3_A::_1)
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = r"Sets the field bit"]
#[inline] #[inline(always)]
pub fn _from(value: bool) -> TP3R { pub fn set_bit(self) -> &'a mut W {
match value { self.bit(true)
false => TP3R::_0, }
true => TP3R::_1, #[doc = r"Clears the field bit"]
} #[inline(always)]
} pub fn clear_bit(self) -> &'a mut W {
#[doc = "Checks if the value of the field is `_0`"] self.bit(false)
#[inline] }
pub fn is_0(&self) -> bool { #[doc = r"Writes raw bits to the field"]
*self == TP3R::_0 #[inline(always)]
} pub fn bit(self, value: bool) -> &'a mut W {
#[doc = "Checks if the value of the field is `_1`"] self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
#[inline] self.w
pub fn is_1(&self) -> bool { }
*self == TP3R::_1 }
} #[doc = "Write Protect\n\nValue on reset: 0"]
} #[derive(Clone, Copy, Debug, PartialEq)]
#[doc = "Possible values of the field `WP3`"] pub enum WP3_A {
#[derive(Clone, Copy, Debug, PartialEq)] #[doc = "0: This peripheral allows write accesses."]
pub enum WP3R { _0 = 0,
#[doc = "This peripheral allows write accesses."] #[doc = "1: This peripheral is write protected."]
_0, _1 = 1,
#[doc = "This peripheral is write protected."] }
_1, impl From<WP3_A> for bool {
} #[inline(always)]
impl WP3R { fn from(variant: WP3_A) -> Self {
#[doc = r" Returns `true` if the bit is clear (0)"] variant as u8 != 0
#[inline] }
pub fn bit_is_clear(&self) -> bool { }
!self.bit() #[doc = "Reader of field `WP3`"]
} pub type WP3_R = crate::R<bool, WP3_A>;
#[doc = r" Returns `true` if the bit is set (1)"] impl WP3_R {
#[inline] #[doc = r"Get enumerated values variant"]
pub fn bit_is_set(&self) -> bool { #[inline(always)]
self.bit() pub fn variant(&self) -> WP3_A {
} match self.bits {
#[doc = r" Value of the field as raw bits"] false => WP3_A::_0,
#[inline] true => WP3_A::_1,
pub fn bit(&self) -> bool { }
match *self { }
WP3R::_0 => false, #[doc = "Checks if the value of the field is `_0`"]
WP3R::_1 => true, #[inline(always)]
} pub fn is_0(&self) -> bool {
} *self == WP3_A::_0
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = "Checks if the value of the field is `_1`"]
#[inline] #[inline(always)]
pub fn _from(value: bool) -> WP3R { pub fn is_1(&self) -> bool {
match value { *self == WP3_A::_1
false => WP3R::_0, }
true => WP3R::_1, }
} #[doc = "Write proxy for field `WP3`"]
} pub struct WP3_W<'a> {
#[doc = "Checks if the value of the field is `_0`"] w: &'a mut W,
#[inline] }
pub fn is_0(&self) -> bool { impl<'a> WP3_W<'a> {
*self == WP3R::_0 #[doc = r"Writes `variant` to the field"]
} #[inline(always)]
#[doc = "Checks if the value of the field is `_1`"] pub fn variant(self, variant: WP3_A) -> &'a mut W {
#[inline] {
pub fn is_1(&self) -> bool { self.bit(variant.into())
*self == WP3R::_1 }
} }
} #[doc = "This peripheral allows write accesses."]
#[doc = "Possible values of the field `SP3`"] #[inline(always)]
#[derive(Clone, Copy, Debug, PartialEq)] pub fn _0(self) -> &'a mut W {
pub enum SP3R { self.variant(WP3_A::_0)
#[doc = "This peripheral does not require supervisor privilege level for accesses."] }
_0, #[doc = "This peripheral is write protected."]
#[doc = "This peripheral requires supervisor privilege level for accesses."] #[inline(always)]
_1, pub fn _1(self) -> &'a mut W {
} self.variant(WP3_A::_1)
impl SP3R { }
#[doc = r" Returns `true` if the bit is clear (0)"] #[doc = r"Sets the field bit"]
#[inline] #[inline(always)]
pub fn bit_is_clear(&self) -> bool { pub fn set_bit(self) -> &'a mut W {
!self.bit() self.bit(true)
} }
#[doc = r" Returns `true` if the bit is set (1)"] #[doc = r"Clears the field bit"]
#[inline] #[inline(always)]
pub fn bit_is_set(&self) -> bool { pub fn clear_bit(self) -> &'a mut W {
self.bit() self.bit(false)
} }
#[doc = r" Value of the field as raw bits"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn bit(&self) -> bool { pub fn bit(self, value: bool) -> &'a mut W {
match *self { self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
SP3R::_0 => false, self.w
SP3R::_1 => true, }
} }
} #[doc = "Supervisor Protect\n\nValue on reset: 1"]
#[allow(missing_docs)] #[derive(Clone, Copy, Debug, PartialEq)]
#[doc(hidden)] pub enum SP3_A {
#[inline] #[doc = "0: This peripheral does not require supervisor privilege level for accesses."]
pub fn _from(value: bool) -> SP3R { _0 = 0,
match value { #[doc = "1: This peripheral requires supervisor privilege level for accesses."]
false => SP3R::_0, _1 = 1,
true => SP3R::_1, }
} impl From<SP3_A> for bool {
} #[inline(always)]
#[doc = "Checks if the value of the field is `_0`"] fn from(variant: SP3_A) -> Self {
#[inline] variant as u8 != 0
pub fn is_0(&self) -> bool { }
*self == SP3R::_0 }
} #[doc = "Reader of field `SP3`"]
#[doc = "Checks if the value of the field is `_1`"] pub type SP3_R = crate::R<bool, SP3_A>;
#[inline] impl SP3_R {
pub fn is_1(&self) -> bool { #[doc = r"Get enumerated values variant"]
*self == SP3R::_1 #[inline(always)]
} pub fn variant(&self) -> SP3_A {
} match self.bits {
#[doc = "Values that can be written to the field `TP3`"] false => SP3_A::_0,
pub enum TP3W { true => SP3_A::_1,
#[doc = "Accesses from an untrusted master are allowed."] }
_0, }
#[doc = "Accesses from an untrusted master are not allowed."] #[doc = "Checks if the value of the field is `_0`"]
_1, #[inline(always)]
} pub fn is_0(&self) -> bool {
impl TP3W { *self == SP3_A::_0
#[allow(missing_docs)] }
#[doc(hidden)] #[doc = "Checks if the value of the field is `_1`"]
#[inline] #[inline(always)]
pub fn _bits(&self) -> bool { pub fn is_1(&self) -> bool {
match *self { *self == SP3_A::_1
TP3W::_0 => false, }
TP3W::_1 => true, }
} #[doc = "Write proxy for field `SP3`"]
} pub struct SP3_W<'a> {
} w: &'a mut W,
#[doc = r" Proxy"] }
pub struct _TP3W<'a> { impl<'a> SP3_W<'a> {
w: &'a mut W, #[doc = r"Writes `variant` to the field"]
} #[inline(always)]
impl<'a> _TP3W<'a> { pub fn variant(self, variant: SP3_A) -> &'a mut W {
#[doc = r" Writes `variant` to the field"] {
#[inline] self.bit(variant.into())
pub fn variant(self, variant: TP3W) -> &'a mut W { }
{ }
self.bit(variant._bits()) #[doc = "This peripheral does not require supervisor privilege level for accesses."]
} #[inline(always)]
} pub fn _0(self) -> &'a mut W {
#[doc = "Accesses from an untrusted master are allowed."] self.variant(SP3_A::_0)
#[inline] }
pub fn _0(self) -> &'a mut W { #[doc = "This peripheral requires supervisor privilege level for accesses."]
self.variant(TP3W::_0) #[inline(always)]
} pub fn _1(self) -> &'a mut W {
#[doc = "Accesses from an untrusted master are not allowed."] self.variant(SP3_A::_1)
#[inline] }
pub fn _1(self) -> &'a mut W { #[doc = r"Sets the field bit"]
self.variant(TP3W::_1) #[inline(always)]
} pub fn set_bit(self) -> &'a mut W {
#[doc = r" Sets the field bit"] self.bit(true)
pub fn set_bit(self) -> &'a mut W { }
self.bit(true) #[doc = r"Clears the field bit"]
} #[inline(always)]
#[doc = r" Clears the field bit"] pub fn clear_bit(self) -> &'a mut W {
pub fn clear_bit(self) -> &'a mut W { self.bit(false)
self.bit(false) }
} #[doc = r"Writes raw bits to the field"]
#[doc = r" Writes raw bits to the field"] #[inline(always)]
#[inline] pub fn bit(self, value: bool) -> &'a mut W {
pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
const MASK: bool = true; self.w
const OFFSET: u8 = 16; }
self.w.bits &= !((MASK as u32) << OFFSET); }
self.w.bits |= ((value & MASK) as u32) << OFFSET; impl R {
self.w #[doc = "Bit 16 - Trusted Protect"]
} #[inline(always)]
} pub fn tp3(&self) -> TP3_R {
#[doc = "Values that can be written to the field `WP3`"] TP3_R::new(((self.bits >> 16) & 0x01) != 0)
pub enum WP3W { }
#[doc = "This peripheral allows write accesses."] #[doc = "Bit 17 - Write Protect"]
_0, #[inline(always)]
#[doc = "This peripheral is write protected."] pub fn wp3(&self) -> WP3_R {
_1, WP3_R::new(((self.bits >> 17) & 0x01) != 0)
} }
impl WP3W { #[doc = "Bit 18 - Supervisor Protect"]
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] pub fn sp3(&self) -> SP3_R {
#[inline] SP3_R::new(((self.bits >> 18) & 0x01) != 0)
pub fn _bits(&self) -> bool { }
match *self { }
WP3W::_0 => false, impl W {
WP3W::_1 => true, #[doc = "Bit 16 - Trusted Protect"]
} #[inline(always)]
} pub fn tp3(&mut self) -> TP3_W {
} TP3_W { w: self }
#[doc = r" Proxy"] }
pub struct _WP3W<'a> { #[doc = "Bit 17 - Write Protect"]
w: &'a mut W, #[inline(always)]
} pub fn wp3(&mut self) -> WP3_W {
impl<'a> _WP3W<'a> { WP3_W { w: self }
#[doc = r" Writes `variant` to the field"] }
#[inline] #[doc = "Bit 18 - Supervisor Protect"]
pub fn variant(self, variant: WP3W) -> &'a mut W { #[inline(always)]
{ pub fn sp3(&mut self) -> SP3_W {
self.bit(variant._bits()) SP3_W { w: self }
} }
} }
#[doc = "This peripheral allows write accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(WP3W::_0)
}
#[doc = "This peripheral is write protected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(WP3W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SP3`"]
pub enum SP3W {
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
_0,
#[doc = "This peripheral requires supervisor privilege level for accesses."]
_1,
}
impl SP3W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SP3W::_0 => false,
SP3W::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SP3W<'a> {
w: &'a mut W,
}
impl<'a> _SP3W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SP3W) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This peripheral does not require supervisor privilege level for accesses."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SP3W::_0)
}
#[doc = "This peripheral requires supervisor privilege level for accesses."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SP3W::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 16 - Trusted Protect"]
#[inline]
pub fn tp3(&self) -> TP3R {
TP3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 17 - Write Protect"]
#[inline]
pub fn wp3(&self) -> WP3R {
WP3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 18 - Supervisor Protect"]
#[inline]
pub fn sp3(&self) -> SP3R {
SP3R::_from({
const MASK: bool = true;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 262144 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 16 - Trusted Protect"]
#[inline]
pub fn tp3(&mut self) -> _TP3W {
_TP3W { w: self }
}
#[doc = "Bit 17 - Write Protect"]
#[inline]
pub fn wp3(&mut self) -> _WP3W {
_WP3W { w: self }
}
#[doc = "Bit 18 - Supervisor Protect"]
#[inline]
pub fn sp3(&mut self) -> _SP3W {
_SP3W { w: self }
}
}

1914
src/aips/opacrl.rs
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1302
src/aips/pacra.rs
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src/aips/pacrb.rs
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src/aips/pacrc.rs
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@ -1,18 +1,3 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register PACRC"]
pub struct R { pub type R = crate::R<u32, super::PACRC>;
bits: u32, impl R {}
}
impl super::PACRC {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}

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src/aips/pacrd.rs
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src/can0.rs
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src/can0/cbt.rs
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@ -1,386 +1,221 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CBT"]
pub struct R { pub type R = crate::R<u32, super::CBT>;
bits: u32, #[doc = "Writer for register CBT"]
} pub type W = crate::W<u32, super::CBT>;
#[doc = r" Value to write to the register"] #[doc = "Register CBT `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::CBT {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CBT { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `EPSEG2`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type EPSEG2_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `EPSEG2`"]
let bits = self.register.get(); pub struct EPSEG2_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> EPSEG2_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] #[doc = "Reader of field `EPSEG1`"]
#[inline] pub type EPSEG1_R = crate::R<u8, u8>;
pub fn write<F>(&self, f: F) #[doc = "Write proxy for field `EPSEG1`"]
where pub struct EPSEG1_W<'a> {
F: FnOnce(&mut W) -> &mut W, w: &'a mut W,
{ }
let mut w = W::reset_value(); impl<'a> EPSEG1_W<'a> {
f(&mut w); #[doc = r"Writes raw bits to the field"]
self.register.set(w.bits); #[inline(always)]
} pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[doc = r" Writes the reset value to the register"] self.w.bits = (self.w.bits & !(0x1f << 5)) | (((value as u32) & 0x1f) << 5);
#[inline] self.w
pub fn reset(&self) { }
self.write(|w| w) }
} #[doc = "Reader of field `EPROPSEG`"]
} pub type EPROPSEG_R = crate::R<u8, u8>;
#[doc = r" Value of the field"] #[doc = "Write proxy for field `EPROPSEG`"]
pub struct EPSEG2R { pub struct EPROPSEG_W<'a> {
bits: u8, w: &'a mut W,
} }
impl EPSEG2R { impl<'a> EPROPSEG_W<'a> {
#[doc = r" Value of the field as raw bits"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn bits(&self) -> u8 { pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.bits self.w.bits = (self.w.bits & !(0x3f << 10)) | (((value as u32) & 0x3f) << 10);
} self.w
} }
#[doc = r" Value of the field"] }
pub struct EPSEG1R { #[doc = "Reader of field `ERJW`"]
bits: u8, pub type ERJW_R = crate::R<u8, u8>;
} #[doc = "Write proxy for field `ERJW`"]
impl EPSEG1R { pub struct ERJW_W<'a> {
#[doc = r" Value of the field as raw bits"] w: &'a mut W,
#[inline] }
pub fn bits(&self) -> u8 { impl<'a> ERJW_W<'a> {
self.bits #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
} pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[doc = r" Value of the field"] self.w.bits = (self.w.bits & !(0x1f << 16)) | (((value as u32) & 0x1f) << 16);
pub struct EPROPSEGR { self.w
bits: u8, }
} }
impl EPROPSEGR { #[doc = "Reader of field `EPRESDIV`"]
#[doc = r" Value of the field as raw bits"] pub type EPRESDIV_R = crate::R<u16, u16>;
#[inline] #[doc = "Write proxy for field `EPRESDIV`"]
pub fn bits(&self) -> u8 { pub struct EPRESDIV_W<'a> {
self.bits w: &'a mut W,
} }
} impl<'a> EPRESDIV_W<'a> {
#[doc = r" Value of the field"] #[doc = r"Writes raw bits to the field"]
pub struct ERJWR { #[inline(always)]
bits: u8, pub unsafe fn bits(self, value: u16) -> &'a mut W {
} self.w.bits = (self.w.bits & !(0x03ff << 21)) | (((value as u32) & 0x03ff) << 21);
impl ERJWR { self.w
#[doc = r" Value of the field as raw bits"] }
#[inline] }
pub fn bits(&self) -> u8 { #[doc = "Bit Timing Format Enable\n\nValue on reset: 0"]
self.bits #[derive(Clone, Copy, Debug, PartialEq)]
} pub enum BTF_A {
} #[doc = "0: Extended bit time definitions disabled."]
#[doc = r" Value of the field"] _0 = 0,
pub struct EPRESDIVR { #[doc = "1: Extended bit time definitions enabled."]
bits: u16, _1 = 1,
} }
impl EPRESDIVR { impl From<BTF_A> for bool {
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] fn from(variant: BTF_A) -> Self {
pub fn bits(&self) -> u16 { variant as u8 != 0
self.bits }
} }
} #[doc = "Reader of field `BTF`"]
#[doc = "Possible values of the field `BTF`"] pub type BTF_R = crate::R<bool, BTF_A>;
#[derive(Clone, Copy, Debug, PartialEq)] impl BTF_R {
pub enum BTFR { #[doc = r"Get enumerated values variant"]
#[doc = "Extended bit time definitions disabled."] #[inline(always)]
_0, pub fn variant(&self) -> BTF_A {
#[doc = "Extended bit time definitions enabled."] match self.bits {
_1, false => BTF_A::_0,
} true => BTF_A::_1,
impl BTFR { }
#[doc = r" Returns `true` if the bit is clear (0)"] }
#[inline] #[doc = "Checks if the value of the field is `_0`"]
pub fn bit_is_clear(&self) -> bool { #[inline(always)]
!self.bit() pub fn is_0(&self) -> bool {
} *self == BTF_A::_0
#[doc = r" Returns `true` if the bit is set (1)"] }
#[inline] #[doc = "Checks if the value of the field is `_1`"]
pub fn bit_is_set(&self) -> bool { #[inline(always)]
self.bit() pub fn is_1(&self) -> bool {
} *self == BTF_A::_1
#[doc = r" Value of the field as raw bits"] }
#[inline] }
pub fn bit(&self) -> bool { #[doc = "Write proxy for field `BTF`"]
match *self { pub struct BTF_W<'a> {
BTFR::_0 => false, w: &'a mut W,
BTFR::_1 => true, }
} impl<'a> BTF_W<'a> {
} #[doc = r"Writes `variant` to the field"]
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] pub fn variant(self, variant: BTF_A) -> &'a mut W {
#[inline] {
pub fn _from(value: bool) -> BTFR { self.bit(variant.into())
match value { }
false => BTFR::_0, }
true => BTFR::_1, #[doc = "Extended bit time definitions disabled."]
} #[inline(always)]
} pub fn _0(self) -> &'a mut W {
#[doc = "Checks if the value of the field is `_0`"] self.variant(BTF_A::_0)
#[inline] }
pub fn is_0(&self) -> bool { #[doc = "Extended bit time definitions enabled."]
*self == BTFR::_0 #[inline(always)]
} pub fn _1(self) -> &'a mut W {
#[doc = "Checks if the value of the field is `_1`"] self.variant(BTF_A::_1)
#[inline] }
pub fn is_1(&self) -> bool { #[doc = r"Sets the field bit"]
*self == BTFR::_1 #[inline(always)]
} pub fn set_bit(self) -> &'a mut W {
} self.bit(true)
#[doc = r" Proxy"] }
pub struct _EPSEG2W<'a> { #[doc = r"Clears the field bit"]
w: &'a mut W, #[inline(always)]
} pub fn clear_bit(self) -> &'a mut W {
impl<'a> _EPSEG2W<'a> { self.bit(false)
#[doc = r" Writes raw bits to the field"] }
#[inline] #[doc = r"Writes raw bits to the field"]
pub unsafe fn bits(self, value: u8) -> &'a mut W { #[inline(always)]
const MASK: u8 = 31; pub fn bit(self, value: bool) -> &'a mut W {
const OFFSET: u8 = 0; self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
self.w.bits &= !((MASK as u32) << OFFSET); self.w
self.w.bits |= ((value & MASK) as u32) << OFFSET; }
self.w }
} impl R {
} #[doc = "Bits 0:4 - Extended Phase Segment 2"]
#[doc = r" Proxy"] #[inline(always)]
pub struct _EPSEG1W<'a> { pub fn epseg2(&self) -> EPSEG2_R {
w: &'a mut W, EPSEG2_R::new((self.bits & 0x1f) as u8)
} }
impl<'a> _EPSEG1W<'a> { #[doc = "Bits 5:9 - Extended Phase Segment 1"]
#[doc = r" Writes raw bits to the field"] #[inline(always)]
#[inline] pub fn epseg1(&self) -> EPSEG1_R {
pub unsafe fn bits(self, value: u8) -> &'a mut W { EPSEG1_R::new(((self.bits >> 5) & 0x1f) as u8)
const MASK: u8 = 31; }
const OFFSET: u8 = 5; #[doc = "Bits 10:15 - Extended Propagation Segment"]
self.w.bits &= !((MASK as u32) << OFFSET); #[inline(always)]
self.w.bits |= ((value & MASK) as u32) << OFFSET; pub fn epropseg(&self) -> EPROPSEG_R {
self.w EPROPSEG_R::new(((self.bits >> 10) & 0x3f) as u8)
} }
} #[doc = "Bits 16:20 - Extended Resync Jump Width"]
#[doc = r" Proxy"] #[inline(always)]
pub struct _EPROPSEGW<'a> { pub fn erjw(&self) -> ERJW_R {
w: &'a mut W, ERJW_R::new(((self.bits >> 16) & 0x1f) as u8)
} }
impl<'a> _EPROPSEGW<'a> { #[doc = "Bits 21:30 - Extended Prescaler Division Factor"]
#[doc = r" Writes raw bits to the field"] #[inline(always)]
#[inline] pub fn epresdiv(&self) -> EPRESDIV_R {
pub unsafe fn bits(self, value: u8) -> &'a mut W { EPRESDIV_R::new(((self.bits >> 21) & 0x03ff) as u16)
const MASK: u8 = 63; }
const OFFSET: u8 = 10; #[doc = "Bit 31 - Bit Timing Format Enable"]
self.w.bits &= !((MASK as u32) << OFFSET); #[inline(always)]
self.w.bits |= ((value & MASK) as u32) << OFFSET; pub fn btf(&self) -> BTF_R {
self.w BTF_R::new(((self.bits >> 31) & 0x01) != 0)
} }
} }
#[doc = r" Proxy"] impl W {
pub struct _ERJWW<'a> { #[doc = "Bits 0:4 - Extended Phase Segment 2"]
w: &'a mut W, #[inline(always)]
} pub fn epseg2(&mut self) -> EPSEG2_W {
impl<'a> _ERJWW<'a> { EPSEG2_W { w: self }
#[doc = r" Writes raw bits to the field"] }
#[inline] #[doc = "Bits 5:9 - Extended Phase Segment 1"]
pub unsafe fn bits(self, value: u8) -> &'a mut W { #[inline(always)]
const MASK: u8 = 31; pub fn epseg1(&mut self) -> EPSEG1_W {
const OFFSET: u8 = 16; EPSEG1_W { w: self }
self.w.bits &= !((MASK as u32) << OFFSET); }
self.w.bits |= ((value & MASK) as u32) << OFFSET; #[doc = "Bits 10:15 - Extended Propagation Segment"]
self.w #[inline(always)]
} pub fn epropseg(&mut self) -> EPROPSEG_W {
} EPROPSEG_W { w: self }
#[doc = r" Proxy"] }
pub struct _EPRESDIVW<'a> { #[doc = "Bits 16:20 - Extended Resync Jump Width"]
w: &'a mut W, #[inline(always)]
} pub fn erjw(&mut self) -> ERJW_W {
impl<'a> _EPRESDIVW<'a> { ERJW_W { w: self }
#[doc = r" Writes raw bits to the field"] }
#[inline] #[doc = "Bits 21:30 - Extended Prescaler Division Factor"]
pub unsafe fn bits(self, value: u16) -> &'a mut W { #[inline(always)]
const MASK: u16 = 1023; pub fn epresdiv(&mut self) -> EPRESDIV_W {
const OFFSET: u8 = 21; EPRESDIV_W { w: self }
self.w.bits &= !((MASK as u32) << OFFSET); }
self.w.bits |= ((value & MASK) as u32) << OFFSET; #[doc = "Bit 31 - Bit Timing Format Enable"]
self.w #[inline(always)]
} pub fn btf(&mut self) -> BTF_W {
} BTF_W { w: self }
#[doc = "Values that can be written to the field `BTF`"] }
pub enum BTFW { }
#[doc = "Extended bit time definitions disabled."]
_0,
#[doc = "Extended bit time definitions enabled."]
_1,
}
impl BTFW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
BTFW::_0 => false,
BTFW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _BTFW<'a> {
w: &'a mut W,
}
impl<'a> _BTFW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: BTFW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Extended bit time definitions disabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(BTFW::_0)
}
#[doc = "Extended bit time definitions enabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(BTFW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 31;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:4 - Extended Phase Segment 2"]
#[inline]
pub fn epseg2(&self) -> EPSEG2R {
let bits = {
const MASK: u8 = 31;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
EPSEG2R { bits }
}
#[doc = "Bits 5:9 - Extended Phase Segment 1"]
#[inline]
pub fn epseg1(&self) -> EPSEG1R {
let bits = {
const MASK: u8 = 31;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) as u8
};
EPSEG1R { bits }
}
#[doc = "Bits 10:15 - Extended Propagation Segment"]
#[inline]
pub fn epropseg(&self) -> EPROPSEGR {
let bits = {
const MASK: u8 = 63;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
};
EPROPSEGR { bits }
}
#[doc = "Bits 16:20 - Extended Resync Jump Width"]
#[inline]
pub fn erjw(&self) -> ERJWR {
let bits = {
const MASK: u8 = 31;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
ERJWR { bits }
}
#[doc = "Bits 21:30 - Extended Prescaler Division Factor"]
#[inline]
pub fn epresdiv(&self) -> EPRESDIVR {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 21;
((self.bits >> OFFSET) & MASK as u32) as u16
};
EPRESDIVR { bits }
}
#[doc = "Bit 31 - Bit Timing Format Enable"]
#[inline]
pub fn btf(&self) -> BTFR {
BTFR::_from({
const MASK: bool = true;
const OFFSET: u8 = 31;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:4 - Extended Phase Segment 2"]
#[inline]
pub fn epseg2(&mut self) -> _EPSEG2W {
_EPSEG2W { w: self }
}
#[doc = "Bits 5:9 - Extended Phase Segment 1"]
#[inline]
pub fn epseg1(&mut self) -> _EPSEG1W {
_EPSEG1W { w: self }
}
#[doc = "Bits 10:15 - Extended Propagation Segment"]
#[inline]
pub fn epropseg(&mut self) -> _EPROPSEGW {
_EPROPSEGW { w: self }
}
#[doc = "Bits 16:20 - Extended Resync Jump Width"]
#[inline]
pub fn erjw(&mut self) -> _ERJWW {
_ERJWW { w: self }
}
#[doc = "Bits 21:30 - Extended Prescaler Division Factor"]
#[inline]
pub fn epresdiv(&mut self) -> _EPRESDIVW {
_EPRESDIVW { w: self }
}
#[doc = "Bit 31 - Bit Timing Format Enable"]
#[inline]
pub fn btf(&mut self) -> _BTFW {
_BTFW { w: self }
}
}

78
src/can0/crcr.rs
View File

@ -1,60 +1,18 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CRCR"]
pub struct R { pub type R = crate::R<u32, super::CRCR>;
bits: u32, #[doc = "Reader of field `TXCRC`"]
} pub type TXCRC_R = crate::R<u16, u16>;
impl super::CRCR { #[doc = "Reader of field `MBCRC`"]
#[doc = r" Reads the contents of the register"] pub type MBCRC_R = crate::R<u8, u8>;
#[inline] impl R {
pub fn read(&self) -> R { #[doc = "Bits 0:14 - Transmitted CRC value"]
R { bits: self.register.get() } #[inline(always)]
} pub fn txcrc(&self) -> TXCRC_R {
} TXCRC_R::new((self.bits & 0x7fff) as u16)
#[doc = r" Value of the field"] }
pub struct TXCRCR { #[doc = "Bits 16:22 - CRC Mailbox"]
bits: u16, #[inline(always)]
} pub fn mbcrc(&self) -> MBCRC_R {
impl TXCRCR { MBCRC_R::new(((self.bits >> 16) & 0x7f) as u8)
#[doc = r" Value of the field as raw bits"] }
#[inline] }
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct MBCRCR {
bits: u8,
}
impl MBCRCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:14 - Transmitted CRC value"]
#[inline]
pub fn txcrc(&self) -> TXCRCR {
let bits = {
const MASK: u16 = 32767;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
TXCRCR { bits }
}
#[doc = "Bits 16:22 - CRC Mailbox"]
#[inline]
pub fn mbcrc(&self) -> MBCRCR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MBCRCR { bits }
}
}

2647
src/can0/ctrl1.rs
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File diff suppressed because it is too large Load Diff

1412
src/can0/ctrl1_pn.rs
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File diff suppressed because it is too large Load Diff

2044
src/can0/ctrl2.rs
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File diff suppressed because it is too large Load Diff

143
src/can0/ctrl2_pn.rs
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@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register CTRL2_PN"]
pub struct R { pub type R = crate::R<u32, super::CTRL2_PN>;
bits: u32, #[doc = "Writer for register CTRL2_PN"]
} pub type W = crate::W<u32, super::CTRL2_PN>;
#[doc = r" Value to write to the register"] #[doc = "Register CTRL2_PN `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::CTRL2_PN {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::CTRL2_PN { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `MATCHTO`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type MATCHTO_R = crate::R<u16, u16>;
{ #[doc = "Write proxy for field `MATCHTO`"]
let bits = self.register.get(); pub struct MATCHTO_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> MATCHTO_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u16) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:15 - Timeout for No Message Matching the Filtering Criteria"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn matchto(&self) -> MATCHTO_R {
F: FnOnce(&mut W) -> &mut W, MATCHTO_R::new((self.bits & 0xffff) as u16)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:15 - Timeout for No Message Matching the Filtering Criteria"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn matchto(&mut self) -> MATCHTO_W {
#[inline] MATCHTO_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct MATCHTOR {
bits: u16,
}
impl MATCHTOR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _MATCHTOW<'a> {
w: &'a mut W,
}
impl<'a> _MATCHTOW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:15 - Timeout for No Message Matching the Filtering Criteria"]
#[inline]
pub fn matchto(&self) -> MATCHTOR {
let bits = {
const MASK: u16 = 65535;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u16
};
MATCHTOR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:15 - Timeout for No Message Matching the Filtering Criteria"]
#[inline]
pub fn matchto(&mut self) -> _MATCHTOW {
_MATCHTOW { w: self }
}
}

338
src/can0/ecr.rs
View File

@ -1,226 +1,112 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register ECR"]
pub struct R { pub type R = crate::R<u32, super::ECR>;
bits: u32, #[doc = "Writer for register ECR"]
} pub type W = crate::W<u32, super::ECR>;
#[doc = r" Value to write to the register"] #[doc = "Register ECR `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::ECR {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::ECR { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `TXERRCNT`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type TXERRCNT_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `TXERRCNT`"]
let bits = self.register.get(); pub struct TXERRCNT_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> TXERRCNT_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] #[doc = "Reader of field `RXERRCNT`"]
#[inline] pub type RXERRCNT_R = crate::R<u8, u8>;
pub fn write<F>(&self, f: F) #[doc = "Write proxy for field `RXERRCNT`"]
where pub struct RXERRCNT_W<'a> {
F: FnOnce(&mut W) -> &mut W, w: &'a mut W,
{ }
let mut w = W::reset_value(); impl<'a> RXERRCNT_W<'a> {
f(&mut w); #[doc = r"Writes raw bits to the field"]
self.register.set(w.bits); #[inline(always)]
} pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[doc = r" Writes the reset value to the register"] self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8);
#[inline] self.w
pub fn reset(&self) { }
self.write(|w| w) }
} #[doc = "Reader of field `TXERRCNT_FAST`"]
} pub type TXERRCNT_FAST_R = crate::R<u8, u8>;
#[doc = r" Value of the field"] #[doc = "Write proxy for field `TXERRCNT_FAST`"]
pub struct TXERRCNTR { pub struct TXERRCNT_FAST_W<'a> {
bits: u8, w: &'a mut W,
} }
impl TXERRCNTR { impl<'a> TXERRCNT_FAST_W<'a> {
#[doc = r" Value of the field as raw bits"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn bits(&self) -> u8 { pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.bits self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
} self.w
} }
#[doc = r" Value of the field"] }
pub struct RXERRCNTR { #[doc = "Reader of field `RXERRCNT_FAST`"]
bits: u8, pub type RXERRCNT_FAST_R = crate::R<u8, u8>;
} #[doc = "Write proxy for field `RXERRCNT_FAST`"]
impl RXERRCNTR { pub struct RXERRCNT_FAST_W<'a> {
#[doc = r" Value of the field as raw bits"] w: &'a mut W,
#[inline] }
pub fn bits(&self) -> u8 { impl<'a> RXERRCNT_FAST_W<'a> {
self.bits #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
} pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[doc = r" Value of the field"] self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24);
pub struct TXERRCNT_FASTR { self.w
bits: u8, }
} }
impl TXERRCNT_FASTR { impl R {
#[doc = r" Value of the field as raw bits"] #[doc = "Bits 0:7 - Transmit Error Counter"]
#[inline] #[inline(always)]
pub fn bits(&self) -> u8 { pub fn txerrcnt(&self) -> TXERRCNT_R {
self.bits TXERRCNT_R::new((self.bits & 0xff) as u8)
} }
} #[doc = "Bits 8:15 - Receive Error Counter"]
#[doc = r" Value of the field"] #[inline(always)]
pub struct RXERRCNT_FASTR { pub fn rxerrcnt(&self) -> RXERRCNT_R {
bits: u8, RXERRCNT_R::new(((self.bits >> 8) & 0xff) as u8)
} }
impl RXERRCNT_FASTR { #[doc = "Bits 16:23 - Transmit Error Counter for fast bits"]
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] pub fn txerrcnt_fast(&self) -> TXERRCNT_FAST_R {
pub fn bits(&self) -> u8 { TXERRCNT_FAST_R::new(((self.bits >> 16) & 0xff) as u8)
self.bits }
} #[doc = "Bits 24:31 - Receive Error Counter for fast bits"]
} #[inline(always)]
#[doc = r" Proxy"] pub fn rxerrcnt_fast(&self) -> RXERRCNT_FAST_R {
pub struct _TXERRCNTW<'a> { RXERRCNT_FAST_R::new(((self.bits >> 24) & 0xff) as u8)
w: &'a mut W, }
} }
impl<'a> _TXERRCNTW<'a> { impl W {
#[doc = r" Writes raw bits to the field"] #[doc = "Bits 0:7 - Transmit Error Counter"]
#[inline] #[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W { pub fn txerrcnt(&mut self) -> TXERRCNT_W {
const MASK: u8 = 255; TXERRCNT_W { w: self }
const OFFSET: u8 = 0; }
self.w.bits &= !((MASK as u32) << OFFSET); #[doc = "Bits 8:15 - Receive Error Counter"]
self.w.bits |= ((value & MASK) as u32) << OFFSET; #[inline(always)]
self.w pub fn rxerrcnt(&mut self) -> RXERRCNT_W {
} RXERRCNT_W { w: self }
} }
#[doc = r" Proxy"] #[doc = "Bits 16:23 - Transmit Error Counter for fast bits"]
pub struct _RXERRCNTW<'a> { #[inline(always)]
w: &'a mut W, pub fn txerrcnt_fast(&mut self) -> TXERRCNT_FAST_W {
} TXERRCNT_FAST_W { w: self }
impl<'a> _RXERRCNTW<'a> { }
#[doc = r" Writes raw bits to the field"] #[doc = "Bits 24:31 - Receive Error Counter for fast bits"]
#[inline] #[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W { pub fn rxerrcnt_fast(&mut self) -> RXERRCNT_FAST_W {
const MASK: u8 = 255; RXERRCNT_FAST_W { w: self }
const OFFSET: u8 = 8; }
self.w.bits &= !((MASK as u32) << OFFSET); }
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _TXERRCNT_FASTW<'a> {
w: &'a mut W,
}
impl<'a> _TXERRCNT_FASTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _RXERRCNT_FASTW<'a> {
w: &'a mut W,
}
impl<'a> _RXERRCNT_FASTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Transmit Error Counter"]
#[inline]
pub fn txerrcnt(&self) -> TXERRCNTR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TXERRCNTR { bits }
}
#[doc = "Bits 8:15 - Receive Error Counter"]
#[inline]
pub fn rxerrcnt(&self) -> RXERRCNTR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RXERRCNTR { bits }
}
#[doc = "Bits 16:23 - Transmit Error Counter for fast bits"]
#[inline]
pub fn txerrcnt_fast(&self) -> TXERRCNT_FASTR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
TXERRCNT_FASTR { bits }
}
#[doc = "Bits 24:31 - Receive Error Counter for fast bits"]
#[inline]
pub fn rxerrcnt_fast(&self) -> RXERRCNT_FASTR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
RXERRCNT_FASTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Transmit Error Counter"]
#[inline]
pub fn txerrcnt(&mut self) -> _TXERRCNTW {
_TXERRCNTW { w: self }
}
#[doc = "Bits 8:15 - Receive Error Counter"]
#[inline]
pub fn rxerrcnt(&mut self) -> _RXERRCNTW {
_RXERRCNTW { w: self }
}
#[doc = "Bits 16:23 - Transmit Error Counter for fast bits"]
#[inline]
pub fn txerrcnt_fast(&mut self) -> _TXERRCNT_FASTW {
_TXERRCNT_FASTW { w: self }
}
#[doc = "Bits 24:31 - Receive Error Counter for fast bits"]
#[inline]
pub fn rxerrcnt_fast(&mut self) -> _RXERRCNT_FASTW {
_RXERRCNT_FASTW { w: self }
}
}

226
src/can0/embedded_ram.rs
View File

@ -1,226 +0,0 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::EMBEDDEDRAM {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_3R {
bits: u8,
}
impl DATA_BYTE_3R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_2R {
bits: u8,
}
impl DATA_BYTE_2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_1R {
bits: u8,
}
impl DATA_BYTE_1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DATA_BYTE_0R {
bits: u8,
}
impl DATA_BYTE_0R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_3W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_3W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_2W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_2W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_1W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_1W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_0W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_0W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Data byte 3 of Rx/Tx frame."]
#[inline]
pub fn data_byte_3(&self) -> DATA_BYTE_3R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_3R { bits }
}
#[doc = "Bits 8:15 - Data byte 2 of Rx/Tx frame."]
#[inline]
pub fn data_byte_2(&self) -> DATA_BYTE_2R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_2R { bits }
}
#[doc = "Bits 16:23 - Data byte 1 of Rx/Tx frame."]
#[inline]
pub fn data_byte_1(&self) -> DATA_BYTE_1R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_1R { bits }
}
#[doc = "Bits 24:31 - Data byte 0 of Rx/Tx frame."]
#[inline]
pub fn data_byte_0(&self) -> DATA_BYTE_0R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_0R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Data byte 3 of Rx/Tx frame."]
#[inline]
pub fn data_byte_3(&mut self) -> _DATA_BYTE_3W {
_DATA_BYTE_3W { w: self }
}
#[doc = "Bits 8:15 - Data byte 2 of Rx/Tx frame."]
#[inline]
pub fn data_byte_2(&mut self) -> _DATA_BYTE_2W {
_DATA_BYTE_2W { w: self }
}
#[doc = "Bits 16:23 - Data byte 1 of Rx/Tx frame."]
#[inline]
pub fn data_byte_1(&mut self) -> _DATA_BYTE_1W {
_DATA_BYTE_1W { w: self }
}
#[doc = "Bits 24:31 - Data byte 0 of Rx/Tx frame."]
#[inline]
pub fn data_byte_0(&mut self) -> _DATA_BYTE_0W {
_DATA_BYTE_0W { w: self }
}
}

3266
src/can0/esr1.rs
View File

File diff suppressed because it is too large Load Diff

183
src/can0/esr2.rs
View File

@ -1,151 +1,96 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register ESR2"]
pub struct R { pub type R = crate::R<u32, super::ESR2>;
bits: u32, #[doc = "Inactive Mailbox\n\nValue on reset: 0"]
}
impl super::ESR2 {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
#[doc = "Possible values of the field `IMB`"]
#[derive(Clone, Copy, Debug, PartialEq)] #[derive(Clone, Copy, Debug, PartialEq)]
pub enum IMBR { pub enum IMB_A {
#[doc = "If ESR2\\[VPS\\] is asserted, the ESR2\\[LPTM\\] is not an inactive Mailbox."] #[doc = "0: If ESR2\\[VPS\\]
_0, is asserted, the ESR2\\[LPTM\\]
#[doc = "If ESR2\\[VPS\\] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one."] is not an inactive Mailbox."]
_1, _0 = 0,
#[doc = "1: If ESR2\\[VPS\\]
is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one."]
_1 = 1,
} }
impl IMBR { impl From<IMB_A> for bool {
#[doc = r" Returns `true` if the bit is clear (0)"] #[inline(always)]
#[inline] fn from(variant: IMB_A) -> Self {
pub fn bit_is_clear(&self) -> bool { variant as u8 != 0
!self.bit()
} }
#[doc = r" Returns `true` if the bit is set (1)"] }
#[inline] #[doc = "Reader of field `IMB`"]
pub fn bit_is_set(&self) -> bool { pub type IMB_R = crate::R<bool, IMB_A>;
self.bit() impl IMB_R {
} #[doc = r"Get enumerated values variant"]
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] pub fn variant(&self) -> IMB_A {
pub fn bit(&self) -> bool { match self.bits {
match *self { false => IMB_A::_0,
IMBR::_0 => false, true => IMB_A::_1,
IMBR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> IMBR {
match value {
false => IMBR::_0,
true => IMBR::_1,
} }
} }
#[doc = "Checks if the value of the field is `_0`"] #[doc = "Checks if the value of the field is `_0`"]
#[inline] #[inline(always)]
pub fn is_0(&self) -> bool { pub fn is_0(&self) -> bool {
*self == IMBR::_0 *self == IMB_A::_0
} }
#[doc = "Checks if the value of the field is `_1`"] #[doc = "Checks if the value of the field is `_1`"]
#[inline] #[inline(always)]
pub fn is_1(&self) -> bool { pub fn is_1(&self) -> bool {
*self == IMBR::_1 *self == IMB_A::_1
} }
} }
#[doc = "Possible values of the field `VPS`"] #[doc = "Valid Priority Status\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)] #[derive(Clone, Copy, Debug, PartialEq)]
pub enum VPSR { pub enum VPS_A {
#[doc = "Contents of IMB and LPTM are invalid."] #[doc = "0: Contents of IMB and LPTM are invalid."]
_0, _0 = 0,
#[doc = "Contents of IMB and LPTM are valid."] #[doc = "1: Contents of IMB and LPTM are valid."]
_1, _1 = 1,
} }
impl VPSR { impl From<VPS_A> for bool {
#[doc = r" Returns `true` if the bit is clear (0)"] #[inline(always)]
#[inline] fn from(variant: VPS_A) -> Self {
pub fn bit_is_clear(&self) -> bool { variant as u8 != 0
!self.bit()
} }
#[doc = r" Returns `true` if the bit is set (1)"] }
#[inline] #[doc = "Reader of field `VPS`"]
pub fn bit_is_set(&self) -> bool { pub type VPS_R = crate::R<bool, VPS_A>;
self.bit() impl VPS_R {
} #[doc = r"Get enumerated values variant"]
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] pub fn variant(&self) -> VPS_A {
pub fn bit(&self) -> bool { match self.bits {
match *self { false => VPS_A::_0,
VPSR::_0 => false, true => VPS_A::_1,
VPSR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> VPSR {
match value {
false => VPSR::_0,
true => VPSR::_1,
} }
} }
#[doc = "Checks if the value of the field is `_0`"] #[doc = "Checks if the value of the field is `_0`"]
#[inline] #[inline(always)]
pub fn is_0(&self) -> bool { pub fn is_0(&self) -> bool {
*self == VPSR::_0 *self == VPS_A::_0
} }
#[doc = "Checks if the value of the field is `_1`"] #[doc = "Checks if the value of the field is `_1`"]
#[inline] #[inline(always)]
pub fn is_1(&self) -> bool { pub fn is_1(&self) -> bool {
*self == VPSR::_1 *self == VPS_A::_1
}
}
#[doc = r" Value of the field"]
pub struct LPTMR {
bits: u8,
}
impl LPTMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
} }
} }
#[doc = "Reader of field `LPTM`"]
pub type LPTM_R = crate::R<u8, u8>;
impl R { impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 13 - Inactive Mailbox"] #[doc = "Bit 13 - Inactive Mailbox"]
#[inline] #[inline(always)]
pub fn imb(&self) -> IMBR { pub fn imb(&self) -> IMB_R {
IMBR::_from({ IMB_R::new(((self.bits >> 13) & 0x01) != 0)
const MASK: bool = true;
const OFFSET: u8 = 13;
((self.bits >> OFFSET) & MASK as u32) != 0
})
} }
#[doc = "Bit 14 - Valid Priority Status"] #[doc = "Bit 14 - Valid Priority Status"]
#[inline] #[inline(always)]
pub fn vps(&self) -> VPSR { pub fn vps(&self) -> VPS_R {
VPSR::_from({ VPS_R::new(((self.bits >> 14) & 0x01) != 0)
const MASK: bool = true;
const OFFSET: u8 = 14;
((self.bits >> OFFSET) & MASK as u32) != 0
})
} }
#[doc = "Bits 16:22 - Lowest Priority Tx Mailbox"] #[doc = "Bits 16:22 - Lowest Priority Tx Mailbox"]
#[inline] #[inline(always)]
pub fn lptm(&self) -> LPTMR { pub fn lptm(&self) -> LPTM_R {
let bits = { LPTM_R::new(((self.bits >> 16) & 0x7f) as u8)
const MASK: u8 = 127;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
LPTMR { bits }
} }
} }

403
src/can0/fdcbt.rs
View File

@ -1,267 +1,136 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register FDCBT"]
pub struct R { pub type R = crate::R<u32, super::FDCBT>;
bits: u32, #[doc = "Writer for register FDCBT"]
} pub type W = crate::W<u32, super::FDCBT>;
#[doc = r" Value to write to the register"] #[doc = "Register FDCBT `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::FDCBT {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::FDCBT { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `FPSEG2`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type FPSEG2_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `FPSEG2`"]
let bits = self.register.get(); pub struct FPSEG2_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> FPSEG2_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] #[doc = "Reader of field `FPSEG1`"]
#[inline] pub type FPSEG1_R = crate::R<u8, u8>;
pub fn write<F>(&self, f: F) #[doc = "Write proxy for field `FPSEG1`"]
where pub struct FPSEG1_W<'a> {
F: FnOnce(&mut W) -> &mut W, w: &'a mut W,
{ }
let mut w = W::reset_value(); impl<'a> FPSEG1_W<'a> {
f(&mut w); #[doc = r"Writes raw bits to the field"]
self.register.set(w.bits); #[inline(always)]
} pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[doc = r" Writes the reset value to the register"] self.w.bits = (self.w.bits & !(0x07 << 5)) | (((value as u32) & 0x07) << 5);
#[inline] self.w
pub fn reset(&self) { }
self.write(|w| w) }
} #[doc = "Reader of field `FPROPSEG`"]
} pub type FPROPSEG_R = crate::R<u8, u8>;
#[doc = r" Value of the field"] #[doc = "Write proxy for field `FPROPSEG`"]
pub struct FPSEG2R { pub struct FPROPSEG_W<'a> {
bits: u8, w: &'a mut W,
} }
impl FPSEG2R { impl<'a> FPROPSEG_W<'a> {
#[doc = r" Value of the field as raw bits"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn bits(&self) -> u8 { pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.bits self.w.bits = (self.w.bits & !(0x1f << 10)) | (((value as u32) & 0x1f) << 10);
} self.w
} }
#[doc = r" Value of the field"] }
pub struct FPSEG1R { #[doc = "Reader of field `FRJW`"]
bits: u8, pub type FRJW_R = crate::R<u8, u8>;
} #[doc = "Write proxy for field `FRJW`"]
impl FPSEG1R { pub struct FRJW_W<'a> {
#[doc = r" Value of the field as raw bits"] w: &'a mut W,
#[inline] }
pub fn bits(&self) -> u8 { impl<'a> FRJW_W<'a> {
self.bits #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
} pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[doc = r" Value of the field"] self.w.bits = (self.w.bits & !(0x07 << 16)) | (((value as u32) & 0x07) << 16);
pub struct FPROPSEGR { self.w
bits: u8, }
} }
impl FPROPSEGR { #[doc = "Reader of field `FPRESDIV`"]
#[doc = r" Value of the field as raw bits"] pub type FPRESDIV_R = crate::R<u16, u16>;
#[inline] #[doc = "Write proxy for field `FPRESDIV`"]
pub fn bits(&self) -> u8 { pub struct FPRESDIV_W<'a> {
self.bits w: &'a mut W,
} }
} impl<'a> FPRESDIV_W<'a> {
#[doc = r" Value of the field"] #[doc = r"Writes raw bits to the field"]
pub struct FRJWR { #[inline(always)]
bits: u8, pub unsafe fn bits(self, value: u16) -> &'a mut W {
} self.w.bits = (self.w.bits & !(0x03ff << 20)) | (((value as u32) & 0x03ff) << 20);
impl FRJWR { self.w
#[doc = r" Value of the field as raw bits"] }
#[inline] }
pub fn bits(&self) -> u8 { impl R {
self.bits #[doc = "Bits 0:2 - Fast Phase Segment 2"]
} #[inline(always)]
} pub fn fpseg2(&self) -> FPSEG2_R {
#[doc = r" Value of the field"] FPSEG2_R::new((self.bits & 0x07) as u8)
pub struct FPRESDIVR { }
bits: u16, #[doc = "Bits 5:7 - Fast Phase Segment 1"]
} #[inline(always)]
impl FPRESDIVR { pub fn fpseg1(&self) -> FPSEG1_R {
#[doc = r" Value of the field as raw bits"] FPSEG1_R::new(((self.bits >> 5) & 0x07) as u8)
#[inline] }
pub fn bits(&self) -> u16 { #[doc = "Bits 10:14 - Fast Propagation Segment"]
self.bits #[inline(always)]
} pub fn fpropseg(&self) -> FPROPSEG_R {
} FPROPSEG_R::new(((self.bits >> 10) & 0x1f) as u8)
#[doc = r" Proxy"] }
pub struct _FPSEG2W<'a> { #[doc = "Bits 16:18 - Fast Resync Jump Width"]
w: &'a mut W, #[inline(always)]
} pub fn frjw(&self) -> FRJW_R {
impl<'a> _FPSEG2W<'a> { FRJW_R::new(((self.bits >> 16) & 0x07) as u8)
#[doc = r" Writes raw bits to the field"] }
#[inline] #[doc = "Bits 20:29 - Fast Prescaler Division Factor"]
pub unsafe fn bits(self, value: u8) -> &'a mut W { #[inline(always)]
const MASK: u8 = 7; pub fn fpresdiv(&self) -> FPRESDIV_R {
const OFFSET: u8 = 0; FPRESDIV_R::new(((self.bits >> 20) & 0x03ff) as u16)
self.w.bits &= !((MASK as u32) << OFFSET); }
self.w.bits |= ((value & MASK) as u32) << OFFSET; }
self.w impl W {
} #[doc = "Bits 0:2 - Fast Phase Segment 2"]
} #[inline(always)]
#[doc = r" Proxy"] pub fn fpseg2(&mut self) -> FPSEG2_W {
pub struct _FPSEG1W<'a> { FPSEG2_W { w: self }
w: &'a mut W, }
} #[doc = "Bits 5:7 - Fast Phase Segment 1"]
impl<'a> _FPSEG1W<'a> { #[inline(always)]
#[doc = r" Writes raw bits to the field"] pub fn fpseg1(&mut self) -> FPSEG1_W {
#[inline] FPSEG1_W { w: self }
pub unsafe fn bits(self, value: u8) -> &'a mut W { }
const MASK: u8 = 7; #[doc = "Bits 10:14 - Fast Propagation Segment"]
const OFFSET: u8 = 5; #[inline(always)]
self.w.bits &= !((MASK as u32) << OFFSET); pub fn fpropseg(&mut self) -> FPROPSEG_W {
self.w.bits |= ((value & MASK) as u32) << OFFSET; FPROPSEG_W { w: self }
self.w }
} #[doc = "Bits 16:18 - Fast Resync Jump Width"]
} #[inline(always)]
#[doc = r" Proxy"] pub fn frjw(&mut self) -> FRJW_W {
pub struct _FPROPSEGW<'a> { FRJW_W { w: self }
w: &'a mut W, }
} #[doc = "Bits 20:29 - Fast Prescaler Division Factor"]
impl<'a> _FPROPSEGW<'a> { #[inline(always)]
#[doc = r" Writes raw bits to the field"] pub fn fpresdiv(&mut self) -> FPRESDIV_W {
#[inline] FPRESDIV_W { w: self }
pub unsafe fn bits(self, value: u8) -> &'a mut W { }
const MASK: u8 = 31; }
const OFFSET: u8 = 10;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FRJWW<'a> {
w: &'a mut W,
}
impl<'a> _FRJWW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FPRESDIVW<'a> {
w: &'a mut W,
}
impl<'a> _FPRESDIVW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 1023;
const OFFSET: u8 = 20;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:2 - Fast Phase Segment 2"]
#[inline]
pub fn fpseg2(&self) -> FPSEG2R {
let bits = {
const MASK: u8 = 7;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FPSEG2R { bits }
}
#[doc = "Bits 5:7 - Fast Phase Segment 1"]
#[inline]
pub fn fpseg1(&self) -> FPSEG1R {
let bits = {
const MASK: u8 = 7;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FPSEG1R { bits }
}
#[doc = "Bits 10:14 - Fast Propagation Segment"]
#[inline]
pub fn fpropseg(&self) -> FPROPSEGR {
let bits = {
const MASK: u8 = 31;
const OFFSET: u8 = 10;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FPROPSEGR { bits }
}
#[doc = "Bits 16:18 - Fast Resync Jump Width"]
#[inline]
pub fn frjw(&self) -> FRJWR {
let bits = {
const MASK: u8 = 7;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FRJWR { bits }
}
#[doc = "Bits 20:29 - Fast Prescaler Division Factor"]
#[inline]
pub fn fpresdiv(&self) -> FPRESDIVR {
let bits = {
const MASK: u16 = 1023;
const OFFSET: u8 = 20;
((self.bits >> OFFSET) & MASK as u32) as u16
};
FPRESDIVR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:2 - Fast Phase Segment 2"]
#[inline]
pub fn fpseg2(&mut self) -> _FPSEG2W {
_FPSEG2W { w: self }
}
#[doc = "Bits 5:7 - Fast Phase Segment 1"]
#[inline]
pub fn fpseg1(&mut self) -> _FPSEG1W {
_FPSEG1W { w: self }
}
#[doc = "Bits 10:14 - Fast Propagation Segment"]
#[inline]
pub fn fpropseg(&mut self) -> _FPROPSEGW {
_FPROPSEGW { w: self }
}
#[doc = "Bits 16:18 - Fast Resync Jump Width"]
#[inline]
pub fn frjw(&mut self) -> _FRJWW {
_FRJWW { w: self }
}
#[doc = "Bits 20:29 - Fast Prescaler Division Factor"]
#[inline]
pub fn fpresdiv(&mut self) -> _FPRESDIVW {
_FPRESDIVW { w: self }
}
}

78
src/can0/fdcrc.rs
View File

@ -1,60 +1,18 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register FDCRC"]
pub struct R { pub type R = crate::R<u32, super::FDCRC>;
bits: u32, #[doc = "Reader of field `FD_TXCRC`"]
} pub type FD_TXCRC_R = crate::R<u32, u32>;
impl super::FDCRC { #[doc = "Reader of field `FD_MBCRC`"]
#[doc = r" Reads the contents of the register"] pub type FD_MBCRC_R = crate::R<u8, u8>;
#[inline] impl R {
pub fn read(&self) -> R { #[doc = "Bits 0:20 - Extended Transmitted CRC value"]
R { bits: self.register.get() } #[inline(always)]
} pub fn fd_txcrc(&self) -> FD_TXCRC_R {
} FD_TXCRC_R::new((self.bits & 0x001f_ffff) as u32)
#[doc = r" Value of the field"] }
pub struct FD_TXCRCR { #[doc = "Bits 24:30 - CRC Mailbox Number for FD_TXCRC"]
bits: u32, #[inline(always)]
} pub fn fd_mbcrc(&self) -> FD_MBCRC_R {
impl FD_TXCRCR { FD_MBCRC_R::new(((self.bits >> 24) & 0x7f) as u8)
#[doc = r" Value of the field as raw bits"] }
#[inline] }
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct FD_MBCRCR {
bits: u8,
}
impl FD_MBCRCR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:20 - Extended Transmitted CRC value"]
#[inline]
pub fn fd_txcrc(&self) -> FD_TXCRCR {
let bits = {
const MASK: u32 = 2097151;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
FD_TXCRCR { bits }
}
#[doc = "Bits 24:30 - CRC Mailbox Number for FD_TXCRC"]
#[inline]
pub fn fd_mbcrc(&self) -> FD_MBCRCR {
let bits = {
const MASK: u8 = 127;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FD_MBCRCR { bits }
}
}

1022
src/can0/fdctrl.rs
View File

File diff suppressed because it is too large Load Diff

208
src/can0/flt_dlc.rs
View File

@ -1,144 +1,64 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register FLT_DLC"]
pub struct R { pub type R = crate::R<u32, super::FLT_DLC>;
bits: u32, #[doc = "Writer for register FLT_DLC"]
} pub type W = crate::W<u32, super::FLT_DLC>;
#[doc = r" Value to write to the register"] #[doc = "Register FLT_DLC `reset()`'s with value 0x08"]
pub struct W { impl crate::ResetValue for super::FLT_DLC {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::FLT_DLC { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0x08
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `FLT_DLC_HI`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type FLT_DLC_HI_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `FLT_DLC_HI`"]
let bits = self.register.get(); pub struct FLT_DLC_HI_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> FLT_DLC_HI_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] #[doc = "Reader of field `FLT_DLC_LO`"]
#[inline] pub type FLT_DLC_LO_R = crate::R<u8, u8>;
pub fn write<F>(&self, f: F) #[doc = "Write proxy for field `FLT_DLC_LO`"]
where pub struct FLT_DLC_LO_W<'a> {
F: FnOnce(&mut W) -> &mut W, w: &'a mut W,
{ }
let mut w = W::reset_value(); impl<'a> FLT_DLC_LO_W<'a> {
f(&mut w); #[doc = r"Writes raw bits to the field"]
self.register.set(w.bits); #[inline(always)]
} pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[doc = r" Writes the reset value to the register"] self.w.bits = (self.w.bits & !(0x0f << 16)) | (((value as u32) & 0x0f) << 16);
#[inline] self.w
pub fn reset(&self) { }
self.write(|w| w) }
} impl R {
} #[doc = "Bits 0:3 - Upper Limit for Length of Data Bytes Filter"]
#[doc = r" Value of the field"] #[inline(always)]
pub struct FLT_DLC_HIR { pub fn flt_dlc_hi(&self) -> FLT_DLC_HI_R {
bits: u8, FLT_DLC_HI_R::new((self.bits & 0x0f) as u8)
} }
impl FLT_DLC_HIR { #[doc = "Bits 16:19 - Lower Limit for Length of Data Bytes Filter"]
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] pub fn flt_dlc_lo(&self) -> FLT_DLC_LO_R {
pub fn bits(&self) -> u8 { FLT_DLC_LO_R::new(((self.bits >> 16) & 0x0f) as u8)
self.bits }
} }
} impl W {
#[doc = r" Value of the field"] #[doc = "Bits 0:3 - Upper Limit for Length of Data Bytes Filter"]
pub struct FLT_DLC_LOR { #[inline(always)]
bits: u8, pub fn flt_dlc_hi(&mut self) -> FLT_DLC_HI_W {
} FLT_DLC_HI_W { w: self }
impl FLT_DLC_LOR { }
#[doc = r" Value of the field as raw bits"] #[doc = "Bits 16:19 - Lower Limit for Length of Data Bytes Filter"]
#[inline] #[inline(always)]
pub fn bits(&self) -> u8 { pub fn flt_dlc_lo(&mut self) -> FLT_DLC_LO_W {
self.bits FLT_DLC_LO_W { w: self }
} }
} }
#[doc = r" Proxy"]
pub struct _FLT_DLC_HIW<'a> {
w: &'a mut W,
}
impl<'a> _FLT_DLC_HIW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _FLT_DLC_LOW<'a> {
w: &'a mut W,
}
impl<'a> _FLT_DLC_LOW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - Upper Limit for Length of Data Bytes Filter"]
#[inline]
pub fn flt_dlc_hi(&self) -> FLT_DLC_HIR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FLT_DLC_HIR { bits }
}
#[doc = "Bits 16:19 - Lower Limit for Length of Data Bytes Filter"]
#[inline]
pub fn flt_dlc_lo(&self) -> FLT_DLC_LOR {
let bits = {
const MASK: u8 = 15;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
FLT_DLC_LOR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 8 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:3 - Upper Limit for Length of Data Bytes Filter"]
#[inline]
pub fn flt_dlc_hi(&mut self) -> _FLT_DLC_HIW {
_FLT_DLC_HIW { w: self }
}
#[doc = "Bits 16:19 - Lower Limit for Length of Data Bytes Filter"]
#[inline]
pub fn flt_dlc_lo(&mut self) -> _FLT_DLC_LOW {
_FLT_DLC_LOW { w: self }
}
}

551
src/can0/flt_id1.rs
View File

@ -1,341 +1,210 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register FLT_ID1"]
pub struct R { pub type R = crate::R<u32, super::FLT_ID1>;
bits: u32, #[doc = "Writer for register FLT_ID1"]
} pub type W = crate::W<u32, super::FLT_ID1>;
#[doc = r" Value to write to the register"] #[doc = "Register FLT_ID1 `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::FLT_ID1 {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::FLT_ID1 { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `FLT_ID1`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type FLT_ID1_R = crate::R<u32, u32>;
{ #[doc = "Write proxy for field `FLT_ID1`"]
let bits = self.register.get(); pub struct FLT_ID1_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> FLT_ID1_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u32) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x1fff_ffff) | ((value as u32) & 0x1fff_ffff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] #[doc = "Remote Transmission Request Filter\n\nValue on reset: 0"]
#[inline] #[derive(Clone, Copy, Debug, PartialEq)]
pub fn write<F>(&self, f: F) pub enum FLT_RTR_A {
where #[doc = "0: Reject remote frame (accept data frame)"]
F: FnOnce(&mut W) -> &mut W, _0 = 0,
{ #[doc = "1: Accept remote frame"]
let mut w = W::reset_value(); _1 = 1,
f(&mut w); }
self.register.set(w.bits); impl From<FLT_RTR_A> for bool {
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] fn from(variant: FLT_RTR_A) -> Self {
#[inline] variant as u8 != 0
pub fn reset(&self) { }
self.write(|w| w) }
} #[doc = "Reader of field `FLT_RTR`"]
} pub type FLT_RTR_R = crate::R<bool, FLT_RTR_A>;
#[doc = r" Value of the field"] impl FLT_RTR_R {
pub struct FLT_ID1R { #[doc = r"Get enumerated values variant"]
bits: u32, #[inline(always)]
} pub fn variant(&self) -> FLT_RTR_A {
impl FLT_ID1R { match self.bits {
#[doc = r" Value of the field as raw bits"] false => FLT_RTR_A::_0,
#[inline] true => FLT_RTR_A::_1,
pub fn bits(&self) -> u32 { }
self.bits }
} #[doc = "Checks if the value of the field is `_0`"]
} #[inline(always)]
#[doc = "Possible values of the field `FLT_RTR`"] pub fn is_0(&self) -> bool {
#[derive(Clone, Copy, Debug, PartialEq)] *self == FLT_RTR_A::_0
pub enum FLT_RTRR { }
#[doc = "Reject remote frame (accept data frame)"] #[doc = "Checks if the value of the field is `_1`"]
_0, #[inline(always)]
#[doc = "Accept remote frame"] pub fn is_1(&self) -> bool {
_1, *self == FLT_RTR_A::_1
} }
impl FLT_RTRR { }
#[doc = r" Returns `true` if the bit is clear (0)"] #[doc = "Write proxy for field `FLT_RTR`"]
#[inline] pub struct FLT_RTR_W<'a> {
pub fn bit_is_clear(&self) -> bool { w: &'a mut W,
!self.bit() }
} impl<'a> FLT_RTR_W<'a> {
#[doc = r" Returns `true` if the bit is set (1)"] #[doc = r"Writes `variant` to the field"]
#[inline] #[inline(always)]
pub fn bit_is_set(&self) -> bool { pub fn variant(self, variant: FLT_RTR_A) -> &'a mut W {
self.bit() {
} self.bit(variant.into())
#[doc = r" Value of the field as raw bits"] }
#[inline] }
pub fn bit(&self) -> bool { #[doc = "Reject remote frame (accept data frame)"]
match *self { #[inline(always)]
FLT_RTRR::_0 => false, pub fn _0(self) -> &'a mut W {
FLT_RTRR::_1 => true, self.variant(FLT_RTR_A::_0)
} }
} #[doc = "Accept remote frame"]
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] pub fn _1(self) -> &'a mut W {
#[inline] self.variant(FLT_RTR_A::_1)
pub fn _from(value: bool) -> FLT_RTRR { }
match value { #[doc = r"Sets the field bit"]
false => FLT_RTRR::_0, #[inline(always)]
true => FLT_RTRR::_1, pub fn set_bit(self) -> &'a mut W {
} self.bit(true)
} }
#[doc = "Checks if the value of the field is `_0`"] #[doc = r"Clears the field bit"]
#[inline] #[inline(always)]
pub fn is_0(&self) -> bool { pub fn clear_bit(self) -> &'a mut W {
*self == FLT_RTRR::_0 self.bit(false)
} }
#[doc = "Checks if the value of the field is `_1`"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn is_1(&self) -> bool { pub fn bit(self, value: bool) -> &'a mut W {
*self == FLT_RTRR::_1 self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
} self.w
} }
#[doc = "Possible values of the field `FLT_IDE`"] }
#[derive(Clone, Copy, Debug, PartialEq)] #[doc = "ID Extended Filter\n\nValue on reset: 0"]
pub enum FLT_IDER { #[derive(Clone, Copy, Debug, PartialEq)]
#[doc = "Accept standard frame format"] pub enum FLT_IDE_A {
_0, #[doc = "0: Accept standard frame format"]
#[doc = "Accept extended frame format"] _0 = 0,
_1, #[doc = "1: Accept extended frame format"]
} _1 = 1,
impl FLT_IDER { }
#[doc = r" Returns `true` if the bit is clear (0)"] impl From<FLT_IDE_A> for bool {
#[inline] #[inline(always)]
pub fn bit_is_clear(&self) -> bool { fn from(variant: FLT_IDE_A) -> Self {
!self.bit() variant as u8 != 0
} }
#[doc = r" Returns `true` if the bit is set (1)"] }
#[inline] #[doc = "Reader of field `FLT_IDE`"]
pub fn bit_is_set(&self) -> bool { pub type FLT_IDE_R = crate::R<bool, FLT_IDE_A>;
self.bit() impl FLT_IDE_R {
} #[doc = r"Get enumerated values variant"]
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] pub fn variant(&self) -> FLT_IDE_A {
pub fn bit(&self) -> bool { match self.bits {
match *self { false => FLT_IDE_A::_0,
FLT_IDER::_0 => false, true => FLT_IDE_A::_1,
FLT_IDER::_1 => true, }
} }
} #[doc = "Checks if the value of the field is `_0`"]
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] pub fn is_0(&self) -> bool {
#[inline] *self == FLT_IDE_A::_0
pub fn _from(value: bool) -> FLT_IDER { }
match value { #[doc = "Checks if the value of the field is `_1`"]
false => FLT_IDER::_0, #[inline(always)]
true => FLT_IDER::_1, pub fn is_1(&self) -> bool {
} *self == FLT_IDE_A::_1
} }
#[doc = "Checks if the value of the field is `_0`"] }
#[inline] #[doc = "Write proxy for field `FLT_IDE`"]
pub fn is_0(&self) -> bool { pub struct FLT_IDE_W<'a> {
*self == FLT_IDER::_0 w: &'a mut W,
} }
#[doc = "Checks if the value of the field is `_1`"] impl<'a> FLT_IDE_W<'a> {
#[inline] #[doc = r"Writes `variant` to the field"]
pub fn is_1(&self) -> bool { #[inline(always)]
*self == FLT_IDER::_1 pub fn variant(self, variant: FLT_IDE_A) -> &'a mut W {
} {
} self.bit(variant.into())
#[doc = r" Proxy"] }
pub struct _FLT_ID1W<'a> { }
w: &'a mut W, #[doc = "Accept standard frame format"]
} #[inline(always)]
impl<'a> _FLT_ID1W<'a> { pub fn _0(self) -> &'a mut W {
#[doc = r" Writes raw bits to the field"] self.variant(FLT_IDE_A::_0)
#[inline] }
pub unsafe fn bits(self, value: u32) -> &'a mut W { #[doc = "Accept extended frame format"]
const MASK: u32 = 536870911; #[inline(always)]
const OFFSET: u8 = 0; pub fn _1(self) -> &'a mut W {
self.w.bits &= !((MASK as u32) << OFFSET); self.variant(FLT_IDE_A::_1)
self.w.bits |= ((value & MASK) as u32) << OFFSET; }
self.w #[doc = r"Sets the field bit"]
} #[inline(always)]
} pub fn set_bit(self) -> &'a mut W {
#[doc = "Values that can be written to the field `FLT_RTR`"] self.bit(true)
pub enum FLT_RTRW { }
#[doc = "Reject remote frame (accept data frame)"] #[doc = r"Clears the field bit"]
_0, #[inline(always)]
#[doc = "Accept remote frame"] pub fn clear_bit(self) -> &'a mut W {
_1, self.bit(false)
} }
impl FLT_RTRW { #[doc = r"Writes raw bits to the field"]
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] pub fn bit(self, value: bool) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
pub fn _bits(&self) -> bool { self.w
match *self { }
FLT_RTRW::_0 => false, }
FLT_RTRW::_1 => true, impl R {
} #[doc = "Bits 0:28 - ID Filter 1 for Pretended Networking filtering"]
} #[inline(always)]
} pub fn flt_id1(&self) -> FLT_ID1_R {
#[doc = r" Proxy"] FLT_ID1_R::new((self.bits & 0x1fff_ffff) as u32)
pub struct _FLT_RTRW<'a> { }
w: &'a mut W, #[doc = "Bit 29 - Remote Transmission Request Filter"]
} #[inline(always)]
impl<'a> _FLT_RTRW<'a> { pub fn flt_rtr(&self) -> FLT_RTR_R {
#[doc = r" Writes `variant` to the field"] FLT_RTR_R::new(((self.bits >> 29) & 0x01) != 0)
#[inline] }
pub fn variant(self, variant: FLT_RTRW) -> &'a mut W { #[doc = "Bit 30 - ID Extended Filter"]
{ #[inline(always)]
self.bit(variant._bits()) pub fn flt_ide(&self) -> FLT_IDE_R {
} FLT_IDE_R::new(((self.bits >> 30) & 0x01) != 0)
} }
#[doc = "Reject remote frame (accept data frame)"] }
#[inline] impl W {
pub fn _0(self) -> &'a mut W { #[doc = "Bits 0:28 - ID Filter 1 for Pretended Networking filtering"]
self.variant(FLT_RTRW::_0) #[inline(always)]
} pub fn flt_id1(&mut self) -> FLT_ID1_W {
#[doc = "Accept remote frame"] FLT_ID1_W { w: self }
#[inline] }
pub fn _1(self) -> &'a mut W { #[doc = "Bit 29 - Remote Transmission Request Filter"]
self.variant(FLT_RTRW::_1) #[inline(always)]
} pub fn flt_rtr(&mut self) -> FLT_RTR_W {
#[doc = r" Sets the field bit"] FLT_RTR_W { w: self }
pub fn set_bit(self) -> &'a mut W { }
self.bit(true) #[doc = "Bit 30 - ID Extended Filter"]
} #[inline(always)]
#[doc = r" Clears the field bit"] pub fn flt_ide(&mut self) -> FLT_IDE_W {
pub fn clear_bit(self) -> &'a mut W { FLT_IDE_W { w: self }
self.bit(false) }
} }
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `FLT_IDE`"]
pub enum FLT_IDEW {
#[doc = "Accept standard frame format"]
_0,
#[doc = "Accept extended frame format"]
_1,
}
impl FLT_IDEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
FLT_IDEW::_0 => false,
FLT_IDEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _FLT_IDEW<'a> {
w: &'a mut W,
}
impl<'a> _FLT_IDEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FLT_IDEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Accept standard frame format"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FLT_IDEW::_0)
}
#[doc = "Accept extended frame format"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FLT_IDEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:28 - ID Filter 1 for Pretended Networking filtering"]
#[inline]
pub fn flt_id1(&self) -> FLT_ID1R {
let bits = {
const MASK: u32 = 536870911;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
FLT_ID1R { bits }
}
#[doc = "Bit 29 - Remote Transmission Request Filter"]
#[inline]
pub fn flt_rtr(&self) -> FLT_RTRR {
FLT_RTRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 30 - ID Extended Filter"]
#[inline]
pub fn flt_ide(&self) -> FLT_IDER {
FLT_IDER::_from({
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:28 - ID Filter 1 for Pretended Networking filtering"]
#[inline]
pub fn flt_id1(&mut self) -> _FLT_ID1W {
_FLT_ID1W { w: self }
}
#[doc = "Bit 29 - Remote Transmission Request Filter"]
#[inline]
pub fn flt_rtr(&mut self) -> _FLT_RTRW {
_FLT_RTRW { w: self }
}
#[doc = "Bit 30 - ID Extended Filter"]
#[inline]
pub fn flt_ide(&mut self) -> _FLT_IDEW {
_FLT_IDEW { w: self }
}
}

551
src/can0/flt_id2_idmask.rs
View File

@ -1,341 +1,210 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register FLT_ID2_IDMASK"]
pub struct R { pub type R = crate::R<u32, super::FLT_ID2_IDMASK>;
bits: u32, #[doc = "Writer for register FLT_ID2_IDMASK"]
} pub type W = crate::W<u32, super::FLT_ID2_IDMASK>;
#[doc = r" Value to write to the register"] #[doc = "Register FLT_ID2_IDMASK `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::FLT_ID2_IDMASK {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::FLT_ID2_IDMASK { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `FLT_ID2_IDMASK`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type FLT_ID2_IDMASK_R = crate::R<u32, u32>;
{ #[doc = "Write proxy for field `FLT_ID2_IDMASK`"]
let bits = self.register.get(); pub struct FLT_ID2_IDMASK_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> FLT_ID2_IDMASK_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u32) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0x1fff_ffff) | ((value as u32) & 0x1fff_ffff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] #[doc = "Remote Transmission Request Mask Bit\n\nValue on reset: 0"]
#[inline] #[derive(Clone, Copy, Debug, PartialEq)]
pub fn write<F>(&self, f: F) pub enum RTR_MSK_A {
where #[doc = "0: The corresponding bit in the filter is \"don't care\""]
F: FnOnce(&mut W) -> &mut W, _0 = 0,
{ #[doc = "1: The corresponding bit in the filter is checked"]
let mut w = W::reset_value(); _1 = 1,
f(&mut w); }
self.register.set(w.bits); impl From<RTR_MSK_A> for bool {
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] fn from(variant: RTR_MSK_A) -> Self {
#[inline] variant as u8 != 0
pub fn reset(&self) { }
self.write(|w| w) }
} #[doc = "Reader of field `RTR_MSK`"]
} pub type RTR_MSK_R = crate::R<bool, RTR_MSK_A>;
#[doc = r" Value of the field"] impl RTR_MSK_R {
pub struct FLT_ID2_IDMASKR { #[doc = r"Get enumerated values variant"]
bits: u32, #[inline(always)]
} pub fn variant(&self) -> RTR_MSK_A {
impl FLT_ID2_IDMASKR { match self.bits {
#[doc = r" Value of the field as raw bits"] false => RTR_MSK_A::_0,
#[inline] true => RTR_MSK_A::_1,
pub fn bits(&self) -> u32 { }
self.bits }
} #[doc = "Checks if the value of the field is `_0`"]
} #[inline(always)]
#[doc = "Possible values of the field `RTR_MSK`"] pub fn is_0(&self) -> bool {
#[derive(Clone, Copy, Debug, PartialEq)] *self == RTR_MSK_A::_0
pub enum RTR_MSKR { }
#[doc = "The corresponding bit in the filter is \"don't care\""] #[doc = "Checks if the value of the field is `_1`"]
_0, #[inline(always)]
#[doc = "The corresponding bit in the filter is checked"] pub fn is_1(&self) -> bool {
_1, *self == RTR_MSK_A::_1
} }
impl RTR_MSKR { }
#[doc = r" Returns `true` if the bit is clear (0)"] #[doc = "Write proxy for field `RTR_MSK`"]
#[inline] pub struct RTR_MSK_W<'a> {
pub fn bit_is_clear(&self) -> bool { w: &'a mut W,
!self.bit() }
} impl<'a> RTR_MSK_W<'a> {
#[doc = r" Returns `true` if the bit is set (1)"] #[doc = r"Writes `variant` to the field"]
#[inline] #[inline(always)]
pub fn bit_is_set(&self) -> bool { pub fn variant(self, variant: RTR_MSK_A) -> &'a mut W {
self.bit() {
} self.bit(variant.into())
#[doc = r" Value of the field as raw bits"] }
#[inline] }
pub fn bit(&self) -> bool { #[doc = "The corresponding bit in the filter is \"don't care\""]
match *self { #[inline(always)]
RTR_MSKR::_0 => false, pub fn _0(self) -> &'a mut W {
RTR_MSKR::_1 => true, self.variant(RTR_MSK_A::_0)
} }
} #[doc = "The corresponding bit in the filter is checked"]
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] pub fn _1(self) -> &'a mut W {
#[inline] self.variant(RTR_MSK_A::_1)
pub fn _from(value: bool) -> RTR_MSKR { }
match value { #[doc = r"Sets the field bit"]
false => RTR_MSKR::_0, #[inline(always)]
true => RTR_MSKR::_1, pub fn set_bit(self) -> &'a mut W {
} self.bit(true)
} }
#[doc = "Checks if the value of the field is `_0`"] #[doc = r"Clears the field bit"]
#[inline] #[inline(always)]
pub fn is_0(&self) -> bool { pub fn clear_bit(self) -> &'a mut W {
*self == RTR_MSKR::_0 self.bit(false)
} }
#[doc = "Checks if the value of the field is `_1`"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn is_1(&self) -> bool { pub fn bit(self, value: bool) -> &'a mut W {
*self == RTR_MSKR::_1 self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
} self.w
} }
#[doc = "Possible values of the field `IDE_MSK`"] }
#[derive(Clone, Copy, Debug, PartialEq)] #[doc = "ID Extended Mask Bit\n\nValue on reset: 0"]
pub enum IDE_MSKR { #[derive(Clone, Copy, Debug, PartialEq)]
#[doc = "The corresponding bit in the filter is \"don't care\""] pub enum IDE_MSK_A {
_0, #[doc = "0: The corresponding bit in the filter is \"don't care\""]
#[doc = "The corresponding bit in the filter is checked"] _0 = 0,
_1, #[doc = "1: The corresponding bit in the filter is checked"]
} _1 = 1,
impl IDE_MSKR { }
#[doc = r" Returns `true` if the bit is clear (0)"] impl From<IDE_MSK_A> for bool {
#[inline] #[inline(always)]
pub fn bit_is_clear(&self) -> bool { fn from(variant: IDE_MSK_A) -> Self {
!self.bit() variant as u8 != 0
} }
#[doc = r" Returns `true` if the bit is set (1)"] }
#[inline] #[doc = "Reader of field `IDE_MSK`"]
pub fn bit_is_set(&self) -> bool { pub type IDE_MSK_R = crate::R<bool, IDE_MSK_A>;
self.bit() impl IDE_MSK_R {
} #[doc = r"Get enumerated values variant"]
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] pub fn variant(&self) -> IDE_MSK_A {
pub fn bit(&self) -> bool { match self.bits {
match *self { false => IDE_MSK_A::_0,
IDE_MSKR::_0 => false, true => IDE_MSK_A::_1,
IDE_MSKR::_1 => true, }
} }
} #[doc = "Checks if the value of the field is `_0`"]
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] pub fn is_0(&self) -> bool {
#[inline] *self == IDE_MSK_A::_0
pub fn _from(value: bool) -> IDE_MSKR { }
match value { #[doc = "Checks if the value of the field is `_1`"]
false => IDE_MSKR::_0, #[inline(always)]
true => IDE_MSKR::_1, pub fn is_1(&self) -> bool {
} *self == IDE_MSK_A::_1
} }
#[doc = "Checks if the value of the field is `_0`"] }
#[inline] #[doc = "Write proxy for field `IDE_MSK`"]
pub fn is_0(&self) -> bool { pub struct IDE_MSK_W<'a> {
*self == IDE_MSKR::_0 w: &'a mut W,
} }
#[doc = "Checks if the value of the field is `_1`"] impl<'a> IDE_MSK_W<'a> {
#[inline] #[doc = r"Writes `variant` to the field"]
pub fn is_1(&self) -> bool { #[inline(always)]
*self == IDE_MSKR::_1 pub fn variant(self, variant: IDE_MSK_A) -> &'a mut W {
} {
} self.bit(variant.into())
#[doc = r" Proxy"] }
pub struct _FLT_ID2_IDMASKW<'a> { }
w: &'a mut W, #[doc = "The corresponding bit in the filter is \"don't care\""]
} #[inline(always)]
impl<'a> _FLT_ID2_IDMASKW<'a> { pub fn _0(self) -> &'a mut W {
#[doc = r" Writes raw bits to the field"] self.variant(IDE_MSK_A::_0)
#[inline] }
pub unsafe fn bits(self, value: u32) -> &'a mut W { #[doc = "The corresponding bit in the filter is checked"]
const MASK: u32 = 536870911; #[inline(always)]
const OFFSET: u8 = 0; pub fn _1(self) -> &'a mut W {
self.w.bits &= !((MASK as u32) << OFFSET); self.variant(IDE_MSK_A::_1)
self.w.bits |= ((value & MASK) as u32) << OFFSET; }
self.w #[doc = r"Sets the field bit"]
} #[inline(always)]
} pub fn set_bit(self) -> &'a mut W {
#[doc = "Values that can be written to the field `RTR_MSK`"] self.bit(true)
pub enum RTR_MSKW { }
#[doc = "The corresponding bit in the filter is \"don't care\""] #[doc = r"Clears the field bit"]
_0, #[inline(always)]
#[doc = "The corresponding bit in the filter is checked"] pub fn clear_bit(self) -> &'a mut W {
_1, self.bit(false)
} }
impl RTR_MSKW { #[doc = r"Writes raw bits to the field"]
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] pub fn bit(self, value: bool) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
pub fn _bits(&self) -> bool { self.w
match *self { }
RTR_MSKW::_0 => false, }
RTR_MSKW::_1 => true, impl R {
} #[doc = "Bits 0:28 - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering"]
} #[inline(always)]
} pub fn flt_id2_idmask(&self) -> FLT_ID2_IDMASK_R {
#[doc = r" Proxy"] FLT_ID2_IDMASK_R::new((self.bits & 0x1fff_ffff) as u32)
pub struct _RTR_MSKW<'a> { }
w: &'a mut W, #[doc = "Bit 29 - Remote Transmission Request Mask Bit"]
} #[inline(always)]
impl<'a> _RTR_MSKW<'a> { pub fn rtr_msk(&self) -> RTR_MSK_R {
#[doc = r" Writes `variant` to the field"] RTR_MSK_R::new(((self.bits >> 29) & 0x01) != 0)
#[inline] }
pub fn variant(self, variant: RTR_MSKW) -> &'a mut W { #[doc = "Bit 30 - ID Extended Mask Bit"]
{ #[inline(always)]
self.bit(variant._bits()) pub fn ide_msk(&self) -> IDE_MSK_R {
} IDE_MSK_R::new(((self.bits >> 30) & 0x01) != 0)
} }
#[doc = "The corresponding bit in the filter is \"don't care\""] }
#[inline] impl W {
pub fn _0(self) -> &'a mut W { #[doc = "Bits 0:28 - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering"]
self.variant(RTR_MSKW::_0) #[inline(always)]
} pub fn flt_id2_idmask(&mut self) -> FLT_ID2_IDMASK_W {
#[doc = "The corresponding bit in the filter is checked"] FLT_ID2_IDMASK_W { w: self }
#[inline] }
pub fn _1(self) -> &'a mut W { #[doc = "Bit 29 - Remote Transmission Request Mask Bit"]
self.variant(RTR_MSKW::_1) #[inline(always)]
} pub fn rtr_msk(&mut self) -> RTR_MSK_W {
#[doc = r" Sets the field bit"] RTR_MSK_W { w: self }
pub fn set_bit(self) -> &'a mut W { }
self.bit(true) #[doc = "Bit 30 - ID Extended Mask Bit"]
} #[inline(always)]
#[doc = r" Clears the field bit"] pub fn ide_msk(&mut self) -> IDE_MSK_W {
pub fn clear_bit(self) -> &'a mut W { IDE_MSK_W { w: self }
self.bit(false) }
} }
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 29;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `IDE_MSK`"]
pub enum IDE_MSKW {
#[doc = "The corresponding bit in the filter is \"don't care\""]
_0,
#[doc = "The corresponding bit in the filter is checked"]
_1,
}
impl IDE_MSKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
IDE_MSKW::_0 => false,
IDE_MSKW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _IDE_MSKW<'a> {
w: &'a mut W,
}
impl<'a> _IDE_MSKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: IDE_MSKW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "The corresponding bit in the filter is \"don't care\""]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(IDE_MSKW::_0)
}
#[doc = "The corresponding bit in the filter is checked"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(IDE_MSKW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 30;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:28 - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering"]
#[inline]
pub fn flt_id2_idmask(&self) -> FLT_ID2_IDMASKR {
let bits = {
const MASK: u32 = 536870911;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
FLT_ID2_IDMASKR { bits }
}
#[doc = "Bit 29 - Remote Transmission Request Mask Bit"]
#[inline]
pub fn rtr_msk(&self) -> RTR_MSKR {
RTR_MSKR::_from({
const MASK: bool = true;
const OFFSET: u8 = 29;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 30 - ID Extended Mask Bit"]
#[inline]
pub fn ide_msk(&self) -> IDE_MSKR {
IDE_MSKR::_from({
const MASK: bool = true;
const OFFSET: u8 = 30;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:28 - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering"]
#[inline]
pub fn flt_id2_idmask(&mut self) -> _FLT_ID2_IDMASKW {
_FLT_ID2_IDMASKW { w: self }
}
#[doc = "Bit 29 - Remote Transmission Request Mask Bit"]
#[inline]
pub fn rtr_msk(&mut self) -> _RTR_MSKW {
_RTR_MSKW { w: self }
}
#[doc = "Bit 30 - ID Extended Mask Bit"]
#[inline]
pub fn ide_msk(&mut self) -> _IDE_MSKW {
_IDE_MSKW { w: self }
}
}

736
src/can0/iflag1.rs
View File

@ -1,620 +1,408 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register IFLAG1"]
pub struct R { pub type R = crate::R<u32, super::IFLAG1>;
bits: u32, #[doc = "Writer for register IFLAG1"]
} pub type W = crate::W<u32, super::IFLAG1>;
#[doc = r" Value to write to the register"] #[doc = "Register IFLAG1 `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::IFLAG1 {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::IFLAG1 { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
} }
} }
#[doc = "Possible values of the field `BUF0I`"] #[doc = "Buffer MB0 Interrupt Or Clear FIFO bit\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)] #[derive(Clone, Copy, Debug, PartialEq)]
pub enum BUF0IR { pub enum BUF0I_A {
#[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR\\[RFEN\\]=0."] #[doc = "0: The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR\\[RFEN\\]=0."]
_0, _0 = 0,
#[doc = "The corresponding buffer has successfully completed transmission or reception when MCR\\[RFEN\\]=0."] #[doc = "1: The corresponding buffer has successfully completed transmission or reception when MCR\\[RFEN\\]=0."]
_1, _1 = 1,
} }
impl BUF0IR { impl From<BUF0I_A> for bool {
#[doc = r" Returns `true` if the bit is clear (0)"] #[inline(always)]
#[inline] fn from(variant: BUF0I_A) -> Self {
pub fn bit_is_clear(&self) -> bool { variant as u8 != 0
!self.bit()
} }
#[doc = r" Returns `true` if the bit is set (1)"] }
#[inline] #[doc = "Reader of field `BUF0I`"]
pub fn bit_is_set(&self) -> bool { pub type BUF0I_R = crate::R<bool, BUF0I_A>;
self.bit() impl BUF0I_R {
} #[doc = r"Get enumerated values variant"]
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] pub fn variant(&self) -> BUF0I_A {
pub fn bit(&self) -> bool { match self.bits {
match *self { false => BUF0I_A::_0,
BUF0IR::_0 => false, true => BUF0I_A::_1,
BUF0IR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BUF0IR {
match value {
false => BUF0IR::_0,
true => BUF0IR::_1,
} }
} }
#[doc = "Checks if the value of the field is `_0`"] #[doc = "Checks if the value of the field is `_0`"]
#[inline] #[inline(always)]
pub fn is_0(&self) -> bool { pub fn is_0(&self) -> bool {
*self == BUF0IR::_0 *self == BUF0I_A::_0
} }
#[doc = "Checks if the value of the field is `_1`"] #[doc = "Checks if the value of the field is `_1`"]
#[inline] #[inline(always)]
pub fn is_1(&self) -> bool { pub fn is_1(&self) -> bool {
*self == BUF0IR::_1 *self == BUF0I_A::_1
} }
} }
#[doc = r" Value of the field"] #[doc = "Write proxy for field `BUF0I`"]
pub struct BUF4TO1IR { pub struct BUF0I_W<'a> {
bits: u8,
}
impl BUF4TO1IR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Possible values of the field `BUF5I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BUF5IR {
#[doc = "No occurrence of MB5 completing transmission/reception when MCR\\[RFEN\\]=0, or of frame(s) available in the FIFO, when MCR\\[RFEN\\]=1"]
_0,
#[doc = "MB5 completed transmission/reception when MCR\\[RFEN\\]=0, or frame(s) available in the Rx FIFO when MCR\\[RFEN\\]=1. It generates a DMA request in case of MCR\\[RFEN\\] and MCR\\[DMA\\] are enabled."]
_1,
}
impl BUF5IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BUF5IR::_0 => false,
BUF5IR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BUF5IR {
match value {
false => BUF5IR::_0,
true => BUF5IR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == BUF5IR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == BUF5IR::_1
}
}
#[doc = "Possible values of the field `BUF6I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BUF6IR {
#[doc = "No occurrence of MB6 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO almost full when MCR\\[RFEN\\]=1"]
_0,
#[doc = "MB6 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO almost full when MCR\\[RFEN\\]=1"]
_1,
}
impl BUF6IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BUF6IR::_0 => false,
BUF6IR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BUF6IR {
match value {
false => BUF6IR::_0,
true => BUF6IR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == BUF6IR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == BUF6IR::_1
}
}
#[doc = "Possible values of the field `BUF7I`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum BUF7IR {
#[doc = "No occurrence of MB7 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO overflow when MCR\\[RFEN\\]=1"]
_0,
#[doc = "MB7 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO overflow when MCR\\[RFEN\\]=1"]
_1,
}
impl BUF7IR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
BUF7IR::_0 => false,
BUF7IR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> BUF7IR {
match value {
false => BUF7IR::_0,
true => BUF7IR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == BUF7IR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == BUF7IR::_1
}
}
#[doc = r" Value of the field"]
pub struct BUF31TO8IR {
bits: u32,
}
impl BUF31TO8IR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = "Values that can be written to the field `BUF0I`"]
pub enum BUF0IW {
#[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR\\[RFEN\\]=0."]
_0,
#[doc = "The corresponding buffer has successfully completed transmission or reception when MCR\\[RFEN\\]=0."]
_1,
}
impl BUF0IW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
BUF0IW::_0 => false,
BUF0IW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _BUF0IW<'a> {
w: &'a mut W, w: &'a mut W,
} }
impl<'a> _BUF0IW<'a> { impl<'a> BUF0I_W<'a> {
#[doc = r" Writes `variant` to the field"] #[doc = r"Writes `variant` to the field"]
#[inline] #[inline(always)]
pub fn variant(self, variant: BUF0IW) -> &'a mut W { pub fn variant(self, variant: BUF0I_A) -> &'a mut W {
{ {
self.bit(variant._bits()) self.bit(variant.into())
} }
} }
#[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR\\[RFEN\\]=0."] #[doc = "The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR\\[RFEN\\]=0."]
#[inline] #[inline(always)]
pub fn _0(self) -> &'a mut W { pub fn _0(self) -> &'a mut W {
self.variant(BUF0IW::_0) self.variant(BUF0I_A::_0)
} }
#[doc = "The corresponding buffer has successfully completed transmission or reception when MCR\\[RFEN\\]=0."] #[doc = "The corresponding buffer has successfully completed transmission or reception when MCR\\[RFEN\\]=0."]
#[inline] #[inline(always)]
pub fn _1(self) -> &'a mut W { pub fn _1(self) -> &'a mut W {
self.variant(BUF0IW::_1) self.variant(BUF0I_A::_1)
} }
#[doc = r" Sets the field bit"] #[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W { pub fn set_bit(self) -> &'a mut W {
self.bit(true) self.bit(true)
} }
#[doc = r" Clears the field bit"] #[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W { pub fn clear_bit(self) -> &'a mut W {
self.bit(false) self.bit(false)
} }
#[doc = r" Writes raw bits to the field"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W { pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true; self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w self.w
} }
} }
#[doc = r" Proxy"] #[doc = "Reader of field `BUF4TO1I`"]
pub struct _BUF4TO1IW<'a> { pub type BUF4TO1I_R = crate::R<u8, u8>;
#[doc = "Write proxy for field `BUF4TO1I`"]
pub struct BUF4TO1I_W<'a> {
w: &'a mut W, w: &'a mut W,
} }
impl<'a> _BUF4TO1IW<'a> { impl<'a> BUF4TO1I_W<'a> {
#[doc = r" Writes raw bits to the field"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W { pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15; self.w.bits = (self.w.bits & !(0x0f << 1)) | (((value as u32) & 0x0f) << 1);
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w self.w
} }
} }
#[doc = "Values that can be written to the field `BUF5I`"] #[doc = "Buffer MB5 Interrupt Or \"Frames available in Rx FIFO\"\n\nValue on reset: 0"]
pub enum BUF5IW { #[derive(Clone, Copy, Debug, PartialEq)]
#[doc = "No occurrence of MB5 completing transmission/reception when MCR\\[RFEN\\]=0, or of frame(s) available in the FIFO, when MCR\\[RFEN\\]=1"] pub enum BUF5I_A {
_0, #[doc = "0: No occurrence of MB5 completing transmission/reception when MCR\\[RFEN\\]=0, or of frame(s) available in the FIFO, when MCR\\[RFEN\\]=1"]
#[doc = "MB5 completed transmission/reception when MCR\\[RFEN\\]=0, or frame(s) available in the Rx FIFO when MCR\\[RFEN\\]=1. It generates a DMA request in case of MCR\\[RFEN\\] and MCR\\[DMA\\] are enabled."] _0 = 0,
_1, #[doc = "1: MB5 completed transmission/reception when MCR\\[RFEN\\]=0, or frame(s) available in the Rx FIFO when MCR\\[RFEN\\]=1. It generates a DMA request in case of MCR\\[RFEN\\]
and MCR\\[DMA\\]
are enabled."]
_1 = 1,
} }
impl BUF5IW { impl From<BUF5I_A> for bool {
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] fn from(variant: BUF5I_A) -> Self {
#[inline] variant as u8 != 0
pub fn _bits(&self) -> bool {
match *self {
BUF5IW::_0 => false,
BUF5IW::_1 => true,
}
} }
} }
#[doc = r" Proxy"] #[doc = "Reader of field `BUF5I`"]
pub struct _BUF5IW<'a> { pub type BUF5I_R = crate::R<bool, BUF5I_A>;
impl BUF5I_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> BUF5I_A {
match self.bits {
false => BUF5I_A::_0,
true => BUF5I_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == BUF5I_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == BUF5I_A::_1
}
}
#[doc = "Write proxy for field `BUF5I`"]
pub struct BUF5I_W<'a> {
w: &'a mut W, w: &'a mut W,
} }
impl<'a> _BUF5IW<'a> { impl<'a> BUF5I_W<'a> {
#[doc = r" Writes `variant` to the field"] #[doc = r"Writes `variant` to the field"]
#[inline] #[inline(always)]
pub fn variant(self, variant: BUF5IW) -> &'a mut W { pub fn variant(self, variant: BUF5I_A) -> &'a mut W {
{ {
self.bit(variant._bits()) self.bit(variant.into())
} }
} }
#[doc = "No occurrence of MB5 completing transmission/reception when MCR\\[RFEN\\]=0, or of frame(s) available in the FIFO, when MCR\\[RFEN\\]=1"] #[doc = "No occurrence of MB5 completing transmission/reception when MCR\\[RFEN\\]=0, or of frame(s) available in the FIFO, when MCR\\[RFEN\\]=1"]
#[inline] #[inline(always)]
pub fn _0(self) -> &'a mut W { pub fn _0(self) -> &'a mut W {
self.variant(BUF5IW::_0) self.variant(BUF5I_A::_0)
} }
#[doc = "MB5 completed transmission/reception when MCR\\[RFEN\\]=0, or frame(s) available in the Rx FIFO when MCR\\[RFEN\\]=1. It generates a DMA request in case of MCR\\[RFEN\\] and MCR\\[DMA\\] are enabled."] #[doc = "MB5 completed transmission/reception when MCR\\[RFEN\\]=0, or frame(s) available in the Rx FIFO when MCR\\[RFEN\\]=1. It generates a DMA request in case of MCR\\[RFEN\\]
#[inline] and MCR\\[DMA\\]
are enabled."]
#[inline(always)]
pub fn _1(self) -> &'a mut W { pub fn _1(self) -> &'a mut W {
self.variant(BUF5IW::_1) self.variant(BUF5I_A::_1)
} }
#[doc = r" Sets the field bit"] #[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W { pub fn set_bit(self) -> &'a mut W {
self.bit(true) self.bit(true)
} }
#[doc = r" Clears the field bit"] #[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W { pub fn clear_bit(self) -> &'a mut W {
self.bit(false) self.bit(false)
} }
#[doc = r" Writes raw bits to the field"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W { pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true; self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
const OFFSET: u8 = 5;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w self.w
} }
} }
#[doc = "Values that can be written to the field `BUF6I`"] #[doc = "Buffer MB6 Interrupt Or \"Rx FIFO Warning\"\n\nValue on reset: 0"]
pub enum BUF6IW { #[derive(Clone, Copy, Debug, PartialEq)]
#[doc = "No occurrence of MB6 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO almost full when MCR\\[RFEN\\]=1"] pub enum BUF6I_A {
_0, #[doc = "0: No occurrence of MB6 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO almost full when MCR\\[RFEN\\]=1"]
#[doc = "MB6 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO almost full when MCR\\[RFEN\\]=1"] _0 = 0,
_1, #[doc = "1: MB6 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO almost full when MCR\\[RFEN\\]=1"]
_1 = 1,
} }
impl BUF6IW { impl From<BUF6I_A> for bool {
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] fn from(variant: BUF6I_A) -> Self {
#[inline] variant as u8 != 0
pub fn _bits(&self) -> bool {
match *self {
BUF6IW::_0 => false,
BUF6IW::_1 => true,
}
} }
} }
#[doc = r" Proxy"] #[doc = "Reader of field `BUF6I`"]
pub struct _BUF6IW<'a> { pub type BUF6I_R = crate::R<bool, BUF6I_A>;
impl BUF6I_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> BUF6I_A {
match self.bits {
false => BUF6I_A::_0,
true => BUF6I_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == BUF6I_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == BUF6I_A::_1
}
}
#[doc = "Write proxy for field `BUF6I`"]
pub struct BUF6I_W<'a> {
w: &'a mut W, w: &'a mut W,
} }
impl<'a> _BUF6IW<'a> { impl<'a> BUF6I_W<'a> {
#[doc = r" Writes `variant` to the field"] #[doc = r"Writes `variant` to the field"]
#[inline] #[inline(always)]
pub fn variant(self, variant: BUF6IW) -> &'a mut W { pub fn variant(self, variant: BUF6I_A) -> &'a mut W {
{ {
self.bit(variant._bits()) self.bit(variant.into())
} }
} }
#[doc = "No occurrence of MB6 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO almost full when MCR\\[RFEN\\]=1"] #[doc = "No occurrence of MB6 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO almost full when MCR\\[RFEN\\]=1"]
#[inline] #[inline(always)]
pub fn _0(self) -> &'a mut W { pub fn _0(self) -> &'a mut W {
self.variant(BUF6IW::_0) self.variant(BUF6I_A::_0)
} }
#[doc = "MB6 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO almost full when MCR\\[RFEN\\]=1"] #[doc = "MB6 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO almost full when MCR\\[RFEN\\]=1"]
#[inline] #[inline(always)]
pub fn _1(self) -> &'a mut W { pub fn _1(self) -> &'a mut W {
self.variant(BUF6IW::_1) self.variant(BUF6I_A::_1)
} }
#[doc = r" Sets the field bit"] #[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W { pub fn set_bit(self) -> &'a mut W {
self.bit(true) self.bit(true)
} }
#[doc = r" Clears the field bit"] #[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W { pub fn clear_bit(self) -> &'a mut W {
self.bit(false) self.bit(false)
} }
#[doc = r" Writes raw bits to the field"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W { pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true; self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w self.w
} }
} }
#[doc = "Values that can be written to the field `BUF7I`"] #[doc = "Buffer MB7 Interrupt Or \"Rx FIFO Overflow\"\n\nValue on reset: 0"]
pub enum BUF7IW { #[derive(Clone, Copy, Debug, PartialEq)]
#[doc = "No occurrence of MB7 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO overflow when MCR\\[RFEN\\]=1"] pub enum BUF7I_A {
_0, #[doc = "0: No occurrence of MB7 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO overflow when MCR\\[RFEN\\]=1"]
#[doc = "MB7 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO overflow when MCR\\[RFEN\\]=1"] _0 = 0,
_1, #[doc = "1: MB7 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO overflow when MCR\\[RFEN\\]=1"]
_1 = 1,
} }
impl BUF7IW { impl From<BUF7I_A> for bool {
#[allow(missing_docs)] #[inline(always)]
#[doc(hidden)] fn from(variant: BUF7I_A) -> Self {
#[inline] variant as u8 != 0
pub fn _bits(&self) -> bool {
match *self {
BUF7IW::_0 => false,
BUF7IW::_1 => true,
}
} }
} }
#[doc = r" Proxy"] #[doc = "Reader of field `BUF7I`"]
pub struct _BUF7IW<'a> { pub type BUF7I_R = crate::R<bool, BUF7I_A>;
impl BUF7I_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> BUF7I_A {
match self.bits {
false => BUF7I_A::_0,
true => BUF7I_A::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline(always)]
pub fn is_0(&self) -> bool {
*self == BUF7I_A::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline(always)]
pub fn is_1(&self) -> bool {
*self == BUF7I_A::_1
}
}
#[doc = "Write proxy for field `BUF7I`"]
pub struct BUF7I_W<'a> {
w: &'a mut W, w: &'a mut W,
} }
impl<'a> _BUF7IW<'a> { impl<'a> BUF7I_W<'a> {
#[doc = r" Writes `variant` to the field"] #[doc = r"Writes `variant` to the field"]
#[inline] #[inline(always)]
pub fn variant(self, variant: BUF7IW) -> &'a mut W { pub fn variant(self, variant: BUF7I_A) -> &'a mut W {
{ {
self.bit(variant._bits()) self.bit(variant.into())
} }
} }
#[doc = "No occurrence of MB7 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO overflow when MCR\\[RFEN\\]=1"] #[doc = "No occurrence of MB7 completing transmission/reception when MCR\\[RFEN\\]=0, or of Rx FIFO overflow when MCR\\[RFEN\\]=1"]
#[inline] #[inline(always)]
pub fn _0(self) -> &'a mut W { pub fn _0(self) -> &'a mut W {
self.variant(BUF7IW::_0) self.variant(BUF7I_A::_0)
} }
#[doc = "MB7 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO overflow when MCR\\[RFEN\\]=1"] #[doc = "MB7 completed transmission/reception when MCR\\[RFEN\\]=0, or Rx FIFO overflow when MCR\\[RFEN\\]=1"]
#[inline] #[inline(always)]
pub fn _1(self) -> &'a mut W { pub fn _1(self) -> &'a mut W {
self.variant(BUF7IW::_1) self.variant(BUF7I_A::_1)
} }
#[doc = r" Sets the field bit"] #[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W { pub fn set_bit(self) -> &'a mut W {
self.bit(true) self.bit(true)
} }
#[doc = r" Clears the field bit"] #[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W { pub fn clear_bit(self) -> &'a mut W {
self.bit(false) self.bit(false)
} }
#[doc = r" Writes raw bits to the field"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W { pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true; self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
const OFFSET: u8 = 7;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w self.w
} }
} }
#[doc = r" Proxy"] #[doc = "Reader of field `BUF31TO8I`"]
pub struct _BUF31TO8IW<'a> { pub type BUF31TO8I_R = crate::R<u32, u32>;
#[doc = "Write proxy for field `BUF31TO8I`"]
pub struct BUF31TO8I_W<'a> {
w: &'a mut W, w: &'a mut W,
} }
impl<'a> _BUF31TO8IW<'a> { impl<'a> BUF31TO8I_W<'a> {
#[doc = r" Writes raw bits to the field"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub unsafe fn bits(self, value: u32) -> &'a mut W { pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 16777215; self.w.bits = (self.w.bits & !(0x00ff_ffff << 8)) | (((value as u32) & 0x00ff_ffff) << 8);
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w self.w
} }
} }
impl R { impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Buffer MB0 Interrupt Or Clear FIFO bit"] #[doc = "Bit 0 - Buffer MB0 Interrupt Or Clear FIFO bit"]
#[inline] #[inline(always)]
pub fn buf0i(&self) -> BUF0IR { pub fn buf0i(&self) -> BUF0I_R {
BUF0IR::_from({ BUF0I_R::new((self.bits & 0x01) != 0)
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
} }
#[doc = "Bits 1:4 - Buffer MB i Interrupt Or \"reserved\""] #[doc = "Bits 1:4 - Buffer MB i Interrupt Or \"reserved\""]
#[inline] #[inline(always)]
pub fn buf4to1i(&self) -> BUF4TO1IR { pub fn buf4to1i(&self) -> BUF4TO1I_R {
let bits = { BUF4TO1I_R::new(((self.bits >> 1) & 0x0f) as u8)
const MASK: u8 = 15;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) as u8
};
BUF4TO1IR { bits }
} }
#[doc = "Bit 5 - Buffer MB5 Interrupt Or \"Frames available in Rx FIFO\""] #[doc = "Bit 5 - Buffer MB5 Interrupt Or \"Frames available in Rx FIFO\""]
#[inline] #[inline(always)]
pub fn buf5i(&self) -> BUF5IR { pub fn buf5i(&self) -> BUF5I_R {
BUF5IR::_from({ BUF5I_R::new(((self.bits >> 5) & 0x01) != 0)
const MASK: bool = true;
const OFFSET: u8 = 5;
((self.bits >> OFFSET) & MASK as u32) != 0
})
} }
#[doc = "Bit 6 - Buffer MB6 Interrupt Or \"Rx FIFO Warning\""] #[doc = "Bit 6 - Buffer MB6 Interrupt Or \"Rx FIFO Warning\""]
#[inline] #[inline(always)]
pub fn buf6i(&self) -> BUF6IR { pub fn buf6i(&self) -> BUF6I_R {
BUF6IR::_from({ BUF6I_R::new(((self.bits >> 6) & 0x01) != 0)
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
} }
#[doc = "Bit 7 - Buffer MB7 Interrupt Or \"Rx FIFO Overflow\""] #[doc = "Bit 7 - Buffer MB7 Interrupt Or \"Rx FIFO Overflow\""]
#[inline] #[inline(always)]
pub fn buf7i(&self) -> BUF7IR { pub fn buf7i(&self) -> BUF7I_R {
BUF7IR::_from({ BUF7I_R::new(((self.bits >> 7) & 0x01) != 0)
const MASK: bool = true;
const OFFSET: u8 = 7;
((self.bits >> OFFSET) & MASK as u32) != 0
})
} }
#[doc = "Bits 8:31 - Buffer MBi Interrupt"] #[doc = "Bits 8:31 - Buffer MBi Interrupt"]
#[inline] #[inline(always)]
pub fn buf31to8i(&self) -> BUF31TO8IR { pub fn buf31to8i(&self) -> BUF31TO8I_R {
let bits = { BUF31TO8I_R::new(((self.bits >> 8) & 0x00ff_ffff) as u32)
const MASK: u32 = 16777215;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u32
};
BUF31TO8IR { bits }
} }
} }
impl W { impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Buffer MB0 Interrupt Or Clear FIFO bit"] #[doc = "Bit 0 - Buffer MB0 Interrupt Or Clear FIFO bit"]
#[inline] #[inline(always)]
pub fn buf0i(&mut self) -> _BUF0IW { pub fn buf0i(&mut self) -> BUF0I_W {
_BUF0IW { w: self } BUF0I_W { w: self }
} }
#[doc = "Bits 1:4 - Buffer MB i Interrupt Or \"reserved\""] #[doc = "Bits 1:4 - Buffer MB i Interrupt Or \"reserved\""]
#[inline] #[inline(always)]
pub fn buf4to1i(&mut self) -> _BUF4TO1IW { pub fn buf4to1i(&mut self) -> BUF4TO1I_W {
_BUF4TO1IW { w: self } BUF4TO1I_W { w: self }
} }
#[doc = "Bit 5 - Buffer MB5 Interrupt Or \"Frames available in Rx FIFO\""] #[doc = "Bit 5 - Buffer MB5 Interrupt Or \"Frames available in Rx FIFO\""]
#[inline] #[inline(always)]
pub fn buf5i(&mut self) -> _BUF5IW { pub fn buf5i(&mut self) -> BUF5I_W {
_BUF5IW { w: self } BUF5I_W { w: self }
} }
#[doc = "Bit 6 - Buffer MB6 Interrupt Or \"Rx FIFO Warning\""] #[doc = "Bit 6 - Buffer MB6 Interrupt Or \"Rx FIFO Warning\""]
#[inline] #[inline(always)]
pub fn buf6i(&mut self) -> _BUF6IW { pub fn buf6i(&mut self) -> BUF6I_W {
_BUF6IW { w: self } BUF6I_W { w: self }
} }
#[doc = "Bit 7 - Buffer MB7 Interrupt Or \"Rx FIFO Overflow\""] #[doc = "Bit 7 - Buffer MB7 Interrupt Or \"Rx FIFO Overflow\""]
#[inline] #[inline(always)]
pub fn buf7i(&mut self) -> _BUF7IW { pub fn buf7i(&mut self) -> BUF7I_W {
_BUF7IW { w: self } BUF7I_W { w: self }
} }
#[doc = "Bits 8:31 - Buffer MBi Interrupt"] #[doc = "Bits 8:31 - Buffer MBi Interrupt"]
#[inline] #[inline(always)]
pub fn buf31to8i(&mut self) -> _BUF31TO8IW { pub fn buf31to8i(&mut self) -> BUF31TO8I_W {
_BUF31TO8IW { w: self } BUF31TO8I_W { w: self }
} }
} }

143
src/can0/imask1.rs
View File

@ -1,103 +1,40 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register IMASK1"]
pub struct R { pub type R = crate::R<u32, super::IMASK1>;
bits: u32, #[doc = "Writer for register IMASK1"]
} pub type W = crate::W<u32, super::IMASK1>;
#[doc = r" Value to write to the register"] #[doc = "Register IMASK1 `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::IMASK1 {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::IMASK1 { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `BUF31TO0M`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type BUF31TO0M_R = crate::R<u32, u32>;
{ #[doc = "Write proxy for field `BUF31TO0M`"]
let bits = self.register.get(); pub struct BUF31TO0M_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> BUF31TO0M_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u32) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0xffff_ffff) | ((value as u32) & 0xffff_ffff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] impl R {
#[inline] #[doc = "Bits 0:31 - Buffer MB i Mask"]
pub fn write<F>(&self, f: F) #[inline(always)]
where pub fn buf31to0m(&self) -> BUF31TO0M_R {
F: FnOnce(&mut W) -> &mut W, BUF31TO0M_R::new((self.bits & 0xffff_ffff) as u32)
{ }
let mut w = W::reset_value(); }
f(&mut w); impl W {
self.register.set(w.bits); #[doc = "Bits 0:31 - Buffer MB i Mask"]
} #[inline(always)]
#[doc = r" Writes the reset value to the register"] pub fn buf31to0m(&mut self) -> BUF31TO0M_W {
#[inline] BUF31TO0M_W { w: self }
pub fn reset(&self) { }
self.write(|w| w) }
}
}
#[doc = r" Value of the field"]
pub struct BUF31TO0MR {
bits: u32,
}
impl BUF31TO0MR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _BUF31TO0MW<'a> {
w: &'a mut W,
}
impl<'a> _BUF31TO0MW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
const MASK: u32 = 4294967295;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - Buffer MB i Mask"]
#[inline]
pub fn buf31to0m(&self) -> BUF31TO0MR {
let bits = {
const MASK: u32 = 4294967295;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
BUF31TO0MR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:31 - Buffer MB i Mask"]
#[inline]
pub fn buf31to0m(&mut self) -> _BUF31TO0MW {
_BUF31TO0MW { w: self }
}
}

3407
src/can0/mcr.rs
View File

File diff suppressed because it is too large Load Diff

338
src/can0/pl1_hi.rs
View File

@ -1,226 +1,112 @@
#[doc = r" Value read from the register"] #[doc = "Reader of register PL1_HI"]
pub struct R { pub type R = crate::R<u32, super::PL1_HI>;
bits: u32, #[doc = "Writer for register PL1_HI"]
} pub type W = crate::W<u32, super::PL1_HI>;
#[doc = r" Value to write to the register"] #[doc = "Register PL1_HI `reset()`'s with value 0"]
pub struct W { impl crate::ResetValue for super::PL1_HI {
bits: u32, type Type = u32;
} #[inline(always)]
impl super::PL1_HI { fn reset_value() -> Self::Type {
#[doc = r" Modifies the contents of the register"] 0
#[inline] }
pub fn modify<F>(&self, f: F) }
where #[doc = "Reader of field `Data_byte_7`"]
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, pub type DATA_BYTE_7_R = crate::R<u8, u8>;
{ #[doc = "Write proxy for field `Data_byte_7`"]
let bits = self.register.get(); pub struct DATA_BYTE_7_W<'a> {
let r = R { bits: bits }; w: &'a mut W,
let mut w = W { bits: bits }; }
f(&r, &mut w); impl<'a> DATA_BYTE_7_W<'a> {
self.register.set(w.bits); #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
#[doc = r" Reads the contents of the register"] pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[inline] self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
pub fn read(&self) -> R { self.w
R { bits: self.register.get() } }
} }
#[doc = r" Writes to the register"] #[doc = "Reader of field `Data_byte_6`"]
#[inline] pub type DATA_BYTE_6_R = crate::R<u8, u8>;
pub fn write<F>(&self, f: F) #[doc = "Write proxy for field `Data_byte_6`"]
where pub struct DATA_BYTE_6_W<'a> {
F: FnOnce(&mut W) -> &mut W, w: &'a mut W,
{ }
let mut w = W::reset_value(); impl<'a> DATA_BYTE_6_W<'a> {
f(&mut w); #[doc = r"Writes raw bits to the field"]
self.register.set(w.bits); #[inline(always)]
} pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[doc = r" Writes the reset value to the register"] self.w.bits = (self.w.bits & !(0xff << 8)) | (((value as u32) & 0xff) << 8);
#[inline] self.w
pub fn reset(&self) { }
self.write(|w| w) }
} #[doc = "Reader of field `Data_byte_5`"]
} pub type DATA_BYTE_5_R = crate::R<u8, u8>;
#[doc = r" Value of the field"] #[doc = "Write proxy for field `Data_byte_5`"]
pub struct DATA_BYTE_7R { pub struct DATA_BYTE_5_W<'a> {
bits: u8, w: &'a mut W,
} }
impl DATA_BYTE_7R { impl<'a> DATA_BYTE_5_W<'a> {
#[doc = r" Value of the field as raw bits"] #[doc = r"Writes raw bits to the field"]
#[inline] #[inline(always)]
pub fn bits(&self) -> u8 { pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.bits self.w.bits = (self.w.bits & !(0xff << 16)) | (((value as u32) & 0xff) << 16);
} self.w
} }
#[doc = r" Value of the field"] }
pub struct DATA_BYTE_6R { #[doc = "Reader of field `Data_byte_4`"]
bits: u8, pub type DATA_BYTE_4_R = crate::R<u8, u8>;
} #[doc = "Write proxy for field `Data_byte_4`"]
impl DATA_BYTE_6R { pub struct DATA_BYTE_4_W<'a> {
#[doc = r" Value of the field as raw bits"] w: &'a mut W,
#[inline] }
pub fn bits(&self) -> u8 { impl<'a> DATA_BYTE_4_W<'a> {
self.bits #[doc = r"Writes raw bits to the field"]
} #[inline(always)]
} pub unsafe fn bits(self, value: u8) -> &'a mut W {
#[doc = r" Value of the field"] self.w.bits = (self.w.bits & !(0xff << 24)) | (((value as u32) & 0xff) << 24);
pub struct DATA_BYTE_5R { self.w
bits: u8, }
} }
impl DATA_BYTE_5R { impl R {
#[doc = r" Value of the field as raw bits"] #[doc = "Bits 0:7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7."]
#[inline] #[inline(always)]
pub fn bits(&self) -> u8 { pub fn data_byte_7(&self) -> DATA_BYTE_7_R {
self.bits DATA_BYTE_7_R::new((self.bits & 0xff) as u8)
} }
} #[doc = "Bits 8:15 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6."]
#[doc = r" Value of the field"] #[inline(always)]
pub struct DATA_BYTE_4R { pub fn data_byte_6(&self) -> DATA_BYTE_6_R {
bits: u8, DATA_BYTE_6_R::new(((self.bits >> 8) & 0xff) as u8)
} }
impl DATA_BYTE_4R { #[doc = "Bits 16:23 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5."]
#[doc = r" Value of the field as raw bits"] #[inline(always)]
#[inline] pub fn data_byte_5(&self) -> DATA_BYTE_5_R {
pub fn bits(&self) -> u8 { DATA_BYTE_5_R::new(((self.bits >> 16) & 0xff) as u8)
self.bits }
} #[doc = "Bits 24:31 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4."]
} #[inline(always)]
#[doc = r" Proxy"] pub fn data_byte_4(&self) -> DATA_BYTE_4_R {
pub struct _DATA_BYTE_7W<'a> { DATA_BYTE_4_R::new(((self.bits >> 24) & 0xff) as u8)
w: &'a mut W, }
} }
impl<'a> _DATA_BYTE_7W<'a> { impl W {
#[doc = r" Writes raw bits to the field"] #[doc = "Bits 0:7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7."]
#[inline] #[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W { pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W {
const MASK: u8 = 255; DATA_BYTE_7_W { w: self }
const OFFSET: u8 = 0; }
self.w.bits &= !((MASK as u32) << OFFSET); #[doc = "Bits 8:15 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6."]
self.w.bits |= ((value & MASK) as u32) << OFFSET; #[inline(always)]
self.w pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W {
} DATA_BYTE_6_W { w: self }
} }
#[doc = r" Proxy"] #[doc = "Bits 16:23 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5."]
pub struct _DATA_BYTE_6W<'a> { #[inline(always)]
w: &'a mut W, pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W {
} DATA_BYTE_5_W { w: self }
impl<'a> _DATA_BYTE_6W<'a> { }
#[doc = r" Writes raw bits to the field"] #[doc = "Bits 24:31 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4."]
#[inline] #[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W { pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W {
const MASK: u8 = 255; DATA_BYTE_4_W { w: self }
const OFFSET: u8 = 8; }
self.w.bits &= !((MASK as u32) << OFFSET); }
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_5W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_5W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _DATA_BYTE_4W<'a> {
w: &'a mut W,
}
impl<'a> _DATA_BYTE_4W<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7."]
#[inline]
pub fn data_byte_7(&self) -> DATA_BYTE_7R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_7R { bits }
}
#[doc = "Bits 8:15 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6."]
#[inline]
pub fn data_byte_6(&self) -> DATA_BYTE_6R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_6R { bits }
}
#[doc = "Bits 16:23 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5."]
#[inline]
pub fn data_byte_5(&self) -> DATA_BYTE_5R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_5R { bits }
}
#[doc = "Bits 24:31 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4."]
#[inline]
pub fn data_byte_4(&self) -> DATA_BYTE_4R {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DATA_BYTE_4R { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7."]
#[inline]
pub fn data_byte_7(&mut self) -> _DATA_BYTE_7W {
_DATA_BYTE_7W { w: self }
}
#[doc = "Bits 8:15 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6."]
#[inline]
pub fn data_byte_6(&mut self) -> _DATA_BYTE_6W {
_DATA_BYTE_6W { w: self }
}
#[doc = "Bits 16:23 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5."]
#[inline]
pub fn data_byte_5(&mut self) -> _DATA_BYTE_5W {
_DATA_BYTE_5W { w: self }
}
#[doc = "Bits 24:31 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4."]
#[inline]
pub fn data_byte_4(&mut self) -> _DATA_BYTE_4W {
_DATA_BYTE_4W { w: self }
}
}

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