s32k118: rewrite everything for s32k118
Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
parent
444b0e87d1
commit
96cd7368a2
@ -1,12 +1,12 @@
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[package]
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authors = ["Kjetil Kjeka <kjetilkjeka@gmail.com>"]
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name = "s32k144"
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name = "s32k118"
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version = "0.10.0"
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description = "Peripheral access API for NXP S32K144 microcontrollers (generated using svd2rust)"
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description = "Peripheral access API for NXP S32K118 microcontrollers (generated using svd2rust)"
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repository = "https://github.com/kjetilkjeka/s32k144.rs"
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keywords = ["arm", "embedded", "svd2rust", "cortex-m4", "NXP"]
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keywords = ["arm", "embedded", "svd2rust", "cortex-m0", "NXP"]
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categories = ["embedded", "hardware-support", "no-std"]
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license = "Apache-2.0/MIT"
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File diff suppressed because it is too large
Load Diff
96
device.x
96
device.x
@ -2,88 +2,32 @@ PROVIDE(DMA0 = DefaultHandler);
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PROVIDE(DMA1 = DefaultHandler);
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PROVIDE(DMA2 = DefaultHandler);
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PROVIDE(DMA3 = DefaultHandler);
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PROVIDE(DMA4 = DefaultHandler);
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PROVIDE(DMA5 = DefaultHandler);
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PROVIDE(DMA6 = DefaultHandler);
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PROVIDE(DMA7 = DefaultHandler);
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PROVIDE(DMA8 = DefaultHandler);
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PROVIDE(DMA9 = DefaultHandler);
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PROVIDE(DMA10 = DefaultHandler);
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PROVIDE(DMA11 = DefaultHandler);
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PROVIDE(DMA12 = DefaultHandler);
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PROVIDE(DMA13 = DefaultHandler);
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PROVIDE(DMA14 = DefaultHandler);
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PROVIDE(DMA15 = DefaultHandler);
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PROVIDE(DMA_ERROR = DefaultHandler);
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PROVIDE(MCM = DefaultHandler);
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PROVIDE(FTFC = DefaultHandler);
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PROVIDE(READ_COLLISION = DefaultHandler);
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PROVIDE(LVD_LVW = DefaultHandler);
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PROVIDE(FTFC_FAULT = DefaultHandler);
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PROVIDE(WDOG_EWM = DefaultHandler);
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PROVIDE(RCM = DefaultHandler);
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PROVIDE(LPI2C0_MASTER = DefaultHandler);
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PROVIDE(LPI2C0_SLAVE = DefaultHandler);
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PROVIDE(LPSPI0 = DefaultHandler);
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PROVIDE(LPSPI1 = DefaultHandler);
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PROVIDE(LPSPI2 = DefaultHandler);
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PROVIDE(LPUART0_RXTX = DefaultHandler);
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PROVIDE(LPUART1_RXTX = DefaultHandler);
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PROVIDE(LPUART2_RXTX = DefaultHandler);
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PROVIDE(ADC0 = DefaultHandler);
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PROVIDE(ADC1 = DefaultHandler);
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PROVIDE(CMP0 = DefaultHandler);
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PROVIDE(ERM_SINGLE_FAULT = DefaultHandler);
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PROVIDE(ERM_DOUBLE_FAULT = DefaultHandler);
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PROVIDE(ERM_FAULT = DefaultHandler);
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PROVIDE(RTC = DefaultHandler);
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PROVIDE(RTC_SECONDS = DefaultHandler);
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PROVIDE(LPIT0_CH0 = DefaultHandler);
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PROVIDE(LPIT0_CH1 = DefaultHandler);
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PROVIDE(LPIT0_CH2 = DefaultHandler);
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PROVIDE(LPIT0_CH3 = DefaultHandler);
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PROVIDE(PDB0 = DefaultHandler);
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PROVIDE(SCG = DefaultHandler);
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PROVIDE(LPTMR0 = DefaultHandler);
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PROVIDE(PORTA = DefaultHandler);
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PROVIDE(PORTB = DefaultHandler);
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PROVIDE(PORTC = DefaultHandler);
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PROVIDE(PORTD = DefaultHandler);
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PROVIDE(PORTE = DefaultHandler);
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PROVIDE(PDB1 = DefaultHandler);
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PROVIDE(FLEXIO = DefaultHandler);
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PROVIDE(CAN0_ORED = DefaultHandler);
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PROVIDE(CAN0_ERROR = DefaultHandler);
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PROVIDE(CAN0_WAKE_UP = DefaultHandler);
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PROVIDE(CAN0_ORED_0_15_MB = DefaultHandler);
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PROVIDE(CAN0_ORED_16_31_MB = DefaultHandler);
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PROVIDE(CAN1_ORED = DefaultHandler);
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PROVIDE(CAN1_ERROR = DefaultHandler);
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PROVIDE(CAN1_ORED_0_15_MB = DefaultHandler);
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PROVIDE(CAN2_ORED = DefaultHandler);
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PROVIDE(CAN2_ERROR = DefaultHandler);
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PROVIDE(CAN2_ORED_0_15_MB = DefaultHandler);
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PROVIDE(FTM0_CH0_CH1 = DefaultHandler);
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PROVIDE(FTM0_CH2_CH3 = DefaultHandler);
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PROVIDE(FTM0_CH4_CH5 = DefaultHandler);
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PROVIDE(FTM0_CH6_CH7 = DefaultHandler);
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PROVIDE(PORT = DefaultHandler);
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PROVIDE(CAN0_ORED_ERR_WAKEUP = DefaultHandler);
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PROVIDE(CAN0_ORED_0_31_MB = DefaultHandler);
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PROVIDE(FTM0_CH0_7 = DefaultHandler);
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PROVIDE(FTM0_FAULT = DefaultHandler);
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PROVIDE(FTM0_OVF_RELOAD = DefaultHandler);
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PROVIDE(FTM1_CH0_CH1 = DefaultHandler);
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PROVIDE(FTM1_CH2_CH3 = DefaultHandler);
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PROVIDE(FTM1_CH4_CH5 = DefaultHandler);
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PROVIDE(FTM1_CH6_CH7 = DefaultHandler);
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PROVIDE(FTM1_CH0_7 = DefaultHandler);
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PROVIDE(FTM1_FAULT = DefaultHandler);
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PROVIDE(FTM1_OVF_RELOAD = DefaultHandler);
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PROVIDE(FTM2_CH0_CH1 = DefaultHandler);
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PROVIDE(FTM2_CH2_CH3 = DefaultHandler);
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PROVIDE(FTM2_CH4_CH5 = DefaultHandler);
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PROVIDE(FTM2_CH6_CH7 = DefaultHandler);
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PROVIDE(FTM2_FAULT = DefaultHandler);
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PROVIDE(FTM2_OVF_RELOAD = DefaultHandler);
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PROVIDE(FTM3_CH0_CH1 = DefaultHandler);
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PROVIDE(FTM3_CH2_CH3 = DefaultHandler);
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PROVIDE(FTM3_CH4_CH5 = DefaultHandler);
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PROVIDE(FTM3_CH6_CH7 = DefaultHandler);
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PROVIDE(FTM3_FAULT = DefaultHandler);
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PROVIDE(FTM3_OVF_RELOAD = DefaultHandler);
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PROVIDE(FTFC = DefaultHandler);
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PROVIDE(PDB0 = DefaultHandler);
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PROVIDE(LPIT0 = DefaultHandler);
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PROVIDE(SCG_CMU_LVD_LVWSCG = DefaultHandler);
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PROVIDE(WDOG = DefaultHandler);
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PROVIDE(RCM = DefaultHandler);
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PROVIDE(LPI2C0_MASTER_SLAVE = DefaultHandler);
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PROVIDE(FLEXIO = DefaultHandler);
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PROVIDE(LPSPI0 = DefaultHandler);
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PROVIDE(LPSPI1 = DefaultHandler);
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PROVIDE(ADC0 = DefaultHandler);
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PROVIDE(CMP0 = DefaultHandler);
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PROVIDE(LPUART1_RXTX = DefaultHandler);
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PROVIDE(LPUART0_RXTX = DefaultHandler);
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718
src/adc0.rs
718
src/adc0.rs
@ -1,290 +1,428 @@
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#[doc = r" Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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#[doc = "0x00 - ADC Status and Control Register 1"]
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pub sc1a: SC1,
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#[doc = "0x04 - ADC Status and Control Register 1"]
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pub sc1b: SC1,
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#[doc = "0x08 - ADC Status and Control Register 1"]
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pub sc1c: SC1,
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#[doc = "0x0c - ADC Status and Control Register 1"]
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pub sc1d: SC1,
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#[doc = "0x10 - ADC Status and Control Register 1"]
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pub sc1e: SC1,
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#[doc = "0x14 - ADC Status and Control Register 1"]
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pub sc1f: SC1,
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#[doc = "0x18 - ADC Status and Control Register 1"]
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pub sc1g: SC1,
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#[doc = "0x1c - ADC Status and Control Register 1"]
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pub sc1h: SC1,
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#[doc = "0x20 - ADC Status and Control Register 1"]
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pub sc1i: SC1,
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#[doc = "0x24 - ADC Status and Control Register 1"]
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pub sc1j: SC1,
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#[doc = "0x28 - ADC Status and Control Register 1"]
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pub sc1k: SC1,
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#[doc = "0x2c - ADC Status and Control Register 1"]
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pub sc1l: SC1,
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#[doc = "0x30 - ADC Status and Control Register 1"]
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pub sc1m: SC1,
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#[doc = "0x34 - ADC Status and Control Register 1"]
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pub sc1n: SC1,
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#[doc = "0x38 - ADC Status and Control Register 1"]
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pub sc1o: SC1,
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#[doc = "0x3c - ADC Status and Control Register 1"]
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pub sc1p: SC1,
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#[doc = "0x40 - ADC Configuration Register 1"]
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pub cfg1: CFG1,
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#[doc = "0x44 - ADC Configuration Register 2"]
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pub cfg2: CFG2,
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#[doc = "0x48 - ADC Data Result Registers"]
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pub ra: R,
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#[doc = "0x4c - ADC Data Result Registers"]
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pub rb: R,
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#[doc = "0x50 - ADC Data Result Registers"]
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pub rc: R,
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#[doc = "0x54 - ADC Data Result Registers"]
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pub rd: R,
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#[doc = "0x58 - ADC Data Result Registers"]
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pub re: R,
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#[doc = "0x5c - ADC Data Result Registers"]
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pub rf: R,
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#[doc = "0x60 - ADC Data Result Registers"]
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pub rg: R,
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#[doc = "0x64 - ADC Data Result Registers"]
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pub rh: R,
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#[doc = "0x68 - ADC Data Result Registers"]
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pub ri: R,
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#[doc = "0x6c - ADC Data Result Registers"]
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pub rj: R,
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#[doc = "0x70 - ADC Data Result Registers"]
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pub rk: R,
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#[doc = "0x74 - ADC Data Result Registers"]
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pub rl: R,
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#[doc = "0x78 - ADC Data Result Registers"]
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pub rm: R,
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#[doc = "0x7c - ADC Data Result Registers"]
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pub rn: R,
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#[doc = "0x80 - ADC Data Result Registers"]
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pub ro: R,
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#[doc = "0x84 - ADC Data Result Registers"]
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pub rp: R,
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#[doc = "0x88 - Compare Value Registers"]
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pub cv1: CV,
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#[doc = "0x8c - Compare Value Registers"]
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pub cv2: CV,
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#[doc = "0x90 - Status and Control Register 2"]
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pub sc2: SC2,
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#[doc = "0x94 - Status and Control Register 3"]
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pub sc3: SC3,
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#[doc = "0x98 - BASE Offset Register"]
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pub base_ofs: BASE_OFS,
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#[doc = "0x9c - ADC Offset Correction Register"]
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pub ofs: OFS,
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#[doc = "0xa0 - USER Offset Correction Register"]
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pub usr_ofs: USR_OFS,
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#[doc = "0xa4 - ADC X Offset Correction Register"]
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pub xofs: XOFS,
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#[doc = "0xa8 - ADC Y Offset Correction Register"]
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pub yofs: YOFS,
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#[doc = "0xac - ADC Gain Register"]
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pub g: G,
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#[doc = "0xb0 - ADC User Gain Register"]
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pub ug: UG,
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#[doc = "0xb4 - ADC General Calibration Value Register S"]
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pub clps: CLPS,
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#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
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pub clp3: CLP3,
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#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
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pub clp2: CLP2,
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#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
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pub clp1: CLP1,
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#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
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pub clp0: CLP0,
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#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
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pub clpx: CLPX,
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#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
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pub clp9: CLP9,
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#[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
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pub clps_ofs: CLPS_OFS,
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#[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
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pub clp3_ofs: CLP3_OFS,
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#[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
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pub clp2_ofs: CLP2_OFS,
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#[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
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pub clp1_ofs: CLP1_OFS,
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#[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
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pub clp0_ofs: CLP0_OFS,
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#[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
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pub clpx_ofs: CLPX_OFS,
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#[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
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pub clp9_ofs: CLP9_OFS,
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}
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#[doc = "ADC Status and Control Register 1"]
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pub struct SC1 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Status and Control Register 1"]
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pub mod sc1;
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#[doc = "ADC Configuration Register 1"]
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pub struct CFG1 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Configuration Register 1"]
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pub mod cfg1;
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#[doc = "ADC Configuration Register 2"]
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pub struct CFG2 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Configuration Register 2"]
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pub mod cfg2;
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#[doc = "ADC Data Result Registers"]
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pub struct R {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Data Result Registers"]
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pub mod r;
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#[doc = "Compare Value Registers"]
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pub struct CV {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Compare Value Registers"]
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pub mod cv;
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#[doc = "Status and Control Register 2"]
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pub struct SC2 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Status and Control Register 2"]
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pub mod sc2;
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#[doc = "Status and Control Register 3"]
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pub struct SC3 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Status and Control Register 3"]
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pub mod sc3;
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#[doc = "BASE Offset Register"]
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pub struct BASE_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "BASE Offset Register"]
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pub mod base_ofs;
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#[doc = "ADC Offset Correction Register"]
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pub struct OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Offset Correction Register"]
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pub mod ofs;
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#[doc = "USER Offset Correction Register"]
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pub struct USR_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "USER Offset Correction Register"]
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pub mod usr_ofs;
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#[doc = "ADC X Offset Correction Register"]
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pub struct XOFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC X Offset Correction Register"]
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pub mod xofs;
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#[doc = "ADC Y Offset Correction Register"]
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pub struct YOFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Y Offset Correction Register"]
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pub mod yofs;
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#[doc = "ADC Gain Register"]
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pub struct G {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Gain Register"]
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pub mod g;
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#[doc = "ADC User Gain Register"]
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pub struct UG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC User Gain Register"]
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pub mod ug;
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#[doc = "ADC General Calibration Value Register S"]
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pub struct CLPS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC General Calibration Value Register S"]
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pub mod clps;
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#[doc = "ADC Plus-Side General Calibration Value Register 3"]
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pub struct CLP3 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 3"]
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pub mod clp3;
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#[doc = "ADC Plus-Side General Calibration Value Register 2"]
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pub struct CLP2 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 2"]
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pub mod clp2;
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#[doc = "ADC Plus-Side General Calibration Value Register 1"]
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pub struct CLP1 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 1"]
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pub mod clp1;
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#[doc = "ADC Plus-Side General Calibration Value Register 0"]
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pub struct CLP0 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 0"]
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pub mod clp0;
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#[doc = "ADC Plus-Side General Calibration Value Register X"]
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pub struct CLPX {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register X"]
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pub mod clpx;
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#[doc = "ADC Plus-Side General Calibration Value Register 9"]
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pub struct CLP9 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 9"]
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pub mod clp9;
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#[doc = "ADC General Calibration Offset Value Register S"]
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pub struct CLPS_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC General Calibration Offset Value Register S"]
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pub mod clps_ofs;
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
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pub struct CLP3_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
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pub mod clp3_ofs;
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
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pub struct CLP2_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
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pub mod clp2_ofs;
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
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pub struct CLP1_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
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pub mod clp1_ofs;
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
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pub struct CLP0_OFS {
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register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub mod clp0_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub struct CLPX_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub mod clpx_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub struct CLP9_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub mod clp9_ofs;
|
||||
#[doc = r"Register block"]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
#[doc = "0x00 - ADC Status and Control Register 1"]
|
||||
pub sc1a: SC1,
|
||||
#[doc = "0x04 - ADC Status and Control Register 1"]
|
||||
pub sc1b: SC1,
|
||||
#[doc = "0x08 - ADC Status and Control Register 1"]
|
||||
pub sc1c: SC1,
|
||||
#[doc = "0x0c - ADC Status and Control Register 1"]
|
||||
pub sc1d: SC1,
|
||||
#[doc = "0x10 - ADC Status and Control Register 1"]
|
||||
pub sc1e: SC1,
|
||||
#[doc = "0x14 - ADC Status and Control Register 1"]
|
||||
pub sc1f: SC1,
|
||||
#[doc = "0x18 - ADC Status and Control Register 1"]
|
||||
pub sc1g: SC1,
|
||||
#[doc = "0x1c - ADC Status and Control Register 1"]
|
||||
pub sc1h: SC1,
|
||||
#[doc = "0x20 - ADC Status and Control Register 1"]
|
||||
pub sc1i: SC1,
|
||||
#[doc = "0x24 - ADC Status and Control Register 1"]
|
||||
pub sc1j: SC1,
|
||||
#[doc = "0x28 - ADC Status and Control Register 1"]
|
||||
pub sc1k: SC1,
|
||||
#[doc = "0x2c - ADC Status and Control Register 1"]
|
||||
pub sc1l: SC1,
|
||||
#[doc = "0x30 - ADC Status and Control Register 1"]
|
||||
pub sc1m: SC1,
|
||||
#[doc = "0x34 - ADC Status and Control Register 1"]
|
||||
pub sc1n: SC1,
|
||||
#[doc = "0x38 - ADC Status and Control Register 1"]
|
||||
pub sc1o: SC1,
|
||||
#[doc = "0x3c - ADC Status and Control Register 1"]
|
||||
pub sc1p: SC1,
|
||||
#[doc = "0x40 - ADC Configuration Register 1"]
|
||||
pub cfg1: CFG1,
|
||||
#[doc = "0x44 - ADC Configuration Register 2"]
|
||||
pub cfg2: CFG2,
|
||||
#[doc = "0x48 - ADC Data Result Registers"]
|
||||
pub ra: R,
|
||||
#[doc = "0x4c - ADC Data Result Registers"]
|
||||
pub rb: R,
|
||||
#[doc = "0x50 - ADC Data Result Registers"]
|
||||
pub rc: R,
|
||||
#[doc = "0x54 - ADC Data Result Registers"]
|
||||
pub rd: R,
|
||||
#[doc = "0x58 - ADC Data Result Registers"]
|
||||
pub re: R,
|
||||
#[doc = "0x5c - ADC Data Result Registers"]
|
||||
pub rf: R,
|
||||
#[doc = "0x60 - ADC Data Result Registers"]
|
||||
pub rg: R,
|
||||
#[doc = "0x64 - ADC Data Result Registers"]
|
||||
pub rh: R,
|
||||
#[doc = "0x68 - ADC Data Result Registers"]
|
||||
pub ri: R,
|
||||
#[doc = "0x6c - ADC Data Result Registers"]
|
||||
pub rj: R,
|
||||
#[doc = "0x70 - ADC Data Result Registers"]
|
||||
pub rk: R,
|
||||
#[doc = "0x74 - ADC Data Result Registers"]
|
||||
pub rl: R,
|
||||
#[doc = "0x78 - ADC Data Result Registers"]
|
||||
pub rm: R,
|
||||
#[doc = "0x7c - ADC Data Result Registers"]
|
||||
pub rn: R,
|
||||
#[doc = "0x80 - ADC Data Result Registers"]
|
||||
pub ro: R,
|
||||
#[doc = "0x84 - ADC Data Result Registers"]
|
||||
pub rp: R,
|
||||
#[doc = "0x88 - Compare Value Registers"]
|
||||
pub cv1: CV,
|
||||
#[doc = "0x8c - Compare Value Registers"]
|
||||
pub cv2: CV,
|
||||
#[doc = "0x90 - Status and Control Register 2"]
|
||||
pub sc2: SC2,
|
||||
#[doc = "0x94 - Status and Control Register 3"]
|
||||
pub sc3: SC3,
|
||||
#[doc = "0x98 - BASE Offset Register"]
|
||||
pub base_ofs: BASE_OFS,
|
||||
#[doc = "0x9c - ADC Offset Correction Register"]
|
||||
pub ofs: OFS,
|
||||
#[doc = "0xa0 - USER Offset Correction Register"]
|
||||
pub usr_ofs: USR_OFS,
|
||||
#[doc = "0xa4 - ADC X Offset Correction Register"]
|
||||
pub xofs: XOFS,
|
||||
#[doc = "0xa8 - ADC Y Offset Correction Register"]
|
||||
pub yofs: YOFS,
|
||||
#[doc = "0xac - ADC Gain Register"]
|
||||
pub g: G,
|
||||
#[doc = "0xb0 - ADC User Gain Register"]
|
||||
pub ug: UG,
|
||||
#[doc = "0xb4 - ADC General Calibration Value Register S"]
|
||||
pub clps: CLPS,
|
||||
#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
|
||||
pub clp3: CLP3,
|
||||
#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
|
||||
pub clp2: CLP2,
|
||||
#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
|
||||
pub clp1: CLP1,
|
||||
#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
|
||||
pub clp0: CLP0,
|
||||
#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
|
||||
pub clpx: CLPX,
|
||||
#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
|
||||
pub clp9: CLP9,
|
||||
#[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
|
||||
pub clps_ofs: CLPS_OFS,
|
||||
#[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub clp3_ofs: CLP3_OFS,
|
||||
#[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub clp2_ofs: CLP2_OFS,
|
||||
#[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub clp1_ofs: CLP1_OFS,
|
||||
#[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub clp0_ofs: CLP0_OFS,
|
||||
#[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub clpx_ofs: CLPX_OFS,
|
||||
#[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub clp9_ofs: CLP9_OFS,
|
||||
}
|
||||
#[doc = "ADC Status and Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sc1](sc1) module"]
|
||||
pub type SC1 = crate::Reg<u32, _SC1>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _SC1;
|
||||
#[doc = "`read()` method returns [sc1::R](sc1::R) reader structure"]
|
||||
impl crate::Readable for SC1 {}
|
||||
#[doc = "`write(|w| ..)` method takes [sc1::W](sc1::W) writer structure"]
|
||||
impl crate::Writable for SC1 {}
|
||||
#[doc = "ADC Status and Control Register 1"]
|
||||
pub mod sc1;
|
||||
#[doc = "ADC Configuration Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg1](cfg1) module"]
|
||||
pub type CFG1 = crate::Reg<u32, _CFG1>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CFG1;
|
||||
#[doc = "`read()` method returns [cfg1::R](cfg1::R) reader structure"]
|
||||
impl crate::Readable for CFG1 {}
|
||||
#[doc = "`write(|w| ..)` method takes [cfg1::W](cfg1::W) writer structure"]
|
||||
impl crate::Writable for CFG1 {}
|
||||
#[doc = "ADC Configuration Register 1"]
|
||||
pub mod cfg1;
|
||||
#[doc = "ADC Configuration Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg2](cfg2) module"]
|
||||
pub type CFG2 = crate::Reg<u32, _CFG2>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CFG2;
|
||||
#[doc = "`read()` method returns [cfg2::R](cfg2::R) reader structure"]
|
||||
impl crate::Readable for CFG2 {}
|
||||
#[doc = "`write(|w| ..)` method takes [cfg2::W](cfg2::W) writer structure"]
|
||||
impl crate::Writable for CFG2 {}
|
||||
#[doc = "ADC Configuration Register 2"]
|
||||
pub mod cfg2;
|
||||
#[doc = "ADC Data Result Registers\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r](r) module"]
|
||||
pub type R = crate::Reg<u32, _R>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _R;
|
||||
#[doc = "`read()` method returns [r::R](r::R) reader structure"]
|
||||
impl crate::Readable for R {}
|
||||
#[doc = "ADC Data Result Registers"]
|
||||
pub mod r;
|
||||
#[doc = "Compare Value Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cv](cv) module"]
|
||||
pub type CV = crate::Reg<u32, _CV>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CV;
|
||||
#[doc = "`read()` method returns [cv::R](cv::R) reader structure"]
|
||||
impl crate::Readable for CV {}
|
||||
#[doc = "`write(|w| ..)` method takes [cv::W](cv::W) writer structure"]
|
||||
impl crate::Writable for CV {}
|
||||
#[doc = "Compare Value Registers"]
|
||||
pub mod cv;
|
||||
#[doc = "Status and Control Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sc2](sc2) module"]
|
||||
pub type SC2 = crate::Reg<u32, _SC2>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _SC2;
|
||||
#[doc = "`read()` method returns [sc2::R](sc2::R) reader structure"]
|
||||
impl crate::Readable for SC2 {}
|
||||
#[doc = "`write(|w| ..)` method takes [sc2::W](sc2::W) writer structure"]
|
||||
impl crate::Writable for SC2 {}
|
||||
#[doc = "Status and Control Register 2"]
|
||||
pub mod sc2;
|
||||
#[doc = "Status and Control Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sc3](sc3) module"]
|
||||
pub type SC3 = crate::Reg<u32, _SC3>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _SC3;
|
||||
#[doc = "`read()` method returns [sc3::R](sc3::R) reader structure"]
|
||||
impl crate::Readable for SC3 {}
|
||||
#[doc = "`write(|w| ..)` method takes [sc3::W](sc3::W) writer structure"]
|
||||
impl crate::Writable for SC3 {}
|
||||
#[doc = "Status and Control Register 3"]
|
||||
pub mod sc3;
|
||||
#[doc = "BASE Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base_ofs](base_ofs) module"]
|
||||
pub type BASE_OFS = crate::Reg<u32, _BASE_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _BASE_OFS;
|
||||
#[doc = "`read()` method returns [base_ofs::R](base_ofs::R) reader structure"]
|
||||
impl crate::Readable for BASE_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [base_ofs::W](base_ofs::W) writer structure"]
|
||||
impl crate::Writable for BASE_OFS {}
|
||||
#[doc = "BASE Offset Register"]
|
||||
pub mod base_ofs;
|
||||
#[doc = "ADC Offset Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ofs](ofs) module"]
|
||||
pub type OFS = crate::Reg<u32, _OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _OFS;
|
||||
#[doc = "`read()` method returns [ofs::R](ofs::R) reader structure"]
|
||||
impl crate::Readable for OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [ofs::W](ofs::W) writer structure"]
|
||||
impl crate::Writable for OFS {}
|
||||
#[doc = "ADC Offset Correction Register"]
|
||||
pub mod ofs;
|
||||
#[doc = "USER Offset Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usr_ofs](usr_ofs) module"]
|
||||
pub type USR_OFS = crate::Reg<u32, _USR_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _USR_OFS;
|
||||
#[doc = "`read()` method returns [usr_ofs::R](usr_ofs::R) reader structure"]
|
||||
impl crate::Readable for USR_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [usr_ofs::W](usr_ofs::W) writer structure"]
|
||||
impl crate::Writable for USR_OFS {}
|
||||
#[doc = "USER Offset Correction Register"]
|
||||
pub mod usr_ofs;
|
||||
#[doc = "ADC X Offset Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xofs](xofs) module"]
|
||||
pub type XOFS = crate::Reg<u32, _XOFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _XOFS;
|
||||
#[doc = "`read()` method returns [xofs::R](xofs::R) reader structure"]
|
||||
impl crate::Readable for XOFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [xofs::W](xofs::W) writer structure"]
|
||||
impl crate::Writable for XOFS {}
|
||||
#[doc = "ADC X Offset Correction Register"]
|
||||
pub mod xofs;
|
||||
#[doc = "ADC Y Offset Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [yofs](yofs) module"]
|
||||
pub type YOFS = crate::Reg<u32, _YOFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _YOFS;
|
||||
#[doc = "`read()` method returns [yofs::R](yofs::R) reader structure"]
|
||||
impl crate::Readable for YOFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [yofs::W](yofs::W) writer structure"]
|
||||
impl crate::Writable for YOFS {}
|
||||
#[doc = "ADC Y Offset Correction Register"]
|
||||
pub mod yofs;
|
||||
#[doc = "ADC Gain Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [g](g) module"]
|
||||
pub type G = crate::Reg<u32, _G>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _G;
|
||||
#[doc = "`read()` method returns [g::R](g::R) reader structure"]
|
||||
impl crate::Readable for G {}
|
||||
#[doc = "`write(|w| ..)` method takes [g::W](g::W) writer structure"]
|
||||
impl crate::Writable for G {}
|
||||
#[doc = "ADC Gain Register"]
|
||||
pub mod g;
|
||||
#[doc = "ADC User Gain Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ug](ug) module"]
|
||||
pub type UG = crate::Reg<u32, _UG>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _UG;
|
||||
#[doc = "`read()` method returns [ug::R](ug::R) reader structure"]
|
||||
impl crate::Readable for UG {}
|
||||
#[doc = "`write(|w| ..)` method takes [ug::W](ug::W) writer structure"]
|
||||
impl crate::Writable for UG {}
|
||||
#[doc = "ADC User Gain Register"]
|
||||
pub mod ug;
|
||||
#[doc = "ADC General Calibration Value Register S\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clps](clps) module"]
|
||||
pub type CLPS = crate::Reg<u32, _CLPS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLPS;
|
||||
#[doc = "`read()` method returns [clps::R](clps::R) reader structure"]
|
||||
impl crate::Readable for CLPS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clps::W](clps::W) writer structure"]
|
||||
impl crate::Writable for CLPS {}
|
||||
#[doc = "ADC General Calibration Value Register S"]
|
||||
pub mod clps;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp3](clp3) module"]
|
||||
pub type CLP3 = crate::Reg<u32, _CLP3>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP3;
|
||||
#[doc = "`read()` method returns [clp3::R](clp3::R) reader structure"]
|
||||
impl crate::Readable for CLP3 {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp3::W](clp3::W) writer structure"]
|
||||
impl crate::Writable for CLP3 {}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
|
||||
pub mod clp3;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp2](clp2) module"]
|
||||
pub type CLP2 = crate::Reg<u32, _CLP2>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP2;
|
||||
#[doc = "`read()` method returns [clp2::R](clp2::R) reader structure"]
|
||||
impl crate::Readable for CLP2 {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp2::W](clp2::W) writer structure"]
|
||||
impl crate::Writable for CLP2 {}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
|
||||
pub mod clp2;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp1](clp1) module"]
|
||||
pub type CLP1 = crate::Reg<u32, _CLP1>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP1;
|
||||
#[doc = "`read()` method returns [clp1::R](clp1::R) reader structure"]
|
||||
impl crate::Readable for CLP1 {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp1::W](clp1::W) writer structure"]
|
||||
impl crate::Writable for CLP1 {}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
|
||||
pub mod clp1;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp0](clp0) module"]
|
||||
pub type CLP0 = crate::Reg<u32, _CLP0>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP0;
|
||||
#[doc = "`read()` method returns [clp0::R](clp0::R) reader structure"]
|
||||
impl crate::Readable for CLP0 {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp0::W](clp0::W) writer structure"]
|
||||
impl crate::Writable for CLP0 {}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
|
||||
pub mod clp0;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register X\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clpx](clpx) module"]
|
||||
pub type CLPX = crate::Reg<u32, _CLPX>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLPX;
|
||||
#[doc = "`read()` method returns [clpx::R](clpx::R) reader structure"]
|
||||
impl crate::Readable for CLPX {}
|
||||
#[doc = "`write(|w| ..)` method takes [clpx::W](clpx::W) writer structure"]
|
||||
impl crate::Writable for CLPX {}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register X"]
|
||||
pub mod clpx;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 9\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp9](clp9) module"]
|
||||
pub type CLP9 = crate::Reg<u32, _CLP9>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP9;
|
||||
#[doc = "`read()` method returns [clp9::R](clp9::R) reader structure"]
|
||||
impl crate::Readable for CLP9 {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp9::W](clp9::W) writer structure"]
|
||||
impl crate::Writable for CLP9 {}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
|
||||
pub mod clp9;
|
||||
#[doc = "ADC General Calibration Offset Value Register S\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clps_ofs](clps_ofs) module"]
|
||||
pub type CLPS_OFS = crate::Reg<u32, _CLPS_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLPS_OFS;
|
||||
#[doc = "`read()` method returns [clps_ofs::R](clps_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLPS_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clps_ofs::W](clps_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLPS_OFS {}
|
||||
#[doc = "ADC General Calibration Offset Value Register S"]
|
||||
pub mod clps_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp3_ofs](clp3_ofs) module"]
|
||||
pub type CLP3_OFS = crate::Reg<u32, _CLP3_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP3_OFS;
|
||||
#[doc = "`read()` method returns [clp3_ofs::R](clp3_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLP3_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp3_ofs::W](clp3_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLP3_OFS {}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub mod clp3_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp2_ofs](clp2_ofs) module"]
|
||||
pub type CLP2_OFS = crate::Reg<u32, _CLP2_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP2_OFS;
|
||||
#[doc = "`read()` method returns [clp2_ofs::R](clp2_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLP2_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp2_ofs::W](clp2_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLP2_OFS {}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub mod clp2_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp1_ofs](clp1_ofs) module"]
|
||||
pub type CLP1_OFS = crate::Reg<u32, _CLP1_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP1_OFS;
|
||||
#[doc = "`read()` method returns [clp1_ofs::R](clp1_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLP1_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp1_ofs::W](clp1_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLP1_OFS {}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub mod clp1_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp0_ofs](clp0_ofs) module"]
|
||||
pub type CLP0_OFS = crate::Reg<u32, _CLP0_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP0_OFS;
|
||||
#[doc = "`read()` method returns [clp0_ofs::R](clp0_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLP0_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp0_ofs::W](clp0_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLP0_OFS {}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub mod clp0_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clpx_ofs](clpx_ofs) module"]
|
||||
pub type CLPX_OFS = crate::Reg<u32, _CLPX_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLPX_OFS;
|
||||
#[doc = "`read()` method returns [clpx_ofs::R](clpx_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLPX_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clpx_ofs::W](clpx_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLPX_OFS {}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub mod clpx_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp9_ofs](clp9_ofs) module"]
|
||||
pub type CLP9_OFS = crate::Reg<u32, _CLP9_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP9_OFS;
|
||||
#[doc = "`read()` method returns [clp9_ofs::R](clp9_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLP9_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp9_ofs::W](clp9_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLP9_OFS {}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub mod clp9_ofs;
|
||||
|
||||
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::BASE_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct BA_OFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl BA_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _BA_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _BA_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn ba_ofs(&self) -> BA_OFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
BA_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 64 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn ba_ofs(&mut self) -> _BA_OFSW {
|
||||
_BA_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register BASE_OFS"]
|
||||
pub type R = crate::R<u32, super::BASE_OFS>;
|
||||
#[doc = "Writer for register BASE_OFS"]
|
||||
pub type W = crate::W<u32, super::BASE_OFS>;
|
||||
#[doc = "Register BASE_OFS `reset()`'s with value 0x40"]
|
||||
impl crate::ResetValue for super::BASE_OFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x40
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `BA_OFS`"]
|
||||
pub type BA_OFS_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `BA_OFS`"]
|
||||
pub struct BA_OFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> BA_OFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline(always)]
|
||||
pub fn ba_ofs(&self) -> BA_OFS_R {
|
||||
BA_OFS_R::new((self.bits & 0xff) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline(always)]
|
||||
pub fn ba_ofs(&mut self) -> BA_OFS_W {
|
||||
BA_OFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
||||
820
src/adc0/cfg1.rs
820
src/adc0/cfg1.rs
@ -1,482 +1,338 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CFG1 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `ADICLK`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADICLKR {
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
_00,
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
_01,
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
_10,
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
_11,
|
||||
}
|
||||
impl ADICLKR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADICLKR::_00 => 0,
|
||||
ADICLKR::_01 => 1,
|
||||
ADICLKR::_10 => 2,
|
||||
ADICLKR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> ADICLKR {
|
||||
match value {
|
||||
0 => ADICLKR::_00,
|
||||
1 => ADICLKR::_01,
|
||||
2 => ADICLKR::_10,
|
||||
3 => ADICLKR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == ADICLKR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == ADICLKR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == ADICLKR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == ADICLKR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `MODE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum MODER {
|
||||
#[doc = "8-bit conversion."]
|
||||
_00,
|
||||
#[doc = "12-bit conversion."]
|
||||
_01,
|
||||
#[doc = "10-bit conversion."]
|
||||
_10,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
}
|
||||
impl MODER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
MODER::_00 => 0,
|
||||
MODER::_01 => 1,
|
||||
MODER::_10 => 2,
|
||||
MODER::_Reserved(bits) => bits,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> MODER {
|
||||
match value {
|
||||
0 => MODER::_00,
|
||||
1 => MODER::_01,
|
||||
2 => MODER::_10,
|
||||
i => MODER::_Reserved(i),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == MODER::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == MODER::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == MODER::_10
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `ADIV`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADIVR {
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
_00,
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
_01,
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
_10,
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
_11,
|
||||
}
|
||||
impl ADIVR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADIVR::_00 => 0,
|
||||
ADIVR::_01 => 1,
|
||||
ADIVR::_10 => 2,
|
||||
ADIVR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> ADIVR {
|
||||
match value {
|
||||
0 => ADIVR::_00,
|
||||
1 => ADIVR::_01,
|
||||
2 => ADIVR::_10,
|
||||
3 => ADIVR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == ADIVR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == ADIVR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == ADIVR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == ADIVR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADICLK`"]
|
||||
pub enum ADICLKW {
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
_00,
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
_01,
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
_10,
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
_11,
|
||||
}
|
||||
impl ADICLKW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADICLKW::_00 => 0,
|
||||
ADICLKW::_01 => 1,
|
||||
ADICLKW::_10 => 2,
|
||||
ADICLKW::_11 => 3,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _ADICLKW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _ADICLKW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: ADICLKW) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_00)
|
||||
}
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_01)
|
||||
}
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_10)
|
||||
}
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
#[inline]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_11)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `MODE`"]
|
||||
pub enum MODEW {
|
||||
#[doc = "8-bit conversion."]
|
||||
_00,
|
||||
#[doc = "12-bit conversion."]
|
||||
_01,
|
||||
#[doc = "10-bit conversion."]
|
||||
_10,
|
||||
}
|
||||
impl MODEW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
MODEW::_00 => 0,
|
||||
MODEW::_01 => 1,
|
||||
MODEW::_10 => 2,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _MODEW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _MODEW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: MODEW) -> &'a mut W {
|
||||
unsafe { self.bits(variant._bits()) }
|
||||
}
|
||||
#[doc = "8-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(MODEW::_00)
|
||||
}
|
||||
#[doc = "12-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(MODEW::_01)
|
||||
}
|
||||
#[doc = "10-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(MODEW::_10)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 2;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADIV`"]
|
||||
pub enum ADIVW {
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
_00,
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
_01,
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
_10,
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
_11,
|
||||
}
|
||||
impl ADIVW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADIVW::_00 => 0,
|
||||
ADIVW::_01 => 1,
|
||||
ADIVW::_10 => 2,
|
||||
ADIVW::_11 => 3,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _ADIVW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _ADIVW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: ADIVW) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_00)
|
||||
}
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_01)
|
||||
}
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_10)
|
||||
}
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
#[inline]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_11)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 5;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLRLTRGW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLRLTRGW<'a> {
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool | ||||