s32k118: rewrite everything for s32k118
Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
parent
444b0e87d1
commit
96cd7368a2
@ -1,12 +1,12 @@
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[package]
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authors = ["Kjetil Kjeka <kjetilkjeka@gmail.com>"]
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name = "s32k144"
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name = "s32k118"
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version = "0.10.0"
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description = "Peripheral access API for NXP S32K144 microcontrollers (generated using svd2rust)"
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description = "Peripheral access API for NXP S32K118 microcontrollers (generated using svd2rust)"
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repository = "https://github.com/kjetilkjeka/s32k144.rs"
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keywords = ["arm", "embedded", "svd2rust", "cortex-m4", "NXP"]
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keywords = ["arm", "embedded", "svd2rust", "cortex-m0", "NXP"]
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categories = ["embedded", "hardware-support", "no-std"]
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license = "Apache-2.0/MIT"
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File diff suppressed because it is too large
Load Diff
96
device.x
96
device.x
@ -2,88 +2,32 @@ PROVIDE(DMA0 = DefaultHandler);
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PROVIDE(DMA1 = DefaultHandler);
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PROVIDE(DMA2 = DefaultHandler);
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PROVIDE(DMA3 = DefaultHandler);
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PROVIDE(DMA4 = DefaultHandler);
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PROVIDE(DMA5 = DefaultHandler);
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PROVIDE(DMA6 = DefaultHandler);
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PROVIDE(DMA7 = DefaultHandler);
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PROVIDE(DMA8 = DefaultHandler);
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PROVIDE(DMA9 = DefaultHandler);
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PROVIDE(DMA10 = DefaultHandler);
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PROVIDE(DMA11 = DefaultHandler);
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PROVIDE(DMA12 = DefaultHandler);
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PROVIDE(DMA13 = DefaultHandler);
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PROVIDE(DMA14 = DefaultHandler);
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PROVIDE(DMA15 = DefaultHandler);
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PROVIDE(DMA_ERROR = DefaultHandler);
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PROVIDE(MCM = DefaultHandler);
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PROVIDE(FTFC = DefaultHandler);
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PROVIDE(READ_COLLISION = DefaultHandler);
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PROVIDE(LVD_LVW = DefaultHandler);
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PROVIDE(FTFC_FAULT = DefaultHandler);
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PROVIDE(WDOG_EWM = DefaultHandler);
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PROVIDE(RCM = DefaultHandler);
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PROVIDE(LPI2C0_MASTER = DefaultHandler);
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PROVIDE(LPI2C0_SLAVE = DefaultHandler);
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PROVIDE(LPSPI0 = DefaultHandler);
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PROVIDE(LPSPI1 = DefaultHandler);
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PROVIDE(LPSPI2 = DefaultHandler);
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PROVIDE(LPUART0_RXTX = DefaultHandler);
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PROVIDE(LPUART1_RXTX = DefaultHandler);
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PROVIDE(LPUART2_RXTX = DefaultHandler);
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PROVIDE(ADC0 = DefaultHandler);
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PROVIDE(ADC1 = DefaultHandler);
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PROVIDE(CMP0 = DefaultHandler);
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PROVIDE(ERM_SINGLE_FAULT = DefaultHandler);
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PROVIDE(ERM_DOUBLE_FAULT = DefaultHandler);
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PROVIDE(ERM_FAULT = DefaultHandler);
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PROVIDE(RTC = DefaultHandler);
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PROVIDE(RTC_SECONDS = DefaultHandler);
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PROVIDE(LPIT0_CH0 = DefaultHandler);
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PROVIDE(LPIT0_CH1 = DefaultHandler);
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PROVIDE(LPIT0_CH2 = DefaultHandler);
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PROVIDE(LPIT0_CH3 = DefaultHandler);
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PROVIDE(PDB0 = DefaultHandler);
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PROVIDE(SCG = DefaultHandler);
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PROVIDE(LPTMR0 = DefaultHandler);
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PROVIDE(PORTA = DefaultHandler);
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PROVIDE(PORTB = DefaultHandler);
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PROVIDE(PORTC = DefaultHandler);
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PROVIDE(PORTD = DefaultHandler);
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PROVIDE(PORTE = DefaultHandler);
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PROVIDE(PDB1 = DefaultHandler);
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PROVIDE(FLEXIO = DefaultHandler);
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PROVIDE(CAN0_ORED = DefaultHandler);
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PROVIDE(CAN0_ERROR = DefaultHandler);
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PROVIDE(CAN0_WAKE_UP = DefaultHandler);
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PROVIDE(CAN0_ORED_0_15_MB = DefaultHandler);
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PROVIDE(CAN0_ORED_16_31_MB = DefaultHandler);
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PROVIDE(CAN1_ORED = DefaultHandler);
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PROVIDE(CAN1_ERROR = DefaultHandler);
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PROVIDE(CAN1_ORED_0_15_MB = DefaultHandler);
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PROVIDE(CAN2_ORED = DefaultHandler);
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PROVIDE(CAN2_ERROR = DefaultHandler);
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PROVIDE(CAN2_ORED_0_15_MB = DefaultHandler);
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PROVIDE(FTM0_CH0_CH1 = DefaultHandler);
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PROVIDE(FTM0_CH2_CH3 = DefaultHandler);
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PROVIDE(FTM0_CH4_CH5 = DefaultHandler);
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PROVIDE(FTM0_CH6_CH7 = DefaultHandler);
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PROVIDE(PORT = DefaultHandler);
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PROVIDE(CAN0_ORED_ERR_WAKEUP = DefaultHandler);
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PROVIDE(CAN0_ORED_0_31_MB = DefaultHandler);
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PROVIDE(FTM0_CH0_7 = DefaultHandler);
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PROVIDE(FTM0_FAULT = DefaultHandler);
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PROVIDE(FTM0_OVF_RELOAD = DefaultHandler);
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PROVIDE(FTM1_CH0_CH1 = DefaultHandler);
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PROVIDE(FTM1_CH2_CH3 = DefaultHandler);
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PROVIDE(FTM1_CH4_CH5 = DefaultHandler);
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PROVIDE(FTM1_CH6_CH7 = DefaultHandler);
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PROVIDE(FTM1_CH0_7 = DefaultHandler);
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PROVIDE(FTM1_FAULT = DefaultHandler);
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PROVIDE(FTM1_OVF_RELOAD = DefaultHandler);
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PROVIDE(FTM2_CH0_CH1 = DefaultHandler);
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PROVIDE(FTM2_CH2_CH3 = DefaultHandler);
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PROVIDE(FTM2_CH4_CH5 = DefaultHandler);
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PROVIDE(FTM2_CH6_CH7 = DefaultHandler);
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PROVIDE(FTM2_FAULT = DefaultHandler);
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PROVIDE(FTM2_OVF_RELOAD = DefaultHandler);
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PROVIDE(FTM3_CH0_CH1 = DefaultHandler);
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PROVIDE(FTM3_CH2_CH3 = DefaultHandler);
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PROVIDE(FTM3_CH4_CH5 = DefaultHandler);
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PROVIDE(FTM3_CH6_CH7 = DefaultHandler);
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PROVIDE(FTM3_FAULT = DefaultHandler);
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PROVIDE(FTM3_OVF_RELOAD = DefaultHandler);
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PROVIDE(FTFC = DefaultHandler);
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PROVIDE(PDB0 = DefaultHandler);
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PROVIDE(LPIT0 = DefaultHandler);
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PROVIDE(SCG_CMU_LVD_LVWSCG = DefaultHandler);
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PROVIDE(WDOG = DefaultHandler);
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PROVIDE(RCM = DefaultHandler);
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PROVIDE(LPI2C0_MASTER_SLAVE = DefaultHandler);
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PROVIDE(FLEXIO = DefaultHandler);
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PROVIDE(LPSPI0 = DefaultHandler);
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PROVIDE(LPSPI1 = DefaultHandler);
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PROVIDE(ADC0 = DefaultHandler);
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PROVIDE(CMP0 = DefaultHandler);
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PROVIDE(LPUART1_RXTX = DefaultHandler);
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PROVIDE(LPUART0_RXTX = DefaultHandler);
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718
src/adc0.rs
718
src/adc0.rs
@ -1,290 +1,428 @@
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#[doc = r" Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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#[doc = "0x00 - ADC Status and Control Register 1"]
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pub sc1a: SC1,
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#[doc = "0x04 - ADC Status and Control Register 1"]
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pub sc1b: SC1,
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#[doc = "0x08 - ADC Status and Control Register 1"]
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pub sc1c: SC1,
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#[doc = "0x0c - ADC Status and Control Register 1"]
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pub sc1d: SC1,
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#[doc = "0x10 - ADC Status and Control Register 1"]
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pub sc1e: SC1,
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#[doc = "0x14 - ADC Status and Control Register 1"]
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pub sc1f: SC1,
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#[doc = "0x18 - ADC Status and Control Register 1"]
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pub sc1g: SC1,
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#[doc = "0x1c - ADC Status and Control Register 1"]
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pub sc1h: SC1,
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#[doc = "0x20 - ADC Status and Control Register 1"]
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pub sc1i: SC1,
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#[doc = "0x24 - ADC Status and Control Register 1"]
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pub sc1j: SC1,
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#[doc = "0x28 - ADC Status and Control Register 1"]
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pub sc1k: SC1,
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#[doc = "0x2c - ADC Status and Control Register 1"]
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pub sc1l: SC1,
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#[doc = "0x30 - ADC Status and Control Register 1"]
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pub sc1m: SC1,
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#[doc = "0x34 - ADC Status and Control Register 1"]
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pub sc1n: SC1,
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#[doc = "0x38 - ADC Status and Control Register 1"]
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pub sc1o: SC1,
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#[doc = "0x3c - ADC Status and Control Register 1"]
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pub sc1p: SC1,
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#[doc = "0x40 - ADC Configuration Register 1"]
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pub cfg1: CFG1,
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#[doc = "0x44 - ADC Configuration Register 2"]
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pub cfg2: CFG2,
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#[doc = "0x48 - ADC Data Result Registers"]
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pub ra: R,
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#[doc = "0x4c - ADC Data Result Registers"]
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pub rb: R,
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#[doc = "0x50 - ADC Data Result Registers"]
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pub rc: R,
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#[doc = "0x54 - ADC Data Result Registers"]
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pub rd: R,
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#[doc = "0x58 - ADC Data Result Registers"]
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pub re: R,
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#[doc = "0x5c - ADC Data Result Registers"]
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pub rf: R,
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#[doc = "0x60 - ADC Data Result Registers"]
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pub rg: R,
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#[doc = "0x64 - ADC Data Result Registers"]
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pub rh: R,
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#[doc = "0x68 - ADC Data Result Registers"]
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pub ri: R,
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#[doc = "0x6c - ADC Data Result Registers"]
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pub rj: R,
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#[doc = "0x70 - ADC Data Result Registers"]
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pub rk: R,
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#[doc = "0x74 - ADC Data Result Registers"]
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pub rl: R,
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#[doc = "0x78 - ADC Data Result Registers"]
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pub rm: R,
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#[doc = "0x7c - ADC Data Result Registers"]
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pub rn: R,
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#[doc = "0x80 - ADC Data Result Registers"]
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pub ro: R,
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#[doc = "0x84 - ADC Data Result Registers"]
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pub rp: R,
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#[doc = "0x88 - Compare Value Registers"]
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pub cv1: CV,
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#[doc = "0x8c - Compare Value Registers"]
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pub cv2: CV,
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#[doc = "0x90 - Status and Control Register 2"]
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pub sc2: SC2,
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#[doc = "0x94 - Status and Control Register 3"]
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pub sc3: SC3,
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#[doc = "0x98 - BASE Offset Register"]
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pub base_ofs: BASE_OFS,
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#[doc = "0x9c - ADC Offset Correction Register"]
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pub ofs: OFS,
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#[doc = "0xa0 - USER Offset Correction Register"]
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pub usr_ofs: USR_OFS,
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#[doc = "0xa4 - ADC X Offset Correction Register"]
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pub xofs: XOFS,
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#[doc = "0xa8 - ADC Y Offset Correction Register"]
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pub yofs: YOFS,
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#[doc = "0xac - ADC Gain Register"]
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pub g: G,
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#[doc = "0xb0 - ADC User Gain Register"]
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pub ug: UG,
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#[doc = "0xb4 - ADC General Calibration Value Register S"]
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pub clps: CLPS,
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#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
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pub clp3: CLP3,
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#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
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pub clp2: CLP2,
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#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
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pub clp1: CLP1,
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#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
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pub clp0: CLP0,
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#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
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pub clpx: CLPX,
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#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
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pub clp9: CLP9,
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#[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
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pub clps_ofs: CLPS_OFS,
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#[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
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pub clp3_ofs: CLP3_OFS,
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#[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
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pub clp2_ofs: CLP2_OFS,
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#[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
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pub clp1_ofs: CLP1_OFS,
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#[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
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pub clp0_ofs: CLP0_OFS,
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#[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
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pub clpx_ofs: CLPX_OFS,
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#[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
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pub clp9_ofs: CLP9_OFS,
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}
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#[doc = "ADC Status and Control Register 1"]
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pub struct SC1 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Status and Control Register 1"]
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pub mod sc1;
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#[doc = "ADC Configuration Register 1"]
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pub struct CFG1 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Configuration Register 1"]
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pub mod cfg1;
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#[doc = "ADC Configuration Register 2"]
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pub struct CFG2 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Configuration Register 2"]
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pub mod cfg2;
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#[doc = "ADC Data Result Registers"]
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pub struct R {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Data Result Registers"]
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pub mod r;
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#[doc = "Compare Value Registers"]
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pub struct CV {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Compare Value Registers"]
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pub mod cv;
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#[doc = "Status and Control Register 2"]
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pub struct SC2 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Status and Control Register 2"]
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pub mod sc2;
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#[doc = "Status and Control Register 3"]
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pub struct SC3 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "Status and Control Register 3"]
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pub mod sc3;
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#[doc = "BASE Offset Register"]
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pub struct BASE_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "BASE Offset Register"]
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pub mod base_ofs;
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#[doc = "ADC Offset Correction Register"]
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pub struct OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Offset Correction Register"]
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pub mod ofs;
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#[doc = "USER Offset Correction Register"]
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pub struct USR_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "USER Offset Correction Register"]
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pub mod usr_ofs;
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#[doc = "ADC X Offset Correction Register"]
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pub struct XOFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC X Offset Correction Register"]
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pub mod xofs;
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#[doc = "ADC Y Offset Correction Register"]
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pub struct YOFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Y Offset Correction Register"]
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pub mod yofs;
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#[doc = "ADC Gain Register"]
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pub struct G {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Gain Register"]
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pub mod g;
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#[doc = "ADC User Gain Register"]
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pub struct UG {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC User Gain Register"]
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pub mod ug;
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#[doc = "ADC General Calibration Value Register S"]
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pub struct CLPS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC General Calibration Value Register S"]
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pub mod clps;
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#[doc = "ADC Plus-Side General Calibration Value Register 3"]
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pub struct CLP3 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 3"]
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pub mod clp3;
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#[doc = "ADC Plus-Side General Calibration Value Register 2"]
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pub struct CLP2 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 2"]
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pub mod clp2;
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#[doc = "ADC Plus-Side General Calibration Value Register 1"]
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pub struct CLP1 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 1"]
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pub mod clp1;
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#[doc = "ADC Plus-Side General Calibration Value Register 0"]
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pub struct CLP0 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 0"]
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pub mod clp0;
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#[doc = "ADC Plus-Side General Calibration Value Register X"]
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pub struct CLPX {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register X"]
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pub mod clpx;
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#[doc = "ADC Plus-Side General Calibration Value Register 9"]
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pub struct CLP9 {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Value Register 9"]
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pub mod clp9;
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#[doc = "ADC General Calibration Offset Value Register S"]
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pub struct CLPS_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC General Calibration Offset Value Register S"]
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pub mod clps_ofs;
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
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pub struct CLP3_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
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pub mod clp3_ofs;
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
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pub struct CLP2_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
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pub mod clp2_ofs;
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
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pub struct CLP1_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
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pub mod clp1_ofs;
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#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
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pub struct CLP0_OFS {
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register: ::vcell::VolatileCell<u32>,
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}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub mod clp0_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub struct CLPX_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub mod clpx_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub struct CLP9_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub mod clp9_ofs;
|
||||
#[doc = r"Register block"]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
#[doc = "0x00 - ADC Status and Control Register 1"]
|
||||
pub sc1a: SC1,
|
||||
#[doc = "0x04 - ADC Status and Control Register 1"]
|
||||
pub sc1b: SC1,
|
||||
#[doc = "0x08 - ADC Status and Control Register 1"]
|
||||
pub sc1c: SC1,
|
||||
#[doc = "0x0c - ADC Status and Control Register 1"]
|
||||
pub sc1d: SC1,
|
||||
#[doc = "0x10 - ADC Status and Control Register 1"]
|
||||
pub sc1e: SC1,
|
||||
#[doc = "0x14 - ADC Status and Control Register 1"]
|
||||
pub sc1f: SC1,
|
||||
#[doc = "0x18 - ADC Status and Control Register 1"]
|
||||
pub sc1g: SC1,
|
||||
#[doc = "0x1c - ADC Status and Control Register 1"]
|
||||
pub sc1h: SC1,
|
||||
#[doc = "0x20 - ADC Status and Control Register 1"]
|
||||
pub sc1i: SC1,
|
||||
#[doc = "0x24 - ADC Status and Control Register 1"]
|
||||
pub sc1j: SC1,
|
||||
#[doc = "0x28 - ADC Status and Control Register 1"]
|
||||
pub sc1k: SC1,
|
||||
#[doc = "0x2c - ADC Status and Control Register 1"]
|
||||
pub sc1l: SC1,
|
||||
#[doc = "0x30 - ADC Status and Control Register 1"]
|
||||
pub sc1m: SC1,
|
||||
#[doc = "0x34 - ADC Status and Control Register 1"]
|
||||
pub sc1n: SC1,
|
||||
#[doc = "0x38 - ADC Status and Control Register 1"]
|
||||
pub sc1o: SC1,
|
||||
#[doc = "0x3c - ADC Status and Control Register 1"]
|
||||
pub sc1p: SC1,
|
||||
#[doc = "0x40 - ADC Configuration Register 1"]
|
||||
pub cfg1: CFG1,
|
||||
#[doc = "0x44 - ADC Configuration Register 2"]
|
||||
pub cfg2: CFG2,
|
||||
#[doc = "0x48 - ADC Data Result Registers"]
|
||||
pub ra: R,
|
||||
#[doc = "0x4c - ADC Data Result Registers"]
|
||||
pub rb: R,
|
||||
#[doc = "0x50 - ADC Data Result Registers"]
|
||||
pub rc: R,
|
||||
#[doc = "0x54 - ADC Data Result Registers"]
|
||||
pub rd: R,
|
||||
#[doc = "0x58 - ADC Data Result Registers"]
|
||||
pub re: R,
|
||||
#[doc = "0x5c - ADC Data Result Registers"]
|
||||
pub rf: R,
|
||||
#[doc = "0x60 - ADC Data Result Registers"]
|
||||
pub rg: R,
|
||||
#[doc = "0x64 - ADC Data Result Registers"]
|
||||
pub rh: R,
|
||||
#[doc = "0x68 - ADC Data Result Registers"]
|
||||
pub ri: R,
|
||||
#[doc = "0x6c - ADC Data Result Registers"]
|
||||
pub rj: R,
|
||||
#[doc = "0x70 - ADC Data Result Registers"]
|
||||
pub rk: R,
|
||||
#[doc = "0x74 - ADC Data Result Registers"]
|
||||
pub rl: R,
|
||||
#[doc = "0x78 - ADC Data Result Registers"]
|
||||
pub rm: R,
|
||||
#[doc = "0x7c - ADC Data Result Registers"]
|
||||
pub rn: R,
|
||||
#[doc = "0x80 - ADC Data Result Registers"]
|
||||
pub ro: R,
|
||||
#[doc = "0x84 - ADC Data Result Registers"]
|
||||
pub rp: R,
|
||||
#[doc = "0x88 - Compare Value Registers"]
|
||||
pub cv1: CV,
|
||||
#[doc = "0x8c - Compare Value Registers"]
|
||||
pub cv2: CV,
|
||||
#[doc = "0x90 - Status and Control Register 2"]
|
||||
pub sc2: SC2,
|
||||
#[doc = "0x94 - Status and Control Register 3"]
|
||||
pub sc3: SC3,
|
||||
#[doc = "0x98 - BASE Offset Register"]
|
||||
pub base_ofs: BASE_OFS,
|
||||
#[doc = "0x9c - ADC Offset Correction Register"]
|
||||
pub ofs: OFS,
|
||||
#[doc = "0xa0 - USER Offset Correction Register"]
|
||||
pub usr_ofs: USR_OFS,
|
||||
#[doc = "0xa4 - ADC X Offset Correction Register"]
|
||||
pub xofs: XOFS,
|
||||
#[doc = "0xa8 - ADC Y Offset Correction Register"]
|
||||
pub yofs: YOFS,
|
||||
#[doc = "0xac - ADC Gain Register"]
|
||||
pub g: G,
|
||||
#[doc = "0xb0 - ADC User Gain Register"]
|
||||
pub ug: UG,
|
||||
#[doc = "0xb4 - ADC General Calibration Value Register S"]
|
||||
pub clps: CLPS,
|
||||
#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
|
||||
pub clp3: CLP3,
|
||||
#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
|
||||
pub clp2: CLP2,
|
||||
#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
|
||||
pub clp1: CLP1,
|
||||
#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
|
||||
pub clp0: CLP0,
|
||||
#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
|
||||
pub clpx: CLPX,
|
||||
#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
|
||||
pub clp9: CLP9,
|
||||
#[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
|
||||
pub clps_ofs: CLPS_OFS,
|
||||
#[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub clp3_ofs: CLP3_OFS,
|
||||
#[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub clp2_ofs: CLP2_OFS,
|
||||
#[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub clp1_ofs: CLP1_OFS,
|
||||
#[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub clp0_ofs: CLP0_OFS,
|
||||
#[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub clpx_ofs: CLPX_OFS,
|
||||
#[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub clp9_ofs: CLP9_OFS,
|
||||
}
|
||||
#[doc = "ADC Status and Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sc1](sc1) module"]
|
||||
pub type SC1 = crate::Reg<u32, _SC1>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _SC1;
|
||||
#[doc = "`read()` method returns [sc1::R](sc1::R) reader structure"]
|
||||
impl crate::Readable for SC1 {}
|
||||
#[doc = "`write(|w| ..)` method takes [sc1::W](sc1::W) writer structure"]
|
||||
impl crate::Writable for SC1 {}
|
||||
#[doc = "ADC Status and Control Register 1"]
|
||||
pub mod sc1;
|
||||
#[doc = "ADC Configuration Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg1](cfg1) module"]
|
||||
pub type CFG1 = crate::Reg<u32, _CFG1>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CFG1;
|
||||
#[doc = "`read()` method returns [cfg1::R](cfg1::R) reader structure"]
|
||||
impl crate::Readable for CFG1 {}
|
||||
#[doc = "`write(|w| ..)` method takes [cfg1::W](cfg1::W) writer structure"]
|
||||
impl crate::Writable for CFG1 {}
|
||||
#[doc = "ADC Configuration Register 1"]
|
||||
pub mod cfg1;
|
||||
#[doc = "ADC Configuration Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg2](cfg2) module"]
|
||||
pub type CFG2 = crate::Reg<u32, _CFG2>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CFG2;
|
||||
#[doc = "`read()` method returns [cfg2::R](cfg2::R) reader structure"]
|
||||
impl crate::Readable for CFG2 {}
|
||||
#[doc = "`write(|w| ..)` method takes [cfg2::W](cfg2::W) writer structure"]
|
||||
impl crate::Writable for CFG2 {}
|
||||
#[doc = "ADC Configuration Register 2"]
|
||||
pub mod cfg2;
|
||||
#[doc = "ADC Data Result Registers\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r](r) module"]
|
||||
pub type R = crate::Reg<u32, _R>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _R;
|
||||
#[doc = "`read()` method returns [r::R](r::R) reader structure"]
|
||||
impl crate::Readable for R {}
|
||||
#[doc = "ADC Data Result Registers"]
|
||||
pub mod r;
|
||||
#[doc = "Compare Value Registers\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cv](cv) module"]
|
||||
pub type CV = crate::Reg<u32, _CV>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CV;
|
||||
#[doc = "`read()` method returns [cv::R](cv::R) reader structure"]
|
||||
impl crate::Readable for CV {}
|
||||
#[doc = "`write(|w| ..)` method takes [cv::W](cv::W) writer structure"]
|
||||
impl crate::Writable for CV {}
|
||||
#[doc = "Compare Value Registers"]
|
||||
pub mod cv;
|
||||
#[doc = "Status and Control Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sc2](sc2) module"]
|
||||
pub type SC2 = crate::Reg<u32, _SC2>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _SC2;
|
||||
#[doc = "`read()` method returns [sc2::R](sc2::R) reader structure"]
|
||||
impl crate::Readable for SC2 {}
|
||||
#[doc = "`write(|w| ..)` method takes [sc2::W](sc2::W) writer structure"]
|
||||
impl crate::Writable for SC2 {}
|
||||
#[doc = "Status and Control Register 2"]
|
||||
pub mod sc2;
|
||||
#[doc = "Status and Control Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sc3](sc3) module"]
|
||||
pub type SC3 = crate::Reg<u32, _SC3>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _SC3;
|
||||
#[doc = "`read()` method returns [sc3::R](sc3::R) reader structure"]
|
||||
impl crate::Readable for SC3 {}
|
||||
#[doc = "`write(|w| ..)` method takes [sc3::W](sc3::W) writer structure"]
|
||||
impl crate::Writable for SC3 {}
|
||||
#[doc = "Status and Control Register 3"]
|
||||
pub mod sc3;
|
||||
#[doc = "BASE Offset Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base_ofs](base_ofs) module"]
|
||||
pub type BASE_OFS = crate::Reg<u32, _BASE_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _BASE_OFS;
|
||||
#[doc = "`read()` method returns [base_ofs::R](base_ofs::R) reader structure"]
|
||||
impl crate::Readable for BASE_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [base_ofs::W](base_ofs::W) writer structure"]
|
||||
impl crate::Writable for BASE_OFS {}
|
||||
#[doc = "BASE Offset Register"]
|
||||
pub mod base_ofs;
|
||||
#[doc = "ADC Offset Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ofs](ofs) module"]
|
||||
pub type OFS = crate::Reg<u32, _OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _OFS;
|
||||
#[doc = "`read()` method returns [ofs::R](ofs::R) reader structure"]
|
||||
impl crate::Readable for OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [ofs::W](ofs::W) writer structure"]
|
||||
impl crate::Writable for OFS {}
|
||||
#[doc = "ADC Offset Correction Register"]
|
||||
pub mod ofs;
|
||||
#[doc = "USER Offset Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usr_ofs](usr_ofs) module"]
|
||||
pub type USR_OFS = crate::Reg<u32, _USR_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _USR_OFS;
|
||||
#[doc = "`read()` method returns [usr_ofs::R](usr_ofs::R) reader structure"]
|
||||
impl crate::Readable for USR_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [usr_ofs::W](usr_ofs::W) writer structure"]
|
||||
impl crate::Writable for USR_OFS {}
|
||||
#[doc = "USER Offset Correction Register"]
|
||||
pub mod usr_ofs;
|
||||
#[doc = "ADC X Offset Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xofs](xofs) module"]
|
||||
pub type XOFS = crate::Reg<u32, _XOFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _XOFS;
|
||||
#[doc = "`read()` method returns [xofs::R](xofs::R) reader structure"]
|
||||
impl crate::Readable for XOFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [xofs::W](xofs::W) writer structure"]
|
||||
impl crate::Writable for XOFS {}
|
||||
#[doc = "ADC X Offset Correction Register"]
|
||||
pub mod xofs;
|
||||
#[doc = "ADC Y Offset Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [yofs](yofs) module"]
|
||||
pub type YOFS = crate::Reg<u32, _YOFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _YOFS;
|
||||
#[doc = "`read()` method returns [yofs::R](yofs::R) reader structure"]
|
||||
impl crate::Readable for YOFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [yofs::W](yofs::W) writer structure"]
|
||||
impl crate::Writable for YOFS {}
|
||||
#[doc = "ADC Y Offset Correction Register"]
|
||||
pub mod yofs;
|
||||
#[doc = "ADC Gain Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [g](g) module"]
|
||||
pub type G = crate::Reg<u32, _G>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _G;
|
||||
#[doc = "`read()` method returns [g::R](g::R) reader structure"]
|
||||
impl crate::Readable for G {}
|
||||
#[doc = "`write(|w| ..)` method takes [g::W](g::W) writer structure"]
|
||||
impl crate::Writable for G {}
|
||||
#[doc = "ADC Gain Register"]
|
||||
pub mod g;
|
||||
#[doc = "ADC User Gain Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ug](ug) module"]
|
||||
pub type UG = crate::Reg<u32, _UG>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _UG;
|
||||
#[doc = "`read()` method returns [ug::R](ug::R) reader structure"]
|
||||
impl crate::Readable for UG {}
|
||||
#[doc = "`write(|w| ..)` method takes [ug::W](ug::W) writer structure"]
|
||||
impl crate::Writable for UG {}
|
||||
#[doc = "ADC User Gain Register"]
|
||||
pub mod ug;
|
||||
#[doc = "ADC General Calibration Value Register S\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clps](clps) module"]
|
||||
pub type CLPS = crate::Reg<u32, _CLPS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLPS;
|
||||
#[doc = "`read()` method returns [clps::R](clps::R) reader structure"]
|
||||
impl crate::Readable for CLPS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clps::W](clps::W) writer structure"]
|
||||
impl crate::Writable for CLPS {}
|
||||
#[doc = "ADC General Calibration Value Register S"]
|
||||
pub mod clps;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp3](clp3) module"]
|
||||
pub type CLP3 = crate::Reg<u32, _CLP3>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP3;
|
||||
#[doc = "`read()` method returns [clp3::R](clp3::R) reader structure"]
|
||||
impl crate::Readable for CLP3 {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp3::W](clp3::W) writer structure"]
|
||||
impl crate::Writable for CLP3 {}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
|
||||
pub mod clp3;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp2](clp2) module"]
|
||||
pub type CLP2 = crate::Reg<u32, _CLP2>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP2;
|
||||
#[doc = "`read()` method returns [clp2::R](clp2::R) reader structure"]
|
||||
impl crate::Readable for CLP2 {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp2::W](clp2::W) writer structure"]
|
||||
impl crate::Writable for CLP2 {}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
|
||||
pub mod clp2;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp1](clp1) module"]
|
||||
pub type CLP1 = crate::Reg<u32, _CLP1>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP1;
|
||||
#[doc = "`read()` method returns [clp1::R](clp1::R) reader structure"]
|
||||
impl crate::Readable for CLP1 {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp1::W](clp1::W) writer structure"]
|
||||
impl crate::Writable for CLP1 {}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
|
||||
pub mod clp1;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp0](clp0) module"]
|
||||
pub type CLP0 = crate::Reg<u32, _CLP0>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP0;
|
||||
#[doc = "`read()` method returns [clp0::R](clp0::R) reader structure"]
|
||||
impl crate::Readable for CLP0 {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp0::W](clp0::W) writer structure"]
|
||||
impl crate::Writable for CLP0 {}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
|
||||
pub mod clp0;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register X\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clpx](clpx) module"]
|
||||
pub type CLPX = crate::Reg<u32, _CLPX>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLPX;
|
||||
#[doc = "`read()` method returns [clpx::R](clpx::R) reader structure"]
|
||||
impl crate::Readable for CLPX {}
|
||||
#[doc = "`write(|w| ..)` method takes [clpx::W](clpx::W) writer structure"]
|
||||
impl crate::Writable for CLPX {}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register X"]
|
||||
pub mod clpx;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 9\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp9](clp9) module"]
|
||||
pub type CLP9 = crate::Reg<u32, _CLP9>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP9;
|
||||
#[doc = "`read()` method returns [clp9::R](clp9::R) reader structure"]
|
||||
impl crate::Readable for CLP9 {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp9::W](clp9::W) writer structure"]
|
||||
impl crate::Writable for CLP9 {}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
|
||||
pub mod clp9;
|
||||
#[doc = "ADC General Calibration Offset Value Register S\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clps_ofs](clps_ofs) module"]
|
||||
pub type CLPS_OFS = crate::Reg<u32, _CLPS_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLPS_OFS;
|
||||
#[doc = "`read()` method returns [clps_ofs::R](clps_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLPS_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clps_ofs::W](clps_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLPS_OFS {}
|
||||
#[doc = "ADC General Calibration Offset Value Register S"]
|
||||
pub mod clps_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp3_ofs](clp3_ofs) module"]
|
||||
pub type CLP3_OFS = crate::Reg<u32, _CLP3_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP3_OFS;
|
||||
#[doc = "`read()` method returns [clp3_ofs::R](clp3_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLP3_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp3_ofs::W](clp3_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLP3_OFS {}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub mod clp3_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp2_ofs](clp2_ofs) module"]
|
||||
pub type CLP2_OFS = crate::Reg<u32, _CLP2_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP2_OFS;
|
||||
#[doc = "`read()` method returns [clp2_ofs::R](clp2_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLP2_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp2_ofs::W](clp2_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLP2_OFS {}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub mod clp2_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp1_ofs](clp1_ofs) module"]
|
||||
pub type CLP1_OFS = crate::Reg<u32, _CLP1_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP1_OFS;
|
||||
#[doc = "`read()` method returns [clp1_ofs::R](clp1_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLP1_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp1_ofs::W](clp1_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLP1_OFS {}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub mod clp1_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp0_ofs](clp0_ofs) module"]
|
||||
pub type CLP0_OFS = crate::Reg<u32, _CLP0_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP0_OFS;
|
||||
#[doc = "`read()` method returns [clp0_ofs::R](clp0_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLP0_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp0_ofs::W](clp0_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLP0_OFS {}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub mod clp0_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clpx_ofs](clpx_ofs) module"]
|
||||
pub type CLPX_OFS = crate::Reg<u32, _CLPX_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLPX_OFS;
|
||||
#[doc = "`read()` method returns [clpx_ofs::R](clpx_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLPX_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clpx_ofs::W](clpx_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLPX_OFS {}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub mod clpx_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9\n\nThis register you can [`read`](crate::generic::Reg::read), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clp9_ofs](clp9_ofs) module"]
|
||||
pub type CLP9_OFS = crate::Reg<u32, _CLP9_OFS>;
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
pub struct _CLP9_OFS;
|
||||
#[doc = "`read()` method returns [clp9_ofs::R](clp9_ofs::R) reader structure"]
|
||||
impl crate::Readable for CLP9_OFS {}
|
||||
#[doc = "`write(|w| ..)` method takes [clp9_ofs::W](clp9_ofs::W) writer structure"]
|
||||
impl crate::Writable for CLP9_OFS {}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub mod clp9_ofs;
|
||||
|
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::BASE_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct BA_OFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl BA_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _BA_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _BA_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn ba_ofs(&self) -> BA_OFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
BA_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 64 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn ba_ofs(&mut self) -> _BA_OFSW {
|
||||
_BA_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register BASE_OFS"]
|
||||
pub type R = crate::R<u32, super::BASE_OFS>;
|
||||
#[doc = "Writer for register BASE_OFS"]
|
||||
pub type W = crate::W<u32, super::BASE_OFS>;
|
||||
#[doc = "Register BASE_OFS `reset()`'s with value 0x40"]
|
||||
impl crate::ResetValue for super::BASE_OFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x40
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `BA_OFS`"]
|
||||
pub type BA_OFS_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `BA_OFS`"]
|
||||
pub struct BA_OFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> BA_OFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline(always)]
|
||||
pub fn ba_ofs(&self) -> BA_OFS_R {
|
||||
BA_OFS_R::new((self.bits & 0xff) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline(always)]
|
||||
pub fn ba_ofs(&mut self) -> BA_OFS_W {
|
||||
BA_OFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
820
src/adc0/cfg1.rs
820
src/adc0/cfg1.rs
@ -1,482 +1,338 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CFG1 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `ADICLK`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADICLKR {
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
_00,
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
_01,
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
_10,
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
_11,
|
||||
}
|
||||
impl ADICLKR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADICLKR::_00 => 0,
|
||||
ADICLKR::_01 => 1,
|
||||
ADICLKR::_10 => 2,
|
||||
ADICLKR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> ADICLKR {
|
||||
match value {
|
||||
0 => ADICLKR::_00,
|
||||
1 => ADICLKR::_01,
|
||||
2 => ADICLKR::_10,
|
||||
3 => ADICLKR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == ADICLKR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == ADICLKR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == ADICLKR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == ADICLKR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `MODE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum MODER {
|
||||
#[doc = "8-bit conversion."]
|
||||
_00,
|
||||
#[doc = "12-bit conversion."]
|
||||
_01,
|
||||
#[doc = "10-bit conversion."]
|
||||
_10,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
}
|
||||
impl MODER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
MODER::_00 => 0,
|
||||
MODER::_01 => 1,
|
||||
MODER::_10 => 2,
|
||||
MODER::_Reserved(bits) => bits,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> MODER {
|
||||
match value {
|
||||
0 => MODER::_00,
|
||||
1 => MODER::_01,
|
||||
2 => MODER::_10,
|
||||
i => MODER::_Reserved(i),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == MODER::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == MODER::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == MODER::_10
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `ADIV`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADIVR {
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
_00,
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
_01,
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
_10,
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
_11,
|
||||
}
|
||||
impl ADIVR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADIVR::_00 => 0,
|
||||
ADIVR::_01 => 1,
|
||||
ADIVR::_10 => 2,
|
||||
ADIVR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> ADIVR {
|
||||
match value {
|
||||
0 => ADIVR::_00,
|
||||
1 => ADIVR::_01,
|
||||
2 => ADIVR::_10,
|
||||
3 => ADIVR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == ADIVR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == ADIVR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == ADIVR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == ADIVR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADICLK`"]
|
||||
pub enum ADICLKW {
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
_00,
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
_01,
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
_10,
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
_11,
|
||||
}
|
||||
impl ADICLKW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADICLKW::_00 => 0,
|
||||
ADICLKW::_01 => 1,
|
||||
ADICLKW::_10 => 2,
|
||||
ADICLKW::_11 => 3,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _ADICLKW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _ADICLKW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: ADICLKW) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_00)
|
||||
}
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_01)
|
||||
}
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_10)
|
||||
}
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
#[inline]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_11)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `MODE`"]
|
||||
pub enum MODEW {
|
||||
#[doc = "8-bit conversion."]
|
||||
_00,
|
||||
#[doc = "12-bit conversion."]
|
||||
_01,
|
||||
#[doc = "10-bit conversion."]
|
||||
_10,
|
||||
}
|
||||
impl MODEW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
MODEW::_00 => 0,
|
||||
MODEW::_01 => 1,
|
||||
MODEW::_10 => 2,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _MODEW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _MODEW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: MODEW) -> &'a mut W {
|
||||
unsafe { self.bits(variant._bits()) }
|
||||
}
|
||||
#[doc = "8-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(MODEW::_00)
|
||||
}
|
||||
#[doc = "12-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(MODEW::_01)
|
||||
}
|
||||
#[doc = "10-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(MODEW::_10)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 2;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADIV`"]
|
||||
pub enum ADIVW {
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
_00,
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
_01,
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
_10,
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
_11,
|
||||
}
|
||||
impl ADIVW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADIVW::_00 => 0,
|
||||
ADIVW::_01 => 1,
|
||||
ADIVW::_10 => 2,
|
||||
ADIVW::_11 => 3,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _ADIVW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _ADIVW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: ADIVW) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_00)
|
||||
}
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_01)
|
||||
}
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_10)
|
||||
}
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
#[inline]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_11)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 5;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLRLTRGW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLRLTRGW<'a> {
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 8;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:1 - Input Clock Select"]
|
||||
#[inline]
|
||||
pub fn adiclk(&self) -> ADICLKR {
|
||||
ADICLKR::_from({
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
#[doc = "Bits 2:3 - Conversion mode selection"]
|
||||
#[inline]
|
||||
pub fn mode(&self) -> MODER {
|
||||
MODER::_from({
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 2;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
#[doc = "Bits 5:6 - Clock Divide Select"]
|
||||
#[inline]
|
||||
pub fn adiv(&self) -> ADIVR {
|
||||
ADIVR::_from({
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 5;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:1 - Input Clock Select"]
|
||||
#[inline]
|
||||
pub fn adiclk(&mut self) -> _ADICLKW {
|
||||
_ADICLKW { w: self }
|
||||
}
|
||||
#[doc = "Bits 2:3 - Conversion mode selection"]
|
||||
#[inline]
|
||||
pub fn mode(&mut self) -> _MODEW {
|
||||
_MODEW { w: self }
|
||||
}
|
||||
#[doc = "Bits 5:6 - Clock Divide Select"]
|
||||
#[inline]
|
||||
pub fn adiv(&mut self) -> _ADIVW {
|
||||
_ADIVW { w: self }
|
||||
}
|
||||
#[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
|
||||
#[inline]
|
||||
pub fn clrltrg(&mut self) -> _CLRLTRGW {
|
||||
_CLRLTRGW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CFG1"]
|
||||
pub type R = crate::R<u32, super::CFG1>;
|
||||
#[doc = "Writer for register CFG1"]
|
||||
pub type W = crate::W<u32, super::CFG1>;
|
||||
#[doc = "Register CFG1 `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::CFG1 {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Input Clock Select\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
#[repr(u8)]
|
||||
pub enum ADICLK_A {
|
||||
#[doc = "0: Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
_00 = 0,
|
||||
#[doc = "1: Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
_01 = 1,
|
||||
#[doc = "2: Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
_10 = 2,
|
||||
#[doc = "3: Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
_11 = 3,
|
||||
}
|
||||
impl From<ADICLK_A> for u8 {
|
||||
#[inline(always)]
|
||||
fn from(variant: ADICLK_A) -> Self {
|
||||
variant as _
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `ADICLK`"]
|
||||
pub type ADICLK_R = crate::R<u8, ADICLK_A>;
|
||||
impl ADICLK_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> ADICLK_A {
|
||||
match self.bits {
|
||||
0 => ADICLK_A::_00,
|
||||
1 => ADICLK_A::_01,
|
||||
2 => ADICLK_A::_10,
|
||||
3 => ADICLK_A::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline(always)]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == ADICLK_A::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline(always)]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == ADICLK_A::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline(always)]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == ADICLK_A::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline(always)]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == ADICLK_A::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `ADICLK`"]
|
||||
pub struct ADICLK_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> ADICLK_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: ADICLK_A) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
#[inline(always)]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(ADICLK_A::_00)
|
||||
}
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
#[inline(always)]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(ADICLK_A::_01)
|
||||
}
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
#[inline(always)]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(ADICLK_A::_10)
|
||||
}
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
#[inline(always)]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(ADICLK_A::_11)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Conversion mode selection\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
#[repr(u8)]
|
||||
pub enum MODE_A {
|
||||
#[doc = "0: 8-bit conversion."]
|
||||
_00 = 0,
|
||||
#[doc = "1: 12-bit conversion."]
|
||||
_01 = 1,
|
||||
#[doc = "2: 10-bit conversion."]
|
||||
_10 = 2,
|
||||
}
|
||||
impl From<MODE_A> for u8 {
|
||||
#[inline(always)]
|
||||
fn from(variant: MODE_A) -> Self {
|
||||
variant as _
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `MODE`"]
|
||||
pub type MODE_R = crate::R<u8, MODE_A>;
|
||||
impl MODE_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> crate::Variant<u8, MODE_A> {
|
||||
use crate::Variant::*;
|
||||
match self.bits {
|
||||
0 => Val(MODE_A::_00),
|
||||
1 => Val(MODE_A::_01),
|
||||
2 => Val(MODE_A::_10),
|
||||
i => Res(i),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline(always)]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == MODE_A::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline(always)]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == MODE_A::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline(always)]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == MODE_A::_10
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `MODE`"]
|
||||
pub struct MODE_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> MODE_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: MODE_A) -> &'a mut W {
|
||||
unsafe { self.bits(variant.into()) }
|
||||
}
|
||||
#[doc = "8-bit conversion."]
|
||||
#[inline(always)]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(MODE_A::_00)
|
||||
}
|
||||
#[doc = "12-bit conversion."]
|
||||
#[inline(always)]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(MODE_A::_01)
|
||||
}
|
||||
#[doc = "10-bit conversion."]
|
||||
#[inline(always)]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(MODE_A::_10)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Clock Divide Select\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
#[repr(u8)]
|
||||
pub enum ADIV_A {
|
||||
#[doc = "0: The divide ratio is 1 and the clock rate is input clock."]
|
||||
_00 = 0,
|
||||
#[doc = "1: The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
_01 = 1,
|
||||
#[doc = "2: The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
_10 = 2,
|
||||
#[doc = "3: The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
_11 = 3,
|
||||
}
|
||||
impl From<ADIV_A> for u8 {
|
||||
#[inline(always)]
|
||||
fn from(variant: ADIV_A) -> Self {
|
||||
variant as _
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `ADIV`"]
|
||||
pub type ADIV_R = crate::R<u8, ADIV_A>;
|
||||
impl ADIV_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> ADIV_A {
|
||||
match self.bits {
|
||||
0 => ADIV_A::_00,
|
||||
1 => ADIV_A::_01,
|
||||
2 => ADIV_A::_10,
|
||||
3 => ADIV_A::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline(always)]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == ADIV_A::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline(always)]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == ADIV_A::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline(always)]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == ADIV_A::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline(always)]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == ADIV_A::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `ADIV`"]
|
||||
pub struct ADIV_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> ADIV_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: ADIV_A) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
#[inline(always)]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(ADIV_A::_00)
|
||||
}
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
#[inline(always)]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(ADIV_A::_01)
|
||||
}
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
#[inline(always)]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(ADIV_A::_10)
|
||||
}
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
#[inline(always)]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(ADIV_A::_11)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x03 << 5)) | (((value as u32) & 0x03) << 5);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `CLRLTRG`"]
|
||||
pub struct CLRLTRG_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLRLTRG_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Input Clock Select"]
|
||||
#[inline(always)]
|
||||
pub fn adiclk(&self) -> ADICLK_R {
|
||||
ADICLK_R::new((self.bits & 0x03) as u8)
|
||||
}
|
||||
#[doc = "Bits 2:3 - Conversion mode selection"]
|
||||
#[inline(always)]
|
||||
pub fn mode(&self) -> MODE_R {
|
||||
MODE_R::new(((self.bits >> 2) & 0x03) as u8)
|
||||
}
|
||||
#[doc = "Bits 5:6 - Clock Divide Select"]
|
||||
#[inline(always)]
|
||||
pub fn adiv(&self) -> ADIV_R {
|
||||
ADIV_R::new(((self.bits >> 5) & 0x03) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Input Clock Select"]
|
||||
#[inline(always)]
|
||||
pub fn adiclk(&mut self) -> ADICLK_W {
|
||||
ADICLK_W { w: self }
|
||||
}
|
||||
#[doc = "Bits 2:3 - Conversion mode selection"]
|
||||
#[inline(always)]
|
||||
pub fn mode(&mut self) -> MODE_W {
|
||||
MODE_W { w: self }
|
||||
}
|
||||
#[doc = "Bits 5:6 - Clock Divide Select"]
|
||||
#[inline(always)]
|
||||
pub fn adiv(&mut self) -> ADIV_W {
|
||||
ADIV_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
|
||||
#[inline(always)]
|
||||
pub fn clrltrg(&mut self) -> CLRLTRG_W {
|
||||
CLRLTRG_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/cfg2.rs
143
src/adc0/cfg2.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CFG2 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct SMPLTSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl SMPLTSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _SMPLTSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _SMPLTSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:7 - Sample Time Select"]
|
||||
#[inline]
|
||||
pub fn smplts(&self) -> SMPLTSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
SMPLTSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 12 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:7 - Sample Time Select"]
|
||||
#[inline]
|
||||
pub fn smplts(&mut self) -> _SMPLTSW {
|
||||
_SMPLTSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CFG2"]
|
||||
pub type R = crate::R<u32, super::CFG2>;
|
||||
#[doc = "Writer for register CFG2"]
|
||||
pub type W = crate::W<u32, super::CFG2>;
|
||||
#[doc = "Register CFG2 `reset()`'s with value 0x0c"]
|
||||
impl crate::ResetValue for super::CFG2 {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x0c
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `SMPLTS`"]
|
||||
pub type SMPLTS_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `SMPLTS`"]
|
||||
pub struct SMPLTS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> SMPLTS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:7 - Sample Time Select"]
|
||||
#[inline(always)]
|
||||
pub fn smplts(&self) -> SMPLTS_R {
|
||||
SMPLTS_R::new((self.bits & 0xff) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:7 - Sample Time Select"]
|
||||
#[inline(always)]
|
||||
pub fn smplts(&mut self) -> SMPLTS_W {
|
||||
SMPLTS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/clp0.rs
143
src/adc0/clp0.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP0 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLP0R {
|
||||
bits: u8,
|
||||
}
|
||||
impl CLP0R {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLP0W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLP0W<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:7 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clp0(&self) -> CLP0R {
|
||||
let bits = {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
CLP0R { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 46 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:7 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clp0(&mut self) -> _CLP0W {
|
||||
_CLP0W { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLP0"]
|
||||
pub type R = crate::R<u32, super::CLP0>;
|
||||
#[doc = "Writer for register CLP0"]
|
||||
pub type W = crate::W<u32, super::CLP0>;
|
||||
#[doc = "Register CLP0 `reset()`'s with value 0x2e"]
|
||||
impl crate::ResetValue for super::CLP0 {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x2e
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLP0`"]
|
||||
pub type CLP0_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `CLP0`"]
|
||||
pub struct CLP0_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLP0_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:7 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clp0(&self) -> CLP0_R {
|
||||
CLP0_R::new((self.bits & 0xff) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:7 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clp0(&mut self) -> CLP0_W {
|
||||
CLP0_W { w: self }
|
||||
}
|
||||
}
|
||||
|
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP0_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLP0_OFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl CLP0_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLP0_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLP0_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:3 - CLP0 Offset"]
|
||||
#[inline]
|
||||
pub fn clp0_ofs(&self) -> CLP0_OFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
CLP0_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:3 - CLP0 Offset"]
|
||||
#[inline]
|
||||
pub fn clp0_ofs(&mut self) -> _CLP0_OFSW {
|
||||
_CLP0_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLP0_OFS"]
|
||||
pub type R = crate::R<u32, super::CLP0_OFS>;
|
||||
#[doc = "Writer for register CLP0_OFS"]
|
||||
pub type W = crate::W<u32, super::CLP0_OFS>;
|
||||
#[doc = "Register CLP0_OFS `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::CLP0_OFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLP0_OFS`"]
|
||||
pub type CLP0_OFS_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `CLP0_OFS`"]
|
||||
pub struct CLP0_OFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLP0_OFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:3 - CLP0 Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clp0_ofs(&self) -> CLP0_OFS_R {
|
||||
CLP0_OFS_R::new((self.bits & 0x0f) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:3 - CLP0 Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clp0_ofs(&mut self) -> CLP0_OFS_W {
|
||||
CLP0_OFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/clp1.rs
143
src/adc0/clp1.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP1 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLP1R {
|
||||
bits: u16,
|
||||
}
|
||||
impl CLP1R {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u16 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLP1W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLP1W<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
const MASK: u16 = 511;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:8 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clp1(&self) -> CLP1R {
|
||||
let bits = {
|
||||
const MASK: u16 = 511;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u16
|
||||
};
|
||||
CLP1R { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 92 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:8 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clp1(&mut self) -> _CLP1W {
|
||||
_CLP1W { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLP1"]
|
||||
pub type R = crate::R<u32, super::CLP1>;
|
||||
#[doc = "Writer for register CLP1"]
|
||||
pub type W = crate::W<u32, super::CLP1>;
|
||||
#[doc = "Register CLP1 `reset()`'s with value 0x5c"]
|
||||
impl crate::ResetValue for super::CLP1 {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x5c
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLP1`"]
|
||||
pub type CLP1_R = crate::R<u16, u16>;
|
||||
#[doc = "Write proxy for field `CLP1`"]
|
||||
pub struct CLP1_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLP1_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x01ff) | ((value as u32) & 0x01ff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:8 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clp1(&self) -> CLP1_R {
|
||||
CLP1_R::new((self.bits & 0x01ff) as u16)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:8 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clp1(&mut self) -> CLP1_W {
|
||||
CLP1_W { w: self }
|
||||
}
|
||||
}
|
||||
|
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP1_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLP1_OFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl CLP1_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLP1_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLP1_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:3 - CLP1 Offset"]
|
||||
#[inline]
|
||||
pub fn clp1_ofs(&self) -> CLP1_OFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
CLP1_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:3 - CLP1 Offset"]
|
||||
#[inline]
|
||||
pub fn clp1_ofs(&mut self) -> _CLP1_OFSW {
|
||||
_CLP1_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLP1_OFS"]
|
||||
pub type R = crate::R<u32, super::CLP1_OFS>;
|
||||
#[doc = "Writer for register CLP1_OFS"]
|
||||
pub type W = crate::W<u32, super::CLP1_OFS>;
|
||||
#[doc = "Register CLP1_OFS `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::CLP1_OFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLP1_OFS`"]
|
||||
pub type CLP1_OFS_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `CLP1_OFS`"]
|
||||
pub struct CLP1_OFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLP1_OFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:3 - CLP1 Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clp1_ofs(&self) -> CLP1_OFS_R {
|
||||
CLP1_OFS_R::new((self.bits & 0x0f) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:3 - CLP1 Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clp1_ofs(&mut self) -> CLP1_OFS_W {
|
||||
CLP1_OFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/clp2.rs
143
src/adc0/clp2.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP2 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLP2R {
|
||||
bits: u16,
|
||||
}
|
||||
impl CLP2R {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u16 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLP2W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLP2W<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
const MASK: u16 = 1023;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:9 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clp2(&self) -> CLP2R {
|
||||
let bits = {
|
||||
const MASK: u16 = 1023;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u16
|
||||
};
|
||||
CLP2R { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 184 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:9 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clp2(&mut self) -> _CLP2W {
|
||||
_CLP2W { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLP2"]
|
||||
pub type R = crate::R<u32, super::CLP2>;
|
||||
#[doc = "Writer for register CLP2"]
|
||||
pub type W = crate::W<u32, super::CLP2>;
|
||||
#[doc = "Register CLP2 `reset()`'s with value 0xb8"]
|
||||
impl crate::ResetValue for super::CLP2 {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0xb8
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLP2`"]
|
||||
pub type CLP2_R = crate::R<u16, u16>;
|
||||
#[doc = "Write proxy for field `CLP2`"]
|
||||
pub struct CLP2_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLP2_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:9 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clp2(&self) -> CLP2_R {
|
||||
CLP2_R::new((self.bits & 0x03ff) as u16)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:9 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clp2(&mut self) -> CLP2_W {
|
||||
CLP2_W { w: self }
|
||||
}
|
||||
}
|
||||
|
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP2_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLP2_OFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl CLP2_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLP2_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLP2_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:3 - CLP2 Offset"]
|
||||
#[inline]
|
||||
pub fn clp2_ofs(&self) -> CLP2_OFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
CLP2_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:3 - CLP2 Offset"]
|
||||
#[inline]
|
||||
pub fn clp2_ofs(&mut self) -> _CLP2_OFSW {
|
||||
_CLP2_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLP2_OFS"]
|
||||
pub type R = crate::R<u32, super::CLP2_OFS>;
|
||||
#[doc = "Writer for register CLP2_OFS"]
|
||||
pub type W = crate::W<u32, super::CLP2_OFS>;
|
||||
#[doc = "Register CLP2_OFS `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::CLP2_OFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLP2_OFS`"]
|
||||
pub type CLP2_OFS_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `CLP2_OFS`"]
|
||||
pub struct CLP2_OFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLP2_OFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:3 - CLP2 Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clp2_ofs(&self) -> CLP2_OFS_R {
|
||||
CLP2_OFS_R::new((self.bits & 0x0f) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:3 - CLP2 Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clp2_ofs(&mut self) -> CLP2_OFS_W {
|
||||
CLP2_OFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/clp3.rs
143
src/adc0/clp3.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP3 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLP3R {
|
||||
bits: u16,
|
||||
}
|
||||
impl CLP3R {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u16 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLP3W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLP3W<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
const MASK: u16 = 1023;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:9 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clp3(&self) -> CLP3R {
|
||||
let bits = {
|
||||
const MASK: u16 = 1023;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u16
|
||||
};
|
||||
CLP3R { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 384 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:9 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clp3(&mut self) -> _CLP3W {
|
||||
_CLP3W { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLP3"]
|
||||
pub type R = crate::R<u32, super::CLP3>;
|
||||
#[doc = "Writer for register CLP3"]
|
||||
pub type W = crate::W<u32, super::CLP3>;
|
||||
#[doc = "Register CLP3 `reset()`'s with value 0x0180"]
|
||||
impl crate::ResetValue for super::CLP3 {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x0180
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLP3`"]
|
||||
pub type CLP3_R = crate::R<u16, u16>;
|
||||
#[doc = "Write proxy for field `CLP3`"]
|
||||
pub struct CLP3_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLP3_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:9 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clp3(&self) -> CLP3_R {
|
||||
CLP3_R::new((self.bits & 0x03ff) as u16)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:9 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clp3(&mut self) -> CLP3_W {
|
||||
CLP3_W { w: self }
|
||||
}
|
||||
}
|
||||
|
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP3_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLP3_OFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl CLP3_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLP3_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLP3_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:3 - CLP3 Offset"]
|
||||
#[inline]
|
||||
pub fn clp3_ofs(&self) -> CLP3_OFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
CLP3_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:3 - CLP3 Offset"]
|
||||
#[inline]
|
||||
pub fn clp3_ofs(&mut self) -> _CLP3_OFSW {
|
||||
_CLP3_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLP3_OFS"]
|
||||
pub type R = crate::R<u32, super::CLP3_OFS>;
|
||||
#[doc = "Writer for register CLP3_OFS"]
|
||||
pub type W = crate::W<u32, super::CLP3_OFS>;
|
||||
#[doc = "Register CLP3_OFS `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::CLP3_OFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLP3_OFS`"]
|
||||
pub type CLP3_OFS_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `CLP3_OFS`"]
|
||||
pub struct CLP3_OFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLP3_OFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:3 - CLP3 Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clp3_ofs(&self) -> CLP3_OFS_R {
|
||||
CLP3_OFS_R::new((self.bits & 0x0f) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:3 - CLP3 Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clp3_ofs(&mut self) -> CLP3_OFS_W {
|
||||
CLP3_OFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/clp9.rs
143
src/adc0/clp9.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP9 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLP9R {
|
||||
bits: u8,
|
||||
}
|
||||
impl CLP9R {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLP9W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLP9W<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 127;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:6 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clp9(&self) -> CLP9R {
|
||||
let bits = {
|
||||
const MASK: u8 = 127;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
CLP9R { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:6 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clp9(&mut self) -> _CLP9W {
|
||||
_CLP9W { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLP9"]
|
||||
pub type R = crate::R<u32, super::CLP9>;
|
||||
#[doc = "Writer for register CLP9"]
|
||||
pub type W = crate::W<u32, super::CLP9>;
|
||||
#[doc = "Register CLP9 `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::CLP9 {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLP9`"]
|
||||
pub type CLP9_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `CLP9`"]
|
||||
pub struct CLP9_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLP9_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:6 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clp9(&self) -> CLP9_R {
|
||||
CLP9_R::new((self.bits & 0x7f) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:6 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clp9(&mut self) -> CLP9_W {
|
||||
CLP9_W { w: self }
|
||||
}
|
||||
}
|
||||
|
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP9_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLP9_OFSR {
|
||||
bits: u16,
|
||||
}
|
||||
impl CLP9_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u16 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLP9_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLP9_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
const MASK: u16 = 4095;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:11 - CLP9 Offset"]
|
||||
#[inline]
|
||||
pub fn clp9_ofs(&self) -> CLP9_OFSR {
|
||||
let bits = {
|
||||
const MASK: u16 = 4095;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u16
|
||||
};
|
||||
CLP9_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 576 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:11 - CLP9 Offset"]
|
||||
#[inline]
|
||||
pub fn clp9_ofs(&mut self) -> _CLP9_OFSW {
|
||||
_CLP9_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLP9_OFS"]
|
||||
pub type R = crate::R<u32, super::CLP9_OFS>;
|
||||
#[doc = "Writer for register CLP9_OFS"]
|
||||
pub type W = crate::W<u32, super::CLP9_OFS>;
|
||||
#[doc = "Register CLP9_OFS `reset()`'s with value 0x0240"]
|
||||
impl crate::ResetValue for super::CLP9_OFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x0240
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLP9_OFS`"]
|
||||
pub type CLP9_OFS_R = crate::R<u16, u16>;
|
||||
#[doc = "Write proxy for field `CLP9_OFS`"]
|
||||
pub struct CLP9_OFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLP9_OFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:11 - CLP9 Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clp9_ofs(&self) -> CLP9_OFS_R {
|
||||
CLP9_OFS_R::new((self.bits & 0x0fff) as u16)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:11 - CLP9 Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clp9_ofs(&mut self) -> CLP9_OFS_W {
|
||||
CLP9_OFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/clps.rs
143
src/adc0/clps.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLPS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLPSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl CLPSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLPSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLPSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 127;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:6 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clps(&self) -> CLPSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 127;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
CLPSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 46 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:6 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clps(&mut self) -> _CLPSW {
|
||||
_CLPSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLPS"]
|
||||
pub type R = crate::R<u32, super::CLPS>;
|
||||
#[doc = "Writer for register CLPS"]
|
||||
pub type W = crate::W<u32, super::CLPS>;
|
||||
#[doc = "Register CLPS `reset()`'s with value 0x2e"]
|
||||
impl crate::ResetValue for super::CLPS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x2e
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLPS`"]
|
||||
pub type CLPS_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `CLPS`"]
|
||||
pub struct CLPS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLPS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:6 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clps(&self) -> CLPS_R {
|
||||
CLPS_R::new((self.bits & 0x7f) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:6 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clps(&mut self) -> CLPS_W {
|
||||
CLPS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLPS_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLPS_OFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl CLPS_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLPS_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLPS_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:3 - CLPS Offset"]
|
||||
#[inline]
|
||||
pub fn clps_ofs(&self) -> CLPS_OFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
CLPS_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:3 - CLPS Offset"]
|
||||
#[inline]
|
||||
pub fn clps_ofs(&mut self) -> _CLPS_OFSW {
|
||||
_CLPS_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLPS_OFS"]
|
||||
pub type R = crate::R<u32, super::CLPS_OFS>;
|
||||
#[doc = "Writer for register CLPS_OFS"]
|
||||
pub type W = crate::W<u32, super::CLPS_OFS>;
|
||||
#[doc = "Register CLPS_OFS `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::CLPS_OFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLPS_OFS`"]
|
||||
pub type CLPS_OFS_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `CLPS_OFS`"]
|
||||
pub struct CLPS_OFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLPS_OFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:3 - CLPS Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clps_ofs(&self) -> CLPS_OFS_R {
|
||||
CLPS_OFS_R::new((self.bits & 0x0f) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:3 - CLPS Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clps_ofs(&mut self) -> CLPS_OFS_W {
|
||||
CLPS_OFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/clpx.rs
143
src/adc0/clpx.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLPX {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLPXR {
|
||||
bits: u8,
|
||||
}
|
||||
impl CLPXR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLPXW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLPXW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 127;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:6 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clpx(&self) -> CLPXR {
|
||||
let bits = {
|
||||
const MASK: u8 = 127;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
CLPXR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:6 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clpx(&mut self) -> _CLPXW {
|
||||
_CLPXW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLPX"]
|
||||
pub type R = crate::R<u32, super::CLPX>;
|
||||
#[doc = "Writer for register CLPX"]
|
||||
pub type W = crate::W<u32, super::CLPX>;
|
||||
#[doc = "Register CLPX `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::CLPX {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLPX`"]
|
||||
pub type CLPX_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `CLPX`"]
|
||||
pub struct CLPX_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLPX_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:6 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clpx(&self) -> CLPX_R {
|
||||
CLPX_R::new((self.bits & 0x7f) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:6 - Calibration Value"]
|
||||
#[inline(always)]
|
||||
pub fn clpx(&mut self) -> CLPX_W {
|
||||
CLPX_W { w: self }
|
||||
}
|
||||
}
|
||||
|
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLPX_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLPX_OFSR {
|
||||
bits: u16,
|
||||
}
|
||||
impl CLPX_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u16 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLPX_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLPX_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
const MASK: u16 = 4095;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:11 - CLPX Offset"]
|
||||
#[inline]
|
||||
pub fn clpx_ofs(&self) -> CLPX_OFSR {
|
||||
let bits = {
|
||||
const MASK: u16 = 4095;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u16
|
||||
};
|
||||
CLPX_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 1088 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:11 - CLPX Offset"]
|
||||
#[inline]
|
||||
pub fn clpx_ofs(&mut self) -> _CLPX_OFSW {
|
||||
_CLPX_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CLPX_OFS"]
|
||||
pub type R = crate::R<u32, super::CLPX_OFS>;
|
||||
#[doc = "Writer for register CLPX_OFS"]
|
||||
pub type W = crate::W<u32, super::CLPX_OFS>;
|
||||
#[doc = "Register CLPX_OFS `reset()`'s with value 0x0440"]
|
||||
impl crate::ResetValue for super::CLPX_OFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x0440
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CLPX_OFS`"]
|
||||
pub type CLPX_OFS_R = crate::R<u16, u16>;
|
||||
#[doc = "Write proxy for field `CLPX_OFS`"]
|
||||
pub struct CLPX_OFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLPX_OFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x0fff) | ((value as u32) & 0x0fff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:11 - CLPX Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clpx_ofs(&self) -> CLPX_OFS_R {
|
||||
CLPX_OFS_R::new((self.bits & 0x0fff) as u16)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:11 - CLPX Offset"]
|
||||
#[inline(always)]
|
||||
pub fn clpx_ofs(&mut self) -> CLPX_OFS_W {
|
||||
CLPX_OFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/cv.rs
143
src/adc0/cv.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CV {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CVR {
|
||||
bits: u16,
|
||||
}
|
||||
impl CVR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u16 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CVW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CVW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
const MASK: u16 = 65535;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:15 - Compare Value."]
|
||||
#[inline]
|
||||
pub fn cv(&self) -> CVR {
|
||||
let bits = {
|
||||
const MASK: u16 = 65535;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u16
|
||||
};
|
||||
CVR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:15 - Compare Value."]
|
||||
#[inline]
|
||||
pub fn cv(&mut self) -> _CVW {
|
||||
_CVW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register CV%s"]
|
||||
pub type R = crate::R<u32, super::CV>;
|
||||
#[doc = "Writer for register CV%s"]
|
||||
pub type W = crate::W<u32, super::CV>;
|
||||
#[doc = "Register CV%s `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::CV {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CV`"]
|
||||
pub type CV_R = crate::R<u16, u16>;
|
||||
#[doc = "Write proxy for field `CV`"]
|
||||
pub struct CV_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CV_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:15 - Compare Value."]
|
||||
#[inline(always)]
|
||||
pub fn cv(&self) -> CV_R {
|
||||
CV_R::new((self.bits & 0xffff) as u16)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:15 - Compare Value."]
|
||||
#[inline(always)]
|
||||
pub fn cv(&mut self) -> CV_W {
|
||||
CV_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/g.rs
143
src/adc0/g.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::G {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct GR {
|
||||
bits: u16,
|
||||
}
|
||||
impl GR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u16 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _GW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _GW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
const MASK: u16 = 2047;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
|
||||
#[inline]
|
||||
pub fn g(&self) -> GR {
|
||||
let bits = {
|
||||
const MASK: u16 = 2047;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u16
|
||||
};
|
||||
GR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 752 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
|
||||
#[inline]
|
||||
pub fn g(&mut self) -> _GW {
|
||||
_GW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register G"]
|
||||
pub type R = crate::R<u32, super::G>;
|
||||
#[doc = "Writer for register G"]
|
||||
pub type W = crate::W<u32, super::G>;
|
||||
#[doc = "Register G `reset()`'s with value 0x02f0"]
|
||||
impl crate::ResetValue for super::G {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x02f0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `G`"]
|
||||
pub type G_R = crate::R<u16, u16>;
|
||||
#[doc = "Write proxy for field `G`"]
|
||||
pub struct G_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> G_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x07ff) | ((value as u32) & 0x07ff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
|
||||
#[inline(always)]
|
||||
pub fn g(&self) -> G_R {
|
||||
G_R::new((self.bits & 0x07ff) as u16)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:10 - Gain error adjustment factor for the overall conversion"]
|
||||
#[inline(always)]
|
||||
pub fn g(&mut self) -> G_W {
|
||||
G_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/ofs.rs
143
src/adc0/ofs.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct OFSR {
|
||||
bits: u16,
|
||||
}
|
||||
impl OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u16 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
const MASK: u16 = 65535;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:15 - Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn ofs(&self) -> OFSR {
|
||||
let bits = {
|
||||
const MASK: u16 = 65535;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u16
|
||||
};
|
||||
OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:15 - Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn ofs(&mut self) -> _OFSW {
|
||||
_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register OFS"]
|
||||
pub type R = crate::R<u32, super::OFS>;
|
||||
#[doc = "Writer for register OFS"]
|
||||
pub type W = crate::W<u32, super::OFS>;
|
||||
#[doc = "Register OFS `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::OFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `OFS`"]
|
||||
pub type OFS_R = crate::R<u16, u16>;
|
||||
#[doc = "Write proxy for field `OFS`"]
|
||||
pub struct OFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> OFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:15 - Offset Error Correction Value"]
|
||||
#[inline(always)]
|
||||
pub fn ofs(&self) -> OFS_R {
|
||||
OFS_R::new((self.bits & 0xffff) as u16)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:15 - Offset Error Correction Value"]
|
||||
#[inline(always)]
|
||||
pub fn ofs(&mut self) -> OFS_W {
|
||||
OFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
@ -1,39 +1,11 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::R {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct DR {
|
||||
bits: u16,
|
||||
}
|
||||
impl DR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u16 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:11 - Data result"]
|
||||
#[inline]
|
||||
pub fn d(&self) -> DR {
|
||||
let bits = {
|
||||
const MASK: u16 = 4095;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u16
|
||||
};
|
||||
DR { bits }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register R%s"]
|
||||
pub type R = crate::R<u32, super::R>;
|
||||
#[doc = "Reader of field `D`"]
|
||||
pub type D_R = crate::R<u16, u16>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:11 - Data result"]
|
||||
#[inline(always)]
|
||||
pub fn d(&self) -> D_R {
|
||||
D_R::new((self.bits & 0x0fff) as u16)
|
||||
}
|
||||
}
|
||||
|
1308
src/adc0/sc1.rs
1308
src/adc0/sc1.rs
File diff suppressed because it is too large
Load Diff
1052
src/adc0/sc2.rs
1052
src/adc0/sc2.rs
File diff suppressed because it is too large
Load Diff
818
src/adc0/sc3.rs
818
src/adc0/sc3.rs
@ -1,495 +1,323 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::SC3 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `AVGS`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum AVGSR {
|
||||
#[doc = "4 samples averaged."]
|
||||
_00,
|
||||
#[doc = "8 samples averaged."]
|
||||
_01,
|
||||
#[doc = "16 samples averaged."]
|
||||
_10,
|
||||
#[doc = "32 samples averaged."]
|
||||
_11,
|
||||
}
|
||||
impl AVGSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
AVGSR::_00 => 0,
|
||||
AVGSR::_01 => 1,
|
||||
AVGSR::_10 => 2,
|
||||
AVGSR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> AVGSR {
|
||||
match value {
|
||||
0 => AVGSR::_00,
|
||||
1 => AVGSR::_01,
|
||||
2 => AVGSR::_10,
|
||||
3 => AVGSR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == AVGSR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == AVGSR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == AVGSR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == AVGSR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `AVGE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum AVGER {
|
||||
#[doc = "Hardware average function disabled."]
|
||||
_0,
|
||||
#[doc = "Hardware average function enabled."]
|
||||
_1,
|
||||
}
|
||||
impl AVGER {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
#[inline]
|
||||
pub fn bit_is_clear(&self) -> bool {
|
||||
!self.bit()
|
||||
}
|
||||
#[doc = r" Returns `true` if the bit is set (1)"]
|
||||
#[inline]
|
||||
pub fn bit_is_set(&self) -> bool {
|
||||
self.bit()
|
||||
}
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bit(&self) -> bool {
|
||||
match *self {
|
||||
AVGER::_0 => false,
|
||||
AVGER::_1 => true,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: bool) -> AVGER {
|
||||
match value {
|
||||
false => AVGER::_0,
|
||||
true => AVGER::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == AVGER::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == AVGER::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `ADCO`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADCOR {
|
||||
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
|
||||
_0,
|
||||
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
|
||||
_1,
|
||||
}
|
||||
impl ADCOR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
#[inline]
|
||||
pub fn bit_is_clear(&self) -> bool {
|
||||
!self.bit()
|
||||
}
|
||||
#[doc = r" Returns `true` if the bit is set (1)"]
|
||||
#[inline]
|
||||
pub fn bit_is_set(&self) -> bool {
|
||||
self.bit()
|
||||
}
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bit(&self) -> bool {
|
||||
match *self {
|
||||
ADCOR::_0 => false,
|
||||
ADCOR::_1 => true,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: bool) -> ADCOR {
|
||||
match value {
|
||||
false => ADCOR::_0,
|
||||
true => ADCOR::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == ADCOR::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == ADCOR::_1
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CALR {
|
||||
bits: bool,
|
||||
}
|
||||
impl CALR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bit(&self) -> bool {
|
||||
self.bits
|
||||
}
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
#[inline]
|
||||
pub fn bit_is_clear(&self) -> bool {
|
||||
!self.bit()
|
||||
}
|
||||
#[doc = r" Returns `true` if the bit is set (1)"]
|
||||
#[inline]
|
||||
pub fn bit_is_set(&self) -> bool {
|
||||
self.bit()
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `AVGS`"]
|
||||
pub enum AVGSW {
|
||||
#[doc = "4 samples averaged."]
|
||||
_00,
|
||||
#[doc = "8 samples averaged."]
|
||||
_01,
|
||||
#[doc = "16 samples averaged."]
|
||||
_10,
|
||||
#[doc = "32 samples averaged."]
|
||||
_11,
|
||||
}
|
||||
impl AVGSW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
AVGSW::_00 => 0,
|
||||
AVGSW::_01 => 1,
|
||||
AVGSW::_10 => 2,
|
||||
AVGSW::_11 => 3,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _AVGSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _AVGSW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: AVGSW) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "4 samples averaged."]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(AVGSW::_00)
|
||||
}
|
||||
#[doc = "8 samples averaged."]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(AVGSW::_01)
|
||||
}
|
||||
#[doc = "16 samples averaged."]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(AVGSW::_10)
|
||||
}
|
||||
#[doc = "32 samples averaged."]
|
||||
#[inline]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(AVGSW::_11)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `AVGE`"]
|
||||
pub enum AVGEW {
|
||||
#[doc = "Hardware average function disabled."]
|
||||
_0,
|
||||
#[doc = "Hardware average function enabled."]
|
||||
_1,
|
||||
}
|
||||
impl AVGEW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
AVGEW::_0 => false,
|
||||
AVGEW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _AVGEW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _AVGEW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: AVGEW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Hardware average function disabled."]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(AVGEW::_0)
|
||||
}
|
||||
#[doc = "Hardware average function enabled."]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(AVGEW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 2;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADCO`"]
|
||||
pub enum ADCOW {
|
||||
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
|
||||
_0,
|
||||
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
|
||||
_1,
|
||||
}
|
||||
impl ADCOW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
ADCOW::_0 => false,
|
||||
ADCOW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _ADCOW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _ADCOW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: ADCOW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(ADCOW::_0)
|
||||
}
|
||||
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(ADCOW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 3;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CALW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CALW<'a> {
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 7;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:1 - Hardware Average Select"]
|
||||
#[inline]
|
||||
pub fn avgs(&self) -> AVGSR {
|
||||
AVGSR::_from({
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 2 - Hardware Average Enable"]
|
||||
#[inline]
|
||||
pub fn avge(&self) -> AVGER {
|
||||
AVGER::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 2;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 3 - Continuous Conversion Enable"]
|
||||
#[inline]
|
||||
pub fn adco(&self) -> ADCOR {
|
||||
ADCOR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 3;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 7 - Calibration"]
|
||||
#[inline]
|
||||
pub fn cal(&self) -> CALR {
|
||||
let bits = {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 7;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
};
|
||||
CALR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:1 - Hardware Average Select"]
|
||||
#[inline]
|
||||
pub fn avgs(&mut self) -> _AVGSW {
|
||||
_AVGSW { w: self }
|
||||
}
|
||||
#[doc = "Bit 2 - Hardware Average Enable"]
|
||||
#[inline]
|
||||
pub fn avge(&mut self) -> _AVGEW {
|
||||
_AVGEW { w: self }
|
||||
}
|
||||
#[doc = "Bit 3 - Continuous Conversion Enable"]
|
||||
#[inline]
|
||||
pub fn adco(&mut self) -> _ADCOW {
|
||||
_ADCOW { w: self }
|
||||
}
|
||||
#[doc = "Bit 7 - Calibration"]
|
||||
#[inline]
|
||||
pub fn cal(&mut self) -> _CALW {
|
||||
_CALW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register SC3"]
|
||||
pub type R = crate::R<u32, super::SC3>;
|
||||
#[doc = "Writer for register SC3"]
|
||||
pub type W = crate::W<u32, super::SC3>;
|
||||
#[doc = "Register SC3 `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::SC3 {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Hardware Average Select\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
#[repr(u8)]
|
||||
pub enum AVGS_A {
|
||||
#[doc = "0: 4 samples averaged."]
|
||||
_00 = 0,
|
||||
#[doc = "1: 8 samples averaged."]
|
||||
_01 = 1,
|
||||
#[doc = "2: 16 samples averaged."]
|
||||
_10 = 2,
|
||||
#[doc = "3: 32 samples averaged."]
|
||||
_11 = 3,
|
||||
}
|
||||
impl From<AVGS_A> for u8 {
|
||||
#[inline(always)]
|
||||
fn from(variant: AVGS_A) -> Self {
|
||||
variant as _
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `AVGS`"]
|
||||
pub type AVGS_R = crate::R<u8, AVGS_A>;
|
||||
impl AVGS_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> AVGS_A {
|
||||
match self.bits {
|
||||
0 => AVGS_A::_00,
|
||||
1 => AVGS_A::_01,
|
||||
2 => AVGS_A::_10,
|
||||
3 => AVGS_A::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline(always)]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == AVGS_A::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline(always)]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == AVGS_A::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline(always)]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == AVGS_A::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline(always)]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == AVGS_A::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `AVGS`"]
|
||||
pub struct AVGS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> AVGS_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: AVGS_A) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "4 samples averaged."]
|
||||
#[inline(always)]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(AVGS_A::_00)
|
||||
}
|
||||
#[doc = "8 samples averaged."]
|
||||
#[inline(always)]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(AVGS_A::_01)
|
||||
}
|
||||
#[doc = "16 samples averaged."]
|
||||
#[inline(always)]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(AVGS_A::_10)
|
||||
}
|
||||
#[doc = "32 samples averaged."]
|
||||
#[inline(always)]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(AVGS_A::_11)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Hardware Average Enable\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum AVGE_A {
|
||||
#[doc = "0: Hardware average function disabled."]
|
||||
_0 = 0,
|
||||
#[doc = "1: Hardware average function enabled."]
|
||||
_1 = 1,
|
||||
}
|
||||
impl From<AVGE_A> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: AVGE_A) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `AVGE`"]
|
||||
pub type AVGE_R = crate::R<bool, AVGE_A>;
|
||||
impl AVGE_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> AVGE_A {
|
||||
match self.bits {
|
||||
false => AVGE_A::_0,
|
||||
true => AVGE_A::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == AVGE_A::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == AVGE_A::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `AVGE`"]
|
||||
pub struct AVGE_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> AVGE_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: AVGE_A) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "Hardware average function disabled."]
|
||||
#[inline(always)]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(AVGE_A::_0)
|
||||
}
|
||||
#[doc = "Hardware average function enabled."]
|
||||
#[inline(always)]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(AVGE_A::_1)
|
||||
}
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Continuous Conversion Enable\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADCO_A {
|
||||
#[doc = "0: One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
|
||||
_0 = 0,
|
||||
#[doc = "1: Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
|
||||
_1 = 1,
|
||||
}
|
||||
impl From<ADCO_A> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: ADCO_A) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `ADCO`"]
|
||||
pub type ADCO_R = crate::R<bool, ADCO_A>;
|
||||
impl ADCO_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> ADCO_A {
|
||||
match self.bits {
|
||||
false => ADCO_A::_0,
|
||||
true => ADCO_A::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == ADCO_A::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == ADCO_A::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `ADCO`"]
|
||||
pub struct ADCO_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> ADCO_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: ADCO_A) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "One conversion will be performed (or one set of conversions, if AVGE is set) after a conversion is initiated."]
|
||||
#[inline(always)]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(ADCO_A::_0)
|
||||
}
|
||||
#[doc = "Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated."]
|
||||
#[inline(always)]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(ADCO_A::_1)
|
||||
}
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `CAL`"]
|
||||
pub type CAL_R = crate::R<bool, bool>;
|
||||
#[doc = "Write proxy for field `CAL`"]
|
||||
pub struct CAL_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CAL_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:1 - Hardware Average Select"]
|
||||
#[inline(always)]
|
||||
pub fn avgs(&self) -> AVGS_R {
|
||||
AVGS_R::new((self.bits & 0x03) as u8)
|
||||
}
|
||||
#[doc = "Bit 2 - Hardware Average Enable"]
|
||||
#[inline(always)]
|
||||
pub fn avge(&self) -> AVGE_R {
|
||||
AVGE_R::new(((self.bits >> 2) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - Continuous Conversion Enable"]
|
||||
#[inline(always)]
|
||||
pub fn adco(&self) -> ADCO_R {
|
||||
ADCO_R::new(((self.bits >> 3) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 7 - Calibration"]
|
||||
#[inline(always)]
|
||||
pub fn cal(&self) -> CAL_R {
|
||||
CAL_R::new(((self.bits >> 7) & 0x01) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:1 - Hardware Average Select"]
|
||||
#[inline(always)]
|
||||
pub fn avgs(&mut self) -> AVGS_W {
|
||||
AVGS_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 2 - Hardware Average Enable"]
|
||||
#[inline(always)]
|
||||
pub fn avge(&mut self) -> AVGE_W {
|
||||
AVGE_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 3 - Continuous Conversion Enable"]
|
||||
#[inline(always)]
|
||||
pub fn adco(&mut self) -> ADCO_W {
|
||||
ADCO_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 7 - Calibration"]
|
||||
#[inline(always)]
|
||||
pub fn cal(&mut self) -> CAL_W {
|
||||
CAL_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/ug.rs
143
src/adc0/ug.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::UG {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct UGR {
|
||||
bits: u16,
|
||||
}
|
||||
impl UGR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u16 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _UGW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _UGW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
const MASK: u16 = 1023;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:9 - User gain error correction value"]
|
||||
#[inline]
|
||||
pub fn ug(&self) -> UGR {
|
||||
let bits = {
|
||||
const MASK: u16 = 1023;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u16
|
||||
};
|
||||
UGR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 4 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:9 - User gain error correction value"]
|
||||
#[inline]
|
||||
pub fn ug(&mut self) -> _UGW {
|
||||
_UGW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register UG"]
|
||||
pub type R = crate::R<u32, super::UG>;
|
||||
#[doc = "Writer for register UG"]
|
||||
pub type W = crate::W<u32, super::UG>;
|
||||
#[doc = "Register UG `reset()`'s with value 0x04"]
|
||||
impl crate::ResetValue for super::UG {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x04
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `UG`"]
|
||||
pub type UG_R = crate::R<u16, u16>;
|
||||
#[doc = "Write proxy for field `UG`"]
|
||||
pub struct UG_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> UG_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u16) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x03ff) | ((value as u32) & 0x03ff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:9 - User gain error correction value"]
|
||||
#[inline(always)]
|
||||
pub fn ug(&self) -> UG_R {
|
||||
UG_R::new((self.bits & 0x03ff) as u16)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:9 - User gain error correction value"]
|
||||
#[inline(always)]
|
||||
pub fn ug(&mut self) -> UG_W {
|
||||
UG_W { w: self }
|
||||
}
|
||||
}
|
||||
|
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::USR_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct USR_OFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl USR_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _USR_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _USR_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:7 - USER Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn usr_ofs(&self) -> USR_OFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
USR_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:7 - USER Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn usr_ofs(&mut self) -> _USR_OFSW {
|
||||
_USR_OFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register USR_OFS"]
|
||||
pub type R = crate::R<u32, super::USR_OFS>;
|
||||
#[doc = "Writer for register USR_OFS"]
|
||||
pub type W = crate::W<u32, super::USR_OFS>;
|
||||
#[doc = "Register USR_OFS `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::USR_OFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `USR_OFS`"]
|
||||
pub type USR_OFS_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `USR_OFS`"]
|
||||
pub struct USR_OFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> USR_OFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:7 - USER Offset Error Correction Value"]
|
||||
#[inline(always)]
|
||||
pub fn usr_ofs(&self) -> USR_OFS_R {
|
||||
USR_OFS_R::new((self.bits & 0xff) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:7 - USER Offset Error Correction Value"]
|
||||
#[inline(always)]
|
||||
pub fn usr_ofs(&mut self) -> USR_OFS_W {
|
||||
USR_OFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/xofs.rs
143
src/adc0/xofs.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::XOFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct XOFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl XOFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _XOFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _XOFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 63;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:5 - X offset error correction value"]
|
||||
#[inline]
|
||||
pub fn xofs(&self) -> XOFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 63;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
XOFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 48 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:5 - X offset error correction value"]
|
||||
#[inline]
|
||||
pub fn xofs(&mut self) -> _XOFSW {
|
||||
_XOFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register XOFS"]
|
||||
pub type R = crate::R<u32, super::XOFS>;
|
||||
#[doc = "Writer for register XOFS"]
|
||||
pub type W = crate::W<u32, super::XOFS>;
|
||||
#[doc = "Register XOFS `reset()`'s with value 0x30"]
|
||||
impl crate::ResetValue for super::XOFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x30
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `XOFS`"]
|
||||
pub type XOFS_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `XOFS`"]
|
||||
pub struct XOFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> XOFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x3f) | ((value as u32) & 0x3f);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:5 - X offset error correction value"]
|
||||
#[inline(always)]
|
||||
pub fn xofs(&self) -> XOFS_R {
|
||||
XOFS_R::new((self.bits & 0x3f) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:5 - X offset error correction value"]
|
||||
#[inline(always)]
|
||||
pub fn xofs(&mut self) -> XOFS_W {
|
||||
XOFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
143
src/adc0/yofs.rs
143
src/adc0/yofs.rs
@ -1,103 +1,40 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::YOFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct YOFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl YOFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _YOFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _YOFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:7 - Y offset error correction value"]
|
||||
#[inline]
|
||||
pub fn yofs(&self) -> YOFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
YOFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 55 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:7 - Y offset error correction value"]
|
||||
#[inline]
|
||||
pub fn yofs(&mut self) -> _YOFSW {
|
||||
_YOFSW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register YOFS"]
|
||||
pub type R = crate::R<u32, super::YOFS>;
|
||||
#[doc = "Writer for register YOFS"]
|
||||
pub type W = crate::W<u32, super::YOFS>;
|
||||
#[doc = "Register YOFS `reset()`'s with value 0x37"]
|
||||
impl crate::ResetValue for super::YOFS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x37
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `YOFS`"]
|
||||
pub type YOFS_R = crate::R<u8, u8>;
|
||||
#[doc = "Write proxy for field `YOFS`"]
|
||||
pub struct YOFS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> YOFS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0xff) | ((value as u32) & 0xff);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:7 - Y offset error correction value"]
|
||||
#[inline(always)]
|
||||
pub fn yofs(&self) -> YOFS_R {
|
||||
YOFS_R::new((self.bits & 0xff) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:7 - Y offset error correction value"]
|
||||
#[inline(always)]
|
||||
pub fn yofs(&mut self) -> YOFS_W {
|
||||
YOFS_W { w: self }
|
||||
}
|
||||
}
|
||||
|
290
src/adc1.rs
290
src/adc1.rs
@ -1,290 +0,0 @@
|
||||
#[doc = r" Register block"]
|
||||
#[repr(C)]
|
||||
pub struct RegisterBlock {
|
||||
#[doc = "0x00 - ADC Status and Control Register 1"]
|
||||
pub sc1a: SC1,
|
||||
#[doc = "0x04 - ADC Status and Control Register 1"]
|
||||
pub sc1b: SC1,
|
||||
#[doc = "0x08 - ADC Status and Control Register 1"]
|
||||
pub sc1c: SC1,
|
||||
#[doc = "0x0c - ADC Status and Control Register 1"]
|
||||
pub sc1d: SC1,
|
||||
#[doc = "0x10 - ADC Status and Control Register 1"]
|
||||
pub sc1e: SC1,
|
||||
#[doc = "0x14 - ADC Status and Control Register 1"]
|
||||
pub sc1f: SC1,
|
||||
#[doc = "0x18 - ADC Status and Control Register 1"]
|
||||
pub sc1g: SC1,
|
||||
#[doc = "0x1c - ADC Status and Control Register 1"]
|
||||
pub sc1h: SC1,
|
||||
#[doc = "0x20 - ADC Status and Control Register 1"]
|
||||
pub sc1i: SC1,
|
||||
#[doc = "0x24 - ADC Status and Control Register 1"]
|
||||
pub sc1j: SC1,
|
||||
#[doc = "0x28 - ADC Status and Control Register 1"]
|
||||
pub sc1k: SC1,
|
||||
#[doc = "0x2c - ADC Status and Control Register 1"]
|
||||
pub sc1l: SC1,
|
||||
#[doc = "0x30 - ADC Status and Control Register 1"]
|
||||
pub sc1m: SC1,
|
||||
#[doc = "0x34 - ADC Status and Control Register 1"]
|
||||
pub sc1n: SC1,
|
||||
#[doc = "0x38 - ADC Status and Control Register 1"]
|
||||
pub sc1o: SC1,
|
||||
#[doc = "0x3c - ADC Status and Control Register 1"]
|
||||
pub sc1p: SC1,
|
||||
#[doc = "0x40 - ADC Configuration Register 1"]
|
||||
pub cfg1: CFG1,
|
||||
#[doc = "0x44 - ADC Configuration Register 2"]
|
||||
pub cfg2: CFG2,
|
||||
#[doc = "0x48 - ADC Data Result Registers"]
|
||||
pub ra: R,
|
||||
#[doc = "0x4c - ADC Data Result Registers"]
|
||||
pub rb: R,
|
||||
#[doc = "0x50 - ADC Data Result Registers"]
|
||||
pub rc: R,
|
||||
#[doc = "0x54 - ADC Data Result Registers"]
|
||||
pub rd: R,
|
||||
#[doc = "0x58 - ADC Data Result Registers"]
|
||||
pub re: R,
|
||||
#[doc = "0x5c - ADC Data Result Registers"]
|
||||
pub rf: R,
|
||||
#[doc = "0x60 - ADC Data Result Registers"]
|
||||
pub rg: R,
|
||||
#[doc = "0x64 - ADC Data Result Registers"]
|
||||
pub rh: R,
|
||||
#[doc = "0x68 - ADC Data Result Registers"]
|
||||
pub ri: R,
|
||||
#[doc = "0x6c - ADC Data Result Registers"]
|
||||
pub rj: R,
|
||||
#[doc = "0x70 - ADC Data Result Registers"]
|
||||
pub rk: R,
|
||||
#[doc = "0x74 - ADC Data Result Registers"]
|
||||
pub rl: R,
|
||||
#[doc = "0x78 - ADC Data Result Registers"]
|
||||
pub rm: R,
|
||||
#[doc = "0x7c - ADC Data Result Registers"]
|
||||
pub rn: R,
|
||||
#[doc = "0x80 - ADC Data Result Registers"]
|
||||
pub ro: R,
|
||||
#[doc = "0x84 - ADC Data Result Registers"]
|
||||
pub rp: R,
|
||||
#[doc = "0x88 - Compare Value Registers"]
|
||||
pub cv1: CV,
|
||||
#[doc = "0x8c - Compare Value Registers"]
|
||||
pub cv2: CV,
|
||||
#[doc = "0x90 - Status and Control Register 2"]
|
||||
pub sc2: SC2,
|
||||
#[doc = "0x94 - Status and Control Register 3"]
|
||||
pub sc3: SC3,
|
||||
#[doc = "0x98 - BASE Offset Register"]
|
||||
pub base_ofs: BASE_OFS,
|
||||
#[doc = "0x9c - ADC Offset Correction Register"]
|
||||
pub ofs: OFS,
|
||||
#[doc = "0xa0 - USER Offset Correction Register"]
|
||||
pub usr_ofs: USR_OFS,
|
||||
#[doc = "0xa4 - ADC X Offset Correction Register"]
|
||||
pub xofs: XOFS,
|
||||
#[doc = "0xa8 - ADC Y Offset Correction Register"]
|
||||
pub yofs: YOFS,
|
||||
#[doc = "0xac - ADC Gain Register"]
|
||||
pub g: G,
|
||||
#[doc = "0xb0 - ADC User Gain Register"]
|
||||
pub ug: UG,
|
||||
#[doc = "0xb4 - ADC General Calibration Value Register S"]
|
||||
pub clps: CLPS,
|
||||
#[doc = "0xb8 - ADC Plus-Side General Calibration Value Register 3"]
|
||||
pub clp3: CLP3,
|
||||
#[doc = "0xbc - ADC Plus-Side General Calibration Value Register 2"]
|
||||
pub clp2: CLP2,
|
||||
#[doc = "0xc0 - ADC Plus-Side General Calibration Value Register 1"]
|
||||
pub clp1: CLP1,
|
||||
#[doc = "0xc4 - ADC Plus-Side General Calibration Value Register 0"]
|
||||
pub clp0: CLP0,
|
||||
#[doc = "0xc8 - ADC Plus-Side General Calibration Value Register X"]
|
||||
pub clpx: CLPX,
|
||||
#[doc = "0xcc - ADC Plus-Side General Calibration Value Register 9"]
|
||||
pub clp9: CLP9,
|
||||
#[doc = "0xd0 - ADC General Calibration Offset Value Register S"]
|
||||
pub clps_ofs: CLPS_OFS,
|
||||
#[doc = "0xd4 - ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub clp3_ofs: CLP3_OFS,
|
||||
#[doc = "0xd8 - ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub clp2_ofs: CLP2_OFS,
|
||||
#[doc = "0xdc - ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub clp1_ofs: CLP1_OFS,
|
||||
#[doc = "0xe0 - ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub clp0_ofs: CLP0_OFS,
|
||||
#[doc = "0xe4 - ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub clpx_ofs: CLPX_OFS,
|
||||
#[doc = "0xe8 - ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub clp9_ofs: CLP9_OFS,
|
||||
}
|
||||
#[doc = "ADC Status and Control Register 1"]
|
||||
pub struct SC1 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Status and Control Register 1"]
|
||||
pub mod sc1;
|
||||
#[doc = "ADC Configuration Register 1"]
|
||||
pub struct CFG1 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Configuration Register 1"]
|
||||
pub mod cfg1;
|
||||
#[doc = "ADC Configuration Register 2"]
|
||||
pub struct CFG2 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Configuration Register 2"]
|
||||
pub mod cfg2;
|
||||
#[doc = "ADC Data Result Registers"]
|
||||
pub struct R {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Data Result Registers"]
|
||||
pub mod r;
|
||||
#[doc = "Compare Value Registers"]
|
||||
pub struct CV {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Compare Value Registers"]
|
||||
pub mod cv;
|
||||
#[doc = "Status and Control Register 2"]
|
||||
pub struct SC2 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Status and Control Register 2"]
|
||||
pub mod sc2;
|
||||
#[doc = "Status and Control Register 3"]
|
||||
pub struct SC3 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "Status and Control Register 3"]
|
||||
pub mod sc3;
|
||||
#[doc = "BASE Offset Register"]
|
||||
pub struct BASE_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "BASE Offset Register"]
|
||||
pub mod base_ofs;
|
||||
#[doc = "ADC Offset Correction Register"]
|
||||
pub struct OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Offset Correction Register"]
|
||||
pub mod ofs;
|
||||
#[doc = "USER Offset Correction Register"]
|
||||
pub struct USR_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "USER Offset Correction Register"]
|
||||
pub mod usr_ofs;
|
||||
#[doc = "ADC X Offset Correction Register"]
|
||||
pub struct XOFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC X Offset Correction Register"]
|
||||
pub mod xofs;
|
||||
#[doc = "ADC Y Offset Correction Register"]
|
||||
pub struct YOFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Y Offset Correction Register"]
|
||||
pub mod yofs;
|
||||
#[doc = "ADC Gain Register"]
|
||||
pub struct G {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Gain Register"]
|
||||
pub mod g;
|
||||
#[doc = "ADC User Gain Register"]
|
||||
pub struct UG {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC User Gain Register"]
|
||||
pub mod ug;
|
||||
#[doc = "ADC General Calibration Value Register S"]
|
||||
pub struct CLPS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC General Calibration Value Register S"]
|
||||
pub mod clps;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
|
||||
pub struct CLP3 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 3"]
|
||||
pub mod clp3;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
|
||||
pub struct CLP2 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 2"]
|
||||
pub mod clp2;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
|
||||
pub struct CLP1 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 1"]
|
||||
pub mod clp1;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
|
||||
pub struct CLP0 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 0"]
|
||||
pub mod clp0;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register X"]
|
||||
pub struct CLPX {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register X"]
|
||||
pub mod clpx;
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
|
||||
pub struct CLP9 {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Value Register 9"]
|
||||
pub mod clp9;
|
||||
#[doc = "ADC General Calibration Offset Value Register S"]
|
||||
pub struct CLPS_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC General Calibration Offset Value Register S"]
|
||||
pub mod clps_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub struct CLP3_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 3"]
|
||||
pub mod clp3_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub struct CLP2_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 2"]
|
||||
pub mod clp2_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub struct CLP1_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 1"]
|
||||
pub mod clp1_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub struct CLP0_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 0"]
|
||||
pub mod clp0_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub struct CLPX_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register X"]
|
||||
pub mod clpx_ofs;
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub struct CLP9_OFS {
|
||||
register: ::vcell::VolatileCell<u32>,
|
||||
}
|
||||
#[doc = "ADC Plus-Side General Calibration Offset Value Register 9"]
|
||||
pub mod clp9_ofs;
|
@ -1,103 +0,0 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::BASE_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct BA_OFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl BA_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _BA_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _BA_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn ba_ofs(&self) -> BA_OFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
BA_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 64 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:7 - Base Offset Error Correction Value"]
|
||||
#[inline]
|
||||
pub fn ba_ofs(&mut self) -> _BA_OFSW {
|
||||
_BA_OFSW { w: self }
|
||||
}
|
||||
}
|
482
src/adc1/cfg1.rs
482
src/adc1/cfg1.rs
@ -1,482 +0,0 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CFG1 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `ADICLK`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADICLKR {
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
_00,
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
_01,
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
_10,
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
_11,
|
||||
}
|
||||
impl ADICLKR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADICLKR::_00 => 0,
|
||||
ADICLKR::_01 => 1,
|
||||
ADICLKR::_10 => 2,
|
||||
ADICLKR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> ADICLKR {
|
||||
match value {
|
||||
0 => ADICLKR::_00,
|
||||
1 => ADICLKR::_01,
|
||||
2 => ADICLKR::_10,
|
||||
3 => ADICLKR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == ADICLKR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == ADICLKR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == ADICLKR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == ADICLKR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `MODE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum MODER {
|
||||
#[doc = "8-bit conversion."]
|
||||
_00,
|
||||
#[doc = "12-bit conversion."]
|
||||
_01,
|
||||
#[doc = "10-bit conversion."]
|
||||
_10,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
}
|
||||
impl MODER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
MODER::_00 => 0,
|
||||
MODER::_01 => 1,
|
||||
MODER::_10 => 2,
|
||||
MODER::_Reserved(bits) => bits,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> MODER {
|
||||
match value {
|
||||
0 => MODER::_00,
|
||||
1 => MODER::_01,
|
||||
2 => MODER::_10,
|
||||
i => MODER::_Reserved(i),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == MODER::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == MODER::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == MODER::_10
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `ADIV`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum ADIVR {
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
_00,
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
_01,
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
_10,
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
_11,
|
||||
}
|
||||
impl ADIVR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADIVR::_00 => 0,
|
||||
ADIVR::_01 => 1,
|
||||
ADIVR::_10 => 2,
|
||||
ADIVR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> ADIVR {
|
||||
match value {
|
||||
0 => ADIVR::_00,
|
||||
1 => ADIVR::_01,
|
||||
2 => ADIVR::_10,
|
||||
3 => ADIVR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == ADIVR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == ADIVR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == ADIVR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == ADIVR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADICLK`"]
|
||||
pub enum ADICLKW {
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
_00,
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
_01,
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
_10,
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
_11,
|
||||
}
|
||||
impl ADICLKW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADICLKW::_00 => 0,
|
||||
ADICLKW::_01 => 1,
|
||||
ADICLKW::_10 => 2,
|
||||
ADICLKW::_11 => 3,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _ADICLKW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _ADICLKW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: ADICLKW) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Alternate clock 1 (ADC_ALTCLK1)"]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_00)
|
||||
}
|
||||
#[doc = "Alternate clock 2 (ADC_ALTCLK2)"]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_01)
|
||||
}
|
||||
#[doc = "Alternate clock 3 (ADC_ALTCLK3)"]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_10)
|
||||
}
|
||||
#[doc = "Alternate clock 4 (ADC_ALTCLK4)"]
|
||||
#[inline]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(ADICLKW::_11)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `MODE`"]
|
||||
pub enum MODEW {
|
||||
#[doc = "8-bit conversion."]
|
||||
_00,
|
||||
#[doc = "12-bit conversion."]
|
||||
_01,
|
||||
#[doc = "10-bit conversion."]
|
||||
_10,
|
||||
}
|
||||
impl MODEW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
MODEW::_00 => 0,
|
||||
MODEW::_01 => 1,
|
||||
MODEW::_10 => 2,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _MODEW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _MODEW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: MODEW) -> &'a mut W {
|
||||
unsafe { self.bits(variant._bits()) }
|
||||
}
|
||||
#[doc = "8-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(MODEW::_00)
|
||||
}
|
||||
#[doc = "12-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(MODEW::_01)
|
||||
}
|
||||
#[doc = "10-bit conversion."]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(MODEW::_10)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 2;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `ADIV`"]
|
||||
pub enum ADIVW {
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
_00,
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
_01,
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
_10,
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
_11,
|
||||
}
|
||||
impl ADIVW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
ADIVW::_00 => 0,
|
||||
ADIVW::_01 => 1,
|
||||
ADIVW::_10 => 2,
|
||||
ADIVW::_11 => 3,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _ADIVW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _ADIVW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: ADIVW) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "The divide ratio is 1 and the clock rate is input clock."]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_00)
|
||||
}
|
||||
#[doc = "The divide ratio is 2 and the clock rate is (input clock)/2."]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_01)
|
||||
}
|
||||
#[doc = "The divide ratio is 4 and the clock rate is (input clock)/4."]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_10)
|
||||
}
|
||||
#[doc = "The divide ratio is 8 and the clock rate is (input clock)/8."]
|
||||
#[inline]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(ADIVW::_11)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 5;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLRLTRGW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLRLTRGW<'a> {
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 8;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:1 - Input Clock Select"]
|
||||
#[inline]
|
||||
pub fn adiclk(&self) -> ADICLKR {
|
||||
ADICLKR::_from({
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
#[doc = "Bits 2:3 - Conversion mode selection"]
|
||||
#[inline]
|
||||
pub fn mode(&self) -> MODER {
|
||||
MODER::_from({
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 2;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
#[doc = "Bits 5:6 - Clock Divide Select"]
|
||||
#[inline]
|
||||
pub fn adiv(&self) -> ADIVR {
|
||||
ADIVR::_from({
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 5;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:1 - Input Clock Select"]
|
||||
#[inline]
|
||||
pub fn adiclk(&mut self) -> _ADICLKW {
|
||||
_ADICLKW { w: self }
|
||||
}
|
||||
#[doc = "Bits 2:3 - Conversion mode selection"]
|
||||
#[inline]
|
||||
pub fn mode(&mut self) -> _MODEW {
|
||||
_MODEW { w: self }
|
||||
}
|
||||
#[doc = "Bits 5:6 - Clock Divide Select"]
|
||||
#[inline]
|
||||
pub fn adiv(&mut self) -> _ADIVW {
|
||||
_ADIVW { w: self }
|
||||
}
|
||||
#[doc = "Bit 8 - Clear Latch Trigger in Trigger Handler Block"]
|
||||
#[inline]
|
||||
pub fn clrltrg(&mut self) -> _CLRLTRGW {
|
||||
_CLRLTRGW { w: self }
|
||||
}
|
||||
}
|
103
src/adc1/cfg2.rs
103
src/adc1/cfg2.rs
@ -1,103 +0,0 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CFG2 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct SMPLTSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl SMPLTSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _SMPLTSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _SMPLTSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:7 - Sample Time Select"]
|
||||
#[inline]
|
||||
pub fn smplts(&self) -> SMPLTSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
SMPLTSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 12 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:7 - Sample Time Select"]
|
||||
#[inline]
|
||||
pub fn smplts(&mut self) -> _SMPLTSW {
|
||||
_SMPLTSW { w: self }
|
||||
}
|
||||
}
|
103
src/adc1/clp0.rs
103
src/adc1/clp0.rs
@ -1,103 +0,0 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP0 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLP0R {
|
||||
bits: u8,
|
||||
}
|
||||
impl CLP0R {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLP0W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLP0W<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:7 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clp0(&self) -> CLP0R {
|
||||
let bits = {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
CLP0R { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 46 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:7 - Calibration Value"]
|
||||
#[inline]
|
||||
pub fn clp0(&mut self) -> _CLP0W {
|
||||
_CLP0W { w: self }
|
||||
}
|
||||
}
|
@ -1,103 +0,0 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP0_OFS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct CLP0_OFSR {
|
||||
bits: u8,
|
||||
}
|
||||
impl CLP0_OFSR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _CLP0_OFSW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _CLP0_OFSW<'a> {
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:3 - CLP0 Offset"]
|
||||
#[inline]
|
||||
pub fn clp0_ofs(&self) -> CLP0_OFSR {
|
||||
let bits = {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
CLP0_OFSR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bits 0:3 - CLP0 Offset"]
|
||||
#[inline]
|
||||
pub fn clp0_ofs(&mut self) -> _CLP0_OFSW {
|
||||
_CLP0_OFSW { w: self }
|
||||
}
|
||||
}
|
103
src/adc1/clp1.rs
103
src/adc1/clp1.rs
@ -1,103 +0,0 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::CLP1 {
|
||||
#[doc = r& |