s32k118: rewrite everything for s32k118
Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
@ -1,222 +1,125 @@
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#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::TRGMUX_LPSPI0 {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = r" Value of the field"]
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pub struct SEL0R {
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bits: u8,
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}
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impl SEL0R {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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self.bits
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}
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}
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#[doc = "Possible values of the field `LK`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum LKR {
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#[doc = "Register can be written."]
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_0,
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#[doc = "Register cannot be written until the next system Reset."]
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_1,
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}
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impl LKR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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LKR::_0 => false,
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LKR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> LKR {
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match value {
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false => LKR::_0,
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true => LKR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == LKR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == LKR::_1
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}
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}
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#[doc = r" Proxy"]
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pub struct _SEL0W<'a> {
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w: &'a mut W,
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}
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impl<'a> _SEL0W<'a> {
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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const MASK: u8 = 63;
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const OFFSET: u8 = 0;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `LK`"]
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pub enum LKW {
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#[doc = "Register can be written."]
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_0,
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#[doc = "Register cannot be written until the next system Reset."]
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_1,
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}
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impl LKW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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LKW::_0 => false,
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LKW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _LKW<'a> {
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w: &'a mut W,
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}
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impl<'a> _LKW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: LKW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Register can be written."]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(LKW::_0)
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}
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#[doc = "Register cannot be written until the next system Reset."]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(LKW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 31;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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impl R {
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#[doc = r" Value of the register as raw bits"]
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#[inline]
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pub fn bits(&self) -> u32 {
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self.bits
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}
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#[doc = "Bits 0:5 - Trigger MUX Input 0 Source Select"]
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#[inline]
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pub fn sel0(&self) -> SEL0R {
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let bits = {
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const MASK: u8 = 63;
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const OFFSET: u8 = 0;
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((self.bits >> OFFSET) & MASK as u32) as u8
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};
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SEL0R { bits }
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}
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#[doc = "Bit 31 - TRGMUX register lock."]
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#[inline]
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pub fn lk(&self) -> LKR {
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LKR::_from({
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const MASK: bool = true;
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const OFFSET: u8 = 31;
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((self.bits >> OFFSET) & MASK as u32) != 0
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})
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}
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}
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impl W {
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#[doc = r" Reset value of the register"]
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#[inline]
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pub fn reset_value() -> W {
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W { bits: 0 }
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}
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#[doc = r" Writes raw bits to the register"]
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#[inline]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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self.bits = bits;
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self
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}
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#[doc = "Bits 0:5 - Trigger MUX Input 0 Source Select"]
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#[inline]
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pub fn sel0(&mut self) -> _SEL0W {
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_SEL0W { w: self }
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}
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#[doc = "Bit 31 - TRGMUX register lock."]
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#[inline]
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pub fn lk(&mut self) -> _LKW {
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_LKW { w: self }
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}
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}
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#[doc = "Reader of register TRGMUX_LPSPI0"]
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pub type R = crate::R<u32, super::TRGMUX_LPSPI0>;
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#[doc = "Writer for register TRGMUX_LPSPI0"]
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pub type W = crate::W<u32, super::TRGMUX_LPSPI0>;
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#[doc = "Register TRGMUX_LPSPI0 `reset()`'s with value 0"]
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impl crate::ResetValue for super::TRGMUX_LPSPI0 {
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type Type = u32;
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#[inline(always)]
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fn reset_value() -> Self::Type {
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0
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}
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}
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#[doc = "Reader of field `SEL0`"]
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pub type SEL0_R = crate::R<u8, u8>;
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#[doc = "Write proxy for field `SEL0`"]
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pub struct SEL0_W<'a> {
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w: &'a mut W,
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}
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impl<'a> SEL0_W<'a> {
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = (self.w.bits & !0x3f) | ((value as u32) & 0x3f);
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self.w
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}
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}
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#[doc = "TRGMUX register lock.\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum LK_A {
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#[doc = "0: Register can be written."]
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_0 = 0,
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#[doc = "1: Register cannot be written until the next system Reset."]
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_1 = 1,
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}
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impl From<LK_A> for bool {
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#[inline(always)]
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fn from(variant: LK_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `LK`"]
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pub type LK_R = crate::R<bool, LK_A>;
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impl LK_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> LK_A {
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match self.bits {
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false => LK_A::_0,
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true => LK_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == LK_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == LK_A::_1
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}
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}
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#[doc = "Write proxy for field `LK`"]
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pub struct LK_W<'a> {
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w: &'a mut W,
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}
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impl<'a> LK_W<'a> {
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#[doc = r"Writes `variant` to the field"]
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#[inline(always)]
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pub fn variant(self, variant: LK_A) -> &'a mut W {
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{
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self.bit(variant.into())
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}
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}
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#[doc = "Register can be written."]
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#[inline(always)]
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pub fn _0(self) -> &'a mut W {
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self.variant(LK_A::_0)
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}
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#[doc = "Register cannot be written until the next system Reset."]
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#[inline(always)]
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pub fn _1(self) -> &'a mut W {
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self.variant(LK_A::_1)
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}
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31);
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self.w
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}
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}
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impl R {
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#[doc = "Bits 0:5 - Trigger MUX Input 0 Source Select"]
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#[inline(always)]
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pub fn sel0(&self) -> SEL0_R {
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SEL0_R::new((self.bits & 0x3f) as u8)
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}
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#[doc = "Bit 31 - TRGMUX register lock."]
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#[inline(always)]
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pub fn lk(&self) -> LK_R {
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LK_R::new(((self.bits >> 31) & 0x01) != 0)
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}
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}
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impl W {
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#[doc = "Bits 0:5 - Trigger MUX Input 0 Source Select"]
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#[inline(always)]
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pub fn sel0(&mut self) -> SEL0_W {
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SEL0_W { w: self }
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}
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#[doc = "Bit 31 - TRGMUX register lock."]
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#[inline(always)]
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pub fn lk(&mut self) -> LK_W {
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LK_W { w: self }
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}
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}
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