s32k118: rewrite everything for s32k118
Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
1622
src/sim/adcopt.rs
1622
src/sim/adcopt.rs
File diff suppressed because it is too large
Load Diff
2182
src/sim/chipctl.rs
2182
src/sim/chipctl.rs
File diff suppressed because it is too large
Load Diff
@ -1,281 +1,159 @@
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#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::CLKDIV4 {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = r" Value of the field"]
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pub struct TRACEFRACR {
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bits: bool,
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}
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impl TRACEFRACR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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self.bits
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}
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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}
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#[doc = r" Value of the field"]
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pub struct TRACEDIVR {
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bits: u8,
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}
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impl TRACEDIVR {
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bits(&self) -> u8 {
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self.bits
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}
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}
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#[doc = "Possible values of the field `TRACEDIVEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TRACEDIVENR {
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#[doc = "Debug trace divider disabled"]
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_0,
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#[doc = "Debug trace divider enabled"]
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_1,
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}
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impl TRACEDIVENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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TRACEDIVENR::_0 => false,
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TRACEDIVENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> TRACEDIVENR {
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match value {
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false => TRACEDIVENR::_0,
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true => TRACEDIVENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == TRACEDIVENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == TRACEDIVENR::_1
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}
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}
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#[doc = r" Proxy"]
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pub struct _TRACEFRACW<'a> {
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w: &'a mut W,
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}
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impl<'a> _TRACEFRACW<'a> {
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 0;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = r" Proxy"]
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pub struct _TRACEDIVW<'a> {
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w: &'a mut W,
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}
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impl<'a> _TRACEDIVW<'a> {
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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const MASK: u8 = 7;
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const OFFSET: u8 = 1;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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#[doc = "Values that can be written to the field `TRACEDIVEN`"]
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pub enum TRACEDIVENW {
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#[doc = "Debug trace divider disabled"]
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_0,
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#[doc = "Debug trace divider enabled"]
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_1,
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}
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impl TRACEDIVENW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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TRACEDIVENW::_0 => false,
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TRACEDIVENW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _TRACEDIVENW<'a> {
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w: &'a mut W,
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}
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impl<'a> _TRACEDIVENW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: TRACEDIVENW) -> &'a mut W {
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{
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self.bit(variant._bits())
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}
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}
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#[doc = "Debug trace divider disabled"]
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#[inline]
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pub fn _0(self) -> &'a mut W {
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self.variant(TRACEDIVENW::_0)
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}
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#[doc = "Debug trace divider enabled"]
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#[inline]
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pub fn _1(self) -> &'a mut W {
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self.variant(TRACEDIVENW::_1)
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}
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#[doc = r" Sets the field bit"]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r" Clears the field bit"]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r" Writes raw bits to the field"]
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#[inline]
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pub fn bit(self, value: bool) -> &'a mut W {
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const MASK: bool = true;
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const OFFSET: u8 = 28;
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self.w.bits &= !((MASK as u32) << OFFSET);
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
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self.w
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}
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}
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impl R {
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#[doc = r" Value of the register as raw bits"]
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#[inline]
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pub fn bits(&self) -> u32 {
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self.bits
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}
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#[doc = "Bit 0 - Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear TRACEDIVEN to disable the trace clock divide function."]
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#[inline]
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pub fn tracefrac(&self) -> TRACEFRACR {
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let bits = {
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const MASK: bool = true;
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const OFFSET: u8 = 0;
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((self.bits >> OFFSET) & MASK as u32) != 0
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};
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TRACEFRACR { bits }
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}
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#[doc = "Bits 1:3 - Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it after setting TRACEDIV."]
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#[inline]
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pub fn tracediv(&self) -> TRACEDIVR {
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let bits = {
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const MASK: u8 = 7;
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const OFFSET: u8 = 1;
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((self.bits >> OFFSET) & MASK as u32) as u8
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};
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TRACEDIVR { bits }
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}
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#[doc = "Bit 28 - Debug Trace Divider control"]
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#[inline]
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pub fn tracediven(&self) -> TRACEDIVENR {
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TRACEDIVENR::_from({
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const MASK: bool = true;
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const OFFSET: u8 = 28;
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((self.bits >> OFFSET) & MASK as u32) != 0
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})
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}
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}
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impl W {
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#[doc = r" Reset value of the register"]
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#[inline]
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pub fn reset_value() -> W {
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W { bits: 268435456 }
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}
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#[doc = r" Writes raw bits to the register"]
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#[inline]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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self.bits = bits;
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self
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}
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#[doc = "Bit 0 - Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear TRACEDIVEN to disable the trace clock divide function."]
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#[inline]
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pub fn tracefrac(&mut self) -> _TRACEFRACW {
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_TRACEFRACW { w: self }
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}
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#[doc = "Bits 1:3 - Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it after setting TRACEDIV."]
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#[inline]
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pub fn tracediv(&mut self) -> _TRACEDIVW {
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_TRACEDIVW { w: self }
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}
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#[doc = "Bit 28 - Debug Trace Divider control"]
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#[inline]
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pub fn tracediven(&mut self) -> _TRACEDIVENW {
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_TRACEDIVENW { w: self }
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}
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}
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#[doc = "Reader of register CLKDIV4"]
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pub type R = crate::R<u32, super::CLKDIV4>;
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#[doc = "Writer for register CLKDIV4"]
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pub type W = crate::W<u32, super::CLKDIV4>;
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#[doc = "Register CLKDIV4 `reset()`'s with value 0x1000_0000"]
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impl crate::ResetValue for super::CLKDIV4 {
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type Type = u32;
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#[inline(always)]
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fn reset_value() -> Self::Type {
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0x1000_0000
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}
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}
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#[doc = "Reader of field `TRACEFRAC`"]
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pub type TRACEFRAC_R = crate::R<bool, bool>;
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#[doc = "Write proxy for field `TRACEFRAC`"]
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pub struct TRACEFRAC_W<'a> {
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w: &'a mut W,
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}
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impl<'a> TRACEFRAC_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
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self.w
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}
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}
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#[doc = "Reader of field `TRACEDIV`"]
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pub type TRACEDIV_R = crate::R<u8, u8>;
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#[doc = "Write proxy for field `TRACEDIV`"]
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pub struct TRACEDIV_W<'a> {
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w: &'a mut W,
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}
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impl<'a> TRACEDIV_W<'a> {
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x07 << 1)) | (((value as u32) & 0x07) << 1);
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self.w
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}
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}
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#[doc = "Debug Trace Divider control\n\nValue on reset: 1"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum TRACEDIVEN_A {
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#[doc = "0: Debug trace divider disabled"]
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_0 = 0,
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#[doc = "1: Debug trace divider enabled"]
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_1 = 1,
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}
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impl From<TRACEDIVEN_A> for bool {
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#[inline(always)]
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fn from(variant: TRACEDIVEN_A) -> Self {
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variant as u8 != 0
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}
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}
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#[doc = "Reader of field `TRACEDIVEN`"]
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pub type TRACEDIVEN_R = crate::R<bool, TRACEDIVEN_A>;
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impl TRACEDIVEN_R {
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#[doc = r"Get enumerated values variant"]
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#[inline(always)]
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pub fn variant(&self) -> TRACEDIVEN_A {
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match self.bits {
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false => TRACEDIVEN_A::_0,
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true => TRACEDIVEN_A::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline(always)]
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pub fn is_0(&self) -> bool {
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*self == TRACEDIVEN_A::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
|
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#[inline(always)]
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pub fn is_1(&self) -> bool {
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*self == TRACEDIVEN_A::_1
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}
|
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}
|
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#[doc = "Write proxy for field `TRACEDIVEN`"]
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pub struct TRACEDIVEN_W<'a> {
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w: &'a mut W,
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}
|
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impl<'a> TRACEDIVEN_W<'a> {
|
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#[doc = r"Writes `variant` to the field"]
|
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#[inline(always)]
|
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pub fn variant(self, variant: TRACEDIVEN_A) -> &'a mut W {
|
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{
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self.bit(variant.into())
|
||||
}
|
||||
}
|
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#[doc = "Debug trace divider disabled"]
|
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#[inline(always)]
|
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pub fn _0(self) -> &'a mut W {
|
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self.variant(TRACEDIVEN_A::_0)
|
||||
}
|
||||
#[doc = "Debug trace divider enabled"]
|
||||
#[inline(always)]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(TRACEDIVEN_A::_1)
|
||||
}
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear TRACEDIVEN to disable the trace clock divide function."]
|
||||
#[inline(always)]
|
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pub fn tracefrac(&self) -> TRACEFRAC_R {
|
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TRACEFRAC_R::new((self.bits & 0x01) != 0)
|
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}
|
||||
#[doc = "Bits 1:3 - Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it after setting TRACEDIV."]
|
||||
#[inline(always)]
|
||||
pub fn tracediv(&self) -> TRACEDIV_R {
|
||||
TRACEDIV_R::new(((self.bits >> 1) & 0x07) as u8)
|
||||
}
|
||||
#[doc = "Bit 28 - Debug Trace Divider control"]
|
||||
#[inline(always)]
|
||||
pub fn tracediven(&self) -> TRACEDIVEN_R {
|
||||
TRACEDIVEN_R::new(((self.bits >> 28) & 0x01) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear TRACEDIVEN to disable the trace clock divide function."]
|
||||
#[inline(always)]
|
||||
pub fn tracefrac(&mut self) -> TRACEFRAC_W {
|
||||
TRACEFRAC_W { w: self }
|
||||
}
|
||||
#[doc = "Bits 1:3 - Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it after setting TRACEDIV."]
|
||||
#[inline(always)]
|
||||
pub fn tracediv(&mut self) -> TRACEDIV_W {
|
||||
TRACEDIV_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 28 - Debug Trace Divider control"]
|
||||
#[inline(always)]
|
||||
pub fn tracediven(&mut self) -> TRACEDIVEN_W {
|
||||
TRACEDIVEN_W { w: self }
|
||||
}
|
||||
}
|
||||
|
||||
318
src/sim/fcfg1.rs
318
src/sim/fcfg1.rs
@ -1,196 +1,122 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::FCFG1 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct DEPARTR {
|
||||
bits: u8,
|
||||
}
|
||||
impl DEPARTR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `EEERAMSIZE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum EEERAMSIZER {
|
||||
#[doc = "4 KB"]
|
||||
_0010,
|
||||
#[doc = "2 KB"]
|
||||
_0011,
|
||||
#[doc = "1 KB"]
|
||||
_0100,
|
||||
#[doc = "512 Bytes"]
|
||||
_0101,
|
||||
#[doc = "256 Bytes"]
|
||||
_0110,
|
||||
#[doc = "128 Bytes"]
|
||||
_0111,
|
||||
#[doc = "64 Bytes"]
|
||||
_1000,
|
||||
#[doc = "32 Bytes"]
|
||||
_1001,
|
||||
#[doc = "0 Bytes"]
|
||||
_1111,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
}
|
||||
impl EEERAMSIZER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
EEERAMSIZER::_0010 => 2,
|
||||
EEERAMSIZER::_0011 => 3,
|
||||
EEERAMSIZER::_0100 => 4,
|
||||
EEERAMSIZER::_0101 => 5,
|
||||
EEERAMSIZER::_0110 => 6,
|
||||
EEERAMSIZER::_0111 => 7,
|
||||
EEERAMSIZER::_1000 => 8,
|
||||
EEERAMSIZER::_1001 => 9,
|
||||
EEERAMSIZER::_1111 => 15,
|
||||
EEERAMSIZER::_Reserved(bits) => bits,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> EEERAMSIZER {
|
||||
match value {
|
||||
2 => EEERAMSIZER::_0010,
|
||||
3 => EEERAMSIZER::_0011,
|
||||
4 => EEERAMSIZER::_0100,
|
||||
5 => EEERAMSIZER::_0101,
|
||||
6 => EEERAMSIZER::_0110,
|
||||
7 => EEERAMSIZER::_0111,
|
||||
8 => EEERAMSIZER::_1000,
|
||||
9 => EEERAMSIZER::_1001,
|
||||
15 => EEERAMSIZER::_1111,
|
||||
i => EEERAMSIZER::_Reserved(i),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0010`"]
|
||||
#[inline]
|
||||
pub fn is_0010(&self) -> bool {
|
||||
*self == EEERAMSIZER::_0010
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0011`"]
|
||||
#[inline]
|
||||
pub fn is_0011(&self) -> bool {
|
||||
*self == EEERAMSIZER::_0011
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0100`"]
|
||||
#[inline]
|
||||
pub fn is_0100(&self) -> bool {
|
||||
*self == EEERAMSIZER::_0100
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0101`"]
|
||||
#[inline]
|
||||
pub fn is_0101(&self) -> bool {
|
||||
*self == EEERAMSIZER::_0101
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0110`"]
|
||||
#[inline]
|
||||
pub fn is_0110(&self) -> bool {
|
||||
*self == EEERAMSIZER::_0110
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0111`"]
|
||||
#[inline]
|
||||
pub fn is_0111(&self) -> bool {
|
||||
*self == EEERAMSIZER::_0111
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1000`"]
|
||||
#[inline]
|
||||
pub fn is_1000(&self) -> bool {
|
||||
*self == EEERAMSIZER::_1000
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1001`"]
|
||||
#[inline]
|
||||
pub fn is_1001(&self) -> bool {
|
||||
*self == EEERAMSIZER::_1001
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1111`"]
|
||||
#[inline]
|
||||
pub fn is_1111(&self) -> bool {
|
||||
*self == EEERAMSIZER::_1111
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 12:15 - FlexNVM partition"]
|
||||
#[inline]
|
||||
pub fn depart(&self) -> DEPARTR {
|
||||
let bits = {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 12;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
DEPARTR { bits }
|
||||
}
|
||||
#[doc = "Bits 16:19 - EEE SRAM SIZE"]
|
||||
#[inline]
|
||||
pub fn eeeramsize(&self) -> EEERAMSIZER {
|
||||
EEERAMSIZER::_from({
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 16;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register FCFG1"]
|
||||
pub type R = crate::R<u32, super::FCFG1>;
|
||||
#[doc = "Writer for register FCFG1"]
|
||||
pub type W = crate::W<u32, super::FCFG1>;
|
||||
#[doc = "Register FCFG1 `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::FCFG1 {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `DEPART`"]
|
||||
pub type DEPART_R = crate::R<u8, u8>;
|
||||
#[doc = "EEE SRAM SIZE\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
#[repr(u8)]
|
||||
pub enum EEERAMSIZE_A {
|
||||
#[doc = "2: 4 KB"]
|
||||
_0010 = 2,
|
||||
#[doc = "3: 2 KB"]
|
||||
_0011 = 3,
|
||||
#[doc = "4: 1 KB"]
|
||||
_0100 = 4,
|
||||
#[doc = "5: 512 Bytes"]
|
||||
_0101 = 5,
|
||||
#[doc = "6: 256 Bytes"]
|
||||
_0110 = 6,
|
||||
#[doc = "7: 128 Bytes"]
|
||||
_0111 = 7,
|
||||
#[doc = "8: 64 Bytes"]
|
||||
_1000 = 8,
|
||||
#[doc = "9: 32 Bytes"]
|
||||
_1001 = 9,
|
||||
#[doc = "15: 0 Bytes"]
|
||||
_1111 = 15,
|
||||
}
|
||||
impl From<EEERAMSIZE_A> for u8 {
|
||||
#[inline(always)]
|
||||
fn from(variant: EEERAMSIZE_A) -> Self {
|
||||
variant as _
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `EEERAMSIZE`"]
|
||||
pub type EEERAMSIZE_R = crate::R<u8, EEERAMSIZE_A>;
|
||||
impl EEERAMSIZE_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> crate::Variant<u8, EEERAMSIZE_A> {
|
||||
use crate::Variant::*;
|
||||
match self.bits {
|
||||
2 => Val(EEERAMSIZE_A::_0010),
|
||||
3 => Val(EEERAMSIZE_A::_0011),
|
||||
4 => Val(EEERAMSIZE_A::_0100),
|
||||
5 => Val(EEERAMSIZE_A::_0101),
|
||||
6 => Val(EEERAMSIZE_A::_0110),
|
||||
7 => Val(EEERAMSIZE_A::_0111),
|
||||
8 => Val(EEERAMSIZE_A::_1000),
|
||||
9 => Val(EEERAMSIZE_A::_1001),
|
||||
15 => Val(EEERAMSIZE_A::_1111),
|
||||
i => Res(i),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0010`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0010(&self) -> bool {
|
||||
*self == EEERAMSIZE_A::_0010
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0011`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0011(&self) -> bool {
|
||||
*self == EEERAMSIZE_A::_0011
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0100`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0100(&self) -> bool {
|
||||
*self == EEERAMSIZE_A::_0100
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0101`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0101(&self) -> bool {
|
||||
*self == EEERAMSIZE_A::_0101
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0110`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0110(&self) -> bool {
|
||||
*self == EEERAMSIZE_A::_0110
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0111`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0111(&self) -> bool {
|
||||
*self == EEERAMSIZE_A::_0111
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1000`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1000(&self) -> bool {
|
||||
*self == EEERAMSIZE_A::_1000
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1001`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1001(&self) -> bool {
|
||||
*self == EEERAMSIZE_A::_1001
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1111`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1111(&self) -> bool {
|
||||
*self == EEERAMSIZE_A::_1111
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 12:15 - FlexNVM partition"]
|
||||
#[inline(always)]
|
||||
pub fn depart(&self) -> DEPART_R {
|
||||
DEPART_R::new(((self.bits >> 12) & 0x0f) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:19 - EEE SRAM SIZE"]
|
||||
#[inline(always)]
|
||||
pub fn eeeramsize(&self) -> EEERAMSIZE_R {
|
||||
EEERAMSIZE_R::new(((self.bits >> 16) & 0x0f) as u8)
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
|
||||
1750
src/sim/ftmopt0.rs
1750
src/sim/ftmopt0.rs
File diff suppressed because it is too large
Load Diff
1574
src/sim/ftmopt1.rs
1574
src/sim/ftmopt1.rs
File diff suppressed because it is too large
Load Diff
@ -1,572 +1,392 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::LPOCLKS {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `LPO1KCLKEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum LPO1KCLKENR {
|
||||
#[doc = "Disable 1 kHz LPO_CLK output"]
|
||||
_0,
|
||||
#[doc = "Enable 1 kHz LPO_CLK output"]
|
||||
_1,
|
||||
}
|
||||
impl LPO1KCLKENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
#[inline]
|
||||
pub fn bit_is_clear(&self) -> bool {
|
||||
!self.bit()
|
||||
}
|
||||
#[doc = r" Returns `true` if the bit is set (1)"]
|
||||
#[inline]
|
||||
pub fn bit_is_set(&self) -> bool {
|
||||
self.bit()
|
||||
}
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bit(&self) -> bool {
|
||||
match *self {
|
||||
LPO1KCLKENR::_0 => false,
|
||||
LPO1KCLKENR::_1 => true,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: bool) -> LPO1KCLKENR {
|
||||
match value {
|
||||
false => LPO1KCLKENR::_0,
|
||||
true => LPO1KCLKENR::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == LPO1KCLKENR::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == LPO1KCLKENR::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `LPO32KCLKEN`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum LPO32KCLKENR {
|
||||
#[doc = "Disable 32 kHz LPO_CLK output"]
|
||||
_0,
|
||||
#[doc = "Enable 32 kHz LPO_CLK output"]
|
||||
_1,
|
||||
}
|
||||
impl LPO32KCLKENR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
#[inline]
|
||||
pub fn bit_is_clear(&self) -> bool {
|
||||
!self.bit()
|
||||
}
|
||||
#[doc = r" Returns `true` if the bit is set (1)"]
|
||||
#[inline]
|
||||
pub fn bit_is_set(&self) -> bool {
|
||||
self.bit()
|
||||
}
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bit(&self) -> bool {
|
||||
match *self {
|
||||
LPO32KCLKENR::_0 => false,
|
||||
LPO32KCLKENR::_1 => true,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: bool) -> LPO32KCLKENR {
|
||||
match value {
|
||||
false => LPO32KCLKENR::_0,
|
||||
true => LPO32KCLKENR::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == LPO32KCLKENR::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == LPO32KCLKENR::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `LPOCLKSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum LPOCLKSELR {
|
||||
#[doc = "128 kHz LPO_CLK"]
|
||||
_00,
|
||||
#[doc = "No clock"]
|
||||
_01,
|
||||
#[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
_10,
|
||||
#[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
_11,
|
||||
}
|
||||
impl LPOCLKSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
LPOCLKSELR::_00 => 0,
|
||||
LPOCLKSELR::_01 => 1,
|
||||
LPOCLKSELR::_10 => 2,
|
||||
LPOCLKSELR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> LPOCLKSELR {
|
||||
match value {
|
||||
0 => LPOCLKSELR::_00,
|
||||
1 => LPOCLKSELR::_01,
|
||||
2 => LPOCLKSELR::_10,
|
||||
3 => LPOCLKSELR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == LPOCLKSELR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == LPOCLKSELR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == LPOCLKSELR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == LPOCLKSELR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `RTCCLKSEL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum RTCCLKSELR {
|
||||
#[doc = "SOSCDIV1_CLK"]
|
||||
_00,
|
||||
#[doc = "32 kHz LPO_CLK"]
|
||||
_01,
|
||||
#[doc = "RTC_CLKIN clock"]
|
||||
_10,
|
||||
#[doc = "FIRCDIV1_CLK"]
|
||||
_11,
|
||||
}
|
||||
impl RTCCLKSELR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
RTCCLKSELR::_00 => 0,
|
||||
RTCCLKSELR::_01 => 1,
|
||||
RTCCLKSELR::_10 => 2,
|
||||
RTCCLKSELR::_11 => 3,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> RTCCLKSELR {
|
||||
match value {
|
||||
0 => RTCCLKSELR::_00,
|
||||
1 => RTCCLKSELR::_01,
|
||||
2 => RTCCLKSELR::_10,
|
||||
3 => RTCCLKSELR::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == RTCCLKSELR::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == RTCCLKSELR::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == RTCCLKSELR::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == RTCCLKSELR::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `LPO1KCLKEN`"]
|
||||
pub enum LPO1KCLKENW {
|
||||
#[doc = "Disable 1 kHz LPO_CLK output"]
|
||||
_0,
|
||||
#[doc = "Enable 1 kHz LPO_CLK output"]
|
||||
_1,
|
||||
}
|
||||
impl LPO1KCLKENW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
LPO1KCLKENW::_0 => false,
|
||||
LPO1KCLKENW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _LPO1KCLKENW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _LPO1KCLKENW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: LPO1KCLKENW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Disable 1 kHz LPO_CLK output"]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(LPO1KCLKENW::_0)
|
||||
}
|
||||
#[doc = "Enable 1 kHz LPO_CLK output"]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(LPO1KCLKENW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `LPO32KCLKEN`"]
|
||||
pub enum LPO32KCLKENW {
|
||||
#[doc = "Disable 32 kHz LPO_CLK output"]
|
||||
_0,
|
||||
#[doc = "Enable 32 kHz LPO_CLK output"]
|
||||
_1,
|
||||
}
|
||||
impl LPO32KCLKENW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
LPO32KCLKENW::_0 => false,
|
||||
LPO32KCLKENW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _LPO32KCLKENW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _LPO32KCLKENW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: LPO32KCLKENW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Disable 32 kHz LPO_CLK output"]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(LPO32KCLKENW::_0)
|
||||
}
|
||||
#[doc = "Enable 32 kHz LPO_CLK output"]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(LPO32KCLKENW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 1;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `LPOCLKSEL`"]
|
||||
pub enum LPOCLKSELW {
|
||||
#[doc = "128 kHz LPO_CLK"]
|
||||
_00,
|
||||
#[doc = "No clock"]
|
||||
_01,
|
||||
#[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
_10,
|
||||
#[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
_11,
|
||||
}
|
||||
impl LPOCLKSELW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
LPOCLKSELW::_00 => 0,
|
||||
LPOCLKSELW::_01 => 1,
|
||||
LPOCLKSELW::_10 => 2,
|
||||
LPOCLKSELW::_11 => 3,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _LPOCLKSELW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _LPOCLKSELW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: LPOCLKSELW) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "128 kHz LPO_CLK"]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(LPOCLKSELW::_00)
|
||||
}
|
||||
#[doc = "No clock"]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(LPOCLKSELW::_01)
|
||||
}
|
||||
#[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(LPOCLKSELW::_10)
|
||||
}
|
||||
#[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
#[inline]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(LPOCLKSELW::_11)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 2;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `RTCCLKSEL`"]
|
||||
pub enum RTCCLKSELW {
|
||||
#[doc = "SOSCDIV1_CLK"]
|
||||
_00,
|
||||
#[doc = "32 kHz LPO_CLK"]
|
||||
_01,
|
||||
#[doc = "RTC_CLKIN clock"]
|
||||
_10,
|
||||
#[doc = "FIRCDIV1_CLK"]
|
||||
_11,
|
||||
}
|
||||
impl RTCCLKSELW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> u8 {
|
||||
match *self {
|
||||
RTCCLKSELW::_00 => 0,
|
||||
RTCCLKSELW::_01 => 1,
|
||||
RTCCLKSELW::_10 => 2,
|
||||
RTCCLKSELW::_11 => 3,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _RTCCLKSELW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _RTCCLKSELW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: RTCCLKSELW) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "SOSCDIV1_CLK"]
|
||||
#[inline]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(RTCCLKSELW::_00)
|
||||
}
|
||||
#[doc = "32 kHz LPO_CLK"]
|
||||
#[inline]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(RTCCLKSELW::_01)
|
||||
}
|
||||
#[doc = "RTC_CLKIN clock"]
|
||||
#[inline]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(RTCCLKSELW::_10)
|
||||
}
|
||||
#[doc = "FIRCDIV1_CLK"]
|
||||
#[inline]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(RTCCLKSELW::_11)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 4;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bit 0 - 1 kHz LPO_CLK enable"]
|
||||
#[inline]
|
||||
pub fn lpo1kclken(&self) -> LPO1KCLKENR {
|
||||
LPO1KCLKENR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 1 - 32 kHz LPO_CLK enable"]
|
||||
#[inline]
|
||||
pub fn lpo32kclken(&self) -> LPO32KCLKENR {
|
||||
LPO32KCLKENR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 1;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bits 2:3 - LPO clock source select"]
|
||||
#[inline]
|
||||
pub fn lpoclksel(&self) -> LPOCLKSELR {
|
||||
LPOCLKSELR::_from({
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 2;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
#[doc = "Bits 4:5 - 32 kHz clock source select"]
|
||||
#[inline]
|
||||
pub fn rtcclksel(&self) -> RTCCLKSELR {
|
||||
RTCCLKSELR::_from({
|
||||
const MASK: u8 = 3;
|
||||
const OFFSET: u8 = 4;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 3 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bit 0 - 1 kHz LPO_CLK enable"]
|
||||
#[inline]
|
||||
pub fn lpo1kclken(&mut self) -> _LPO1KCLKENW {
|
||||
_LPO1KCLKENW { w: self }
|
||||
}
|
||||
#[doc = "Bit 1 - 32 kHz LPO_CLK enable"]
|
||||
#[inline]
|
||||
pub fn lpo32kclken(&mut self) -> _LPO32KCLKENW {
|
||||
_LPO32KCLKENW { w: self }
|
||||
}
|
||||
#[doc = "Bits 2:3 - LPO clock source select"]
|
||||
#[inline]
|
||||
pub fn lpoclksel(&mut self) -> _LPOCLKSELW {
|
||||
_LPOCLKSELW { w: self }
|
||||
}
|
||||
#[doc = "Bits 4:5 - 32 kHz clock source select"]
|
||||
#[inline]
|
||||
pub fn rtcclksel(&mut self) -> _RTCCLKSELW {
|
||||
_RTCCLKSELW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register LPOCLKS"]
|
||||
pub type R = crate::R<u32, super::LPOCLKS>;
|
||||
#[doc = "Writer for register LPOCLKS"]
|
||||
pub type W = crate::W<u32, super::LPOCLKS>;
|
||||
#[doc = "Register LPOCLKS `reset()`'s with value 0x03"]
|
||||
impl crate::ResetValue for super::LPOCLKS {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0x03
|
||||
}
|
||||
}
|
||||
#[doc = "1 kHz LPO_CLK enable\n\nValue on reset: 1"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum LPO1KCLKEN_A {
|
||||
#[doc = "0: Disable 1 kHz LPO_CLK output"]
|
||||
_0 = 0,
|
||||
#[doc = "1: Enable 1 kHz LPO_CLK output"]
|
||||
_1 = 1,
|
||||
}
|
||||
impl From<LPO1KCLKEN_A> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: LPO1KCLKEN_A) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `LPO1KCLKEN`"]
|
||||
pub type LPO1KCLKEN_R = crate::R<bool, LPO1KCLKEN_A>;
|
||||
impl LPO1KCLKEN_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> LPO1KCLKEN_A {
|
||||
match self.bits {
|
||||
false => LPO1KCLKEN_A::_0,
|
||||
true => LPO1KCLKEN_A::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == LPO1KCLKEN_A::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == LPO1KCLKEN_A::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `LPO1KCLKEN`"]
|
||||
pub struct LPO1KCLKEN_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> LPO1KCLKEN_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: LPO1KCLKEN_A) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "Disable 1 kHz LPO_CLK output"]
|
||||
#[inline(always)]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(LPO1KCLKEN_A::_0)
|
||||
}
|
||||
#[doc = "Enable 1 kHz LPO_CLK output"]
|
||||
#[inline(always)]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(LPO1KCLKEN_A::_1)
|
||||
}
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "32 kHz LPO_CLK enable\n\nValue on reset: 1"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum LPO32KCLKEN_A {
|
||||
#[doc = "0: Disable 32 kHz LPO_CLK output"]
|
||||
_0 = 0,
|
||||
#[doc = "1: Enable 32 kHz LPO_CLK output"]
|
||||
_1 = 1,
|
||||
}
|
||||
impl From<LPO32KCLKEN_A> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: LPO32KCLKEN_A) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `LPO32KCLKEN`"]
|
||||
pub type LPO32KCLKEN_R = crate::R<bool, LPO32KCLKEN_A>;
|
||||
impl LPO32KCLKEN_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> LPO32KCLKEN_A {
|
||||
match self.bits {
|
||||
false => LPO32KCLKEN_A::_0,
|
||||
true => LPO32KCLKEN_A::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == LPO32KCLKEN_A::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == LPO32KCLKEN_A::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `LPO32KCLKEN`"]
|
||||
pub struct LPO32KCLKEN_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> LPO32KCLKEN_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: LPO32KCLKEN_A) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "Disable 32 kHz LPO_CLK output"]
|
||||
#[inline(always)]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(LPO32KCLKEN_A::_0)
|
||||
}
|
||||
#[doc = "Enable 32 kHz LPO_CLK output"]
|
||||
#[inline(always)]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(LPO32KCLKEN_A::_1)
|
||||
}
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "LPO clock source select\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
#[repr(u8)]
|
||||
pub enum LPOCLKSEL_A {
|
||||
#[doc = "0: 128 kHz LPO_CLK"]
|
||||
_00 = 0,
|
||||
#[doc = "1: No clock"]
|
||||
_01 = 1,
|
||||
#[doc = "2: 32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
_10 = 2,
|
||||
#[doc = "3: 1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
_11 = 3,
|
||||
}
|
||||
impl From<LPOCLKSEL_A> for u8 {
|
||||
#[inline(always)]
|
||||
fn from(variant: LPOCLKSEL_A) -> Self {
|
||||
variant as _
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `LPOCLKSEL`"]
|
||||
pub type LPOCLKSEL_R = crate::R<u8, LPOCLKSEL_A>;
|
||||
impl LPOCLKSEL_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> LPOCLKSEL_A {
|
||||
match self.bits {
|
||||
0 => LPOCLKSEL_A::_00,
|
||||
1 => LPOCLKSEL_A::_01,
|
||||
2 => LPOCLKSEL_A::_10,
|
||||
3 => LPOCLKSEL_A::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline(always)]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == LPOCLKSEL_A::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline(always)]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == LPOCLKSEL_A::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline(always)]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == LPOCLKSEL_A::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline(always)]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == LPOCLKSEL_A::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `LPOCLKSEL`"]
|
||||
pub struct LPOCLKSEL_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> LPOCLKSEL_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: LPOCLKSEL_A) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "128 kHz LPO_CLK"]
|
||||
#[inline(always)]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(LPOCLKSEL_A::_00)
|
||||
}
|
||||
#[doc = "No clock"]
|
||||
#[inline(always)]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(LPOCLKSEL_A::_01)
|
||||
}
|
||||
#[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
#[inline(always)]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(LPOCLKSEL_A::_10)
|
||||
}
|
||||
#[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
|
||||
#[inline(always)]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(LPOCLKSEL_A::_11)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "32 kHz clock source select\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
#[repr(u8)]
|
||||
pub enum RTCCLKSEL_A {
|
||||
#[doc = "0: SOSCDIV1_CLK"]
|
||||
_00 = 0,
|
||||
#[doc = "1: 32 kHz LPO_CLK"]
|
||||
_01 = 1,
|
||||
#[doc = "2: RTC_CLKIN clock"]
|
||||
_10 = 2,
|
||||
#[doc = "3: FIRCDIV1_CLK"]
|
||||
_11 = 3,
|
||||
}
|
||||
impl From<RTCCLKSEL_A> for u8 {
|
||||
#[inline(always)]
|
||||
fn from(variant: RTCCLKSEL_A) -> Self {
|
||||
variant as _
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `RTCCLKSEL`"]
|
||||
pub type RTCCLKSEL_R = crate::R<u8, RTCCLKSEL_A>;
|
||||
impl RTCCLKSEL_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> RTCCLKSEL_A {
|
||||
match self.bits {
|
||||
0 => RTCCLKSEL_A::_00,
|
||||
1 => RTCCLKSEL_A::_01,
|
||||
2 => RTCCLKSEL_A::_10,
|
||||
3 => RTCCLKSEL_A::_11,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_00`"]
|
||||
#[inline(always)]
|
||||
pub fn is_00(&self) -> bool {
|
||||
*self == RTCCLKSEL_A::_00
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_01`"]
|
||||
#[inline(always)]
|
||||
pub fn is_01(&self) -> bool {
|
||||
*self == RTCCLKSEL_A::_01
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_10`"]
|
||||
#[inline(always)]
|
||||
pub fn is_10(&self) -> bool {
|
||||
*self == RTCCLKSEL_A::_10
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_11`"]
|
||||
#[inline(always)]
|
||||
pub fn is_11(&self) -> bool {
|
||||
*self == RTCCLKSEL_A::_11
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `RTCCLKSEL`"]
|
||||
pub struct RTCCLKSEL_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> RTCCLKSEL_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: RTCCLKSEL_A) -> &'a mut W {
|
||||
{
|
||||
self.bits(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "SOSCDIV1_CLK"]
|
||||
#[inline(always)]
|
||||
pub fn _00(self) -> &'a mut W {
|
||||
self.variant(RTCCLKSEL_A::_00)
|
||||
}
|
||||
#[doc = "32 kHz LPO_CLK"]
|
||||
#[inline(always)]
|
||||
pub fn _01(self) -> &'a mut W {
|
||||
self.variant(RTCCLKSEL_A::_01)
|
||||
}
|
||||
#[doc = "RTC_CLKIN clock"]
|
||||
#[inline(always)]
|
||||
pub fn _10(self) -> &'a mut W {
|
||||
self.variant(RTCCLKSEL_A::_10)
|
||||
}
|
||||
#[doc = "FIRCDIV1_CLK"]
|
||||
#[inline(always)]
|
||||
pub fn _11(self) -> &'a mut W {
|
||||
self.variant(RTCCLKSEL_A::_11)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bit 0 - 1 kHz LPO_CLK enable"]
|
||||
#[inline(always)]
|
||||
pub fn lpo1kclken(&self) -> LPO1KCLKEN_R {
|
||||
LPO1KCLKEN_R::new((self.bits & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - 32 kHz LPO_CLK enable"]
|
||||
#[inline(always)]
|
||||
pub fn lpo32kclken(&self) -> LPO32KCLKEN_R {
|
||||
LPO32KCLKEN_R::new(((self.bits >> 1) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bits 2:3 - LPO clock source select"]
|
||||
#[inline(always)]
|
||||
pub fn lpoclksel(&self) -> LPOCLKSEL_R {
|
||||
LPOCLKSEL_R::new(((self.bits >> 2) & 0x03) as u8)
|
||||
}
|
||||
#[doc = "Bits 4:5 - 32 kHz clock source select"]
|
||||
#[inline(always)]
|
||||
pub fn rtcclksel(&self) -> RTCCLKSEL_R {
|
||||
RTCCLKSEL_R::new(((self.bits >> 4) & 0x03) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - 1 kHz LPO_CLK enable"]
|
||||
#[inline(always)]
|
||||
pub fn lpo1kclken(&mut self) -> LPO1KCLKEN_W {
|
||||
LPO1KCLKEN_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 1 - 32 kHz LPO_CLK enable"]
|
||||
#[inline(always)]
|
||||
pub fn lpo32kclken(&mut self) -> LPO32KCLKEN_W {
|
||||
LPO32KCLKEN_W { w: self }
|
||||
}
|
||||
#[doc = "Bits 2:3 - LPO clock source select"]
|
||||
#[inline(always)]
|
||||
pub fn lpoclksel(&mut self) -> LPOCLKSEL_W {
|
||||
LPOCLKSEL_W { w: self }
|
||||
}
|
||||
#[doc = "Bits 4:5 - 32 kHz clock source select"]
|
||||
#[inline(always)]
|
||||
pub fn rtcclksel(&mut self) -> RTCCLKSEL_W {
|
||||
RTCCLKSEL_W { w: self }
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,538 +1,372 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::MISCTRL0 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
#[doc = "Reader of register MISCTRL0"]
|
||||
pub type R = crate::R<u32, super::MISCTRL0>;
|
||||
#[doc = "Writer for register MISCTRL0"]
|
||||
pub type W = crate::W<u32, super::MISCTRL0>;
|
||||
#[doc = "Register MISCTRL0 `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::MISCTRL0 {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `FTM0_OBE_CTRL`"]
|
||||
#[doc = "FTM0 OBE CTRL bit\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM0_OBE_CTRLR {
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
|
||||
_0,
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
_1,
|
||||
pub enum FTM0_OBE_CTRL_A {
|
||||
#[doc = "0: The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
|
||||
= 1'b1). Otherwise the channel output is tristated."]
|
||||
_0 = 0,
|
||||
#[doc = "1: The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
|
||||
or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
_1 = 1,
|
||||
}
|
||||
impl FTM0_OBE_CTRLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
#[inline]
|
||||
pub fn bit_is_clear(&self) -> bool {
|
||||
!self.bit()
|
||||
impl From<FTM0_OBE_CTRL_A> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: FTM0_OBE_CTRL_A) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
#[doc = r" Returns `true` if the bit is set (1)"]
|
||||
#[inline]
|
||||
pub fn bit_is_set(&self) -> bool {
|
||||
self.bit()
|
||||
}
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bit(&self) -> bool {
|
||||
match *self {
|
||||
FTM0_OBE_CTRLR::_0 => false,
|
||||
FTM0_OBE_CTRLR::_1 => true,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: bool) -> FTM0_OBE_CTRLR {
|
||||
match value {
|
||||
false => FTM0_OBE_CTRLR::_0,
|
||||
true => FTM0_OBE_CTRLR::_1,
|
||||
}
|
||||
#[doc = "Reader of field `FTM0_OBE_CTRL`"]
|
||||
pub type FTM0_OBE_CTRL_R = crate::R<bool, FTM0_OBE_CTRL_A>;
|
||||
impl FTM0_OBE_CTRL_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> FTM0_OBE_CTRL_A {
|
||||
match self.bits {
|
||||
false => FTM0_OBE_CTRL_A::_0,
|
||||
true => FTM0_OBE_CTRL_A::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline]
|
||||
#[inline(always)]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == FTM0_OBE_CTRLR::_0
|
||||
*self == FTM0_OBE_CTRL_A::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline]
|
||||
#[inline(always)]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == FTM0_OBE_CTRLR::_1
|
||||
*self == FTM0_OBE_CTRL_A::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `FTM1_OBE_CTRL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM1_OBE_CTRLR {
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
|
||||
_0,
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
_1,
|
||||
}
|
||||
impl FTM1_OBE_CTRLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
#[inline]
|
||||
pub fn bit_is_clear(&self) -> bool {
|
||||
!self.bit()
|
||||
}
|
||||
#[doc = r" Returns `true` if the bit is set (1)"]
|
||||
#[inline]
|
||||
pub fn bit_is_set(&self) -> bool {
|
||||
self.bit()
|
||||
}
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bit(&self) -> bool {
|
||||
match *self {
|
||||
FTM1_OBE_CTRLR::_0 => false,
|
||||
FTM1_OBE_CTRLR::_1 => true,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: bool) -> FTM1_OBE_CTRLR {
|
||||
match value {
|
||||
false => FTM1_OBE_CTRLR::_0,
|
||||
true => FTM1_OBE_CTRLR::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == FTM1_OBE_CTRLR::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == FTM1_OBE_CTRLR::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `FTM2_OBE_CTRL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM2_OBE_CTRLR {
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
|
||||
_0,
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
_1,
|
||||
}
|
||||
impl FTM2_OBE_CTRLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
#[inline]
|
||||
pub fn bit_is_clear(&self) -> bool {
|
||||
!self.bit()
|
||||
}
|
||||
#[doc = r" Returns `true` if the bit is set (1)"]
|
||||
#[inline]
|
||||
pub fn bit_is_set(&self) -> bool {
|
||||
self.bit()
|
||||
}
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bit(&self) -> bool {
|
||||
match *self {
|
||||
FTM2_OBE_CTRLR::_0 => false,
|
||||
FTM2_OBE_CTRLR::_1 => true,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: bool) -> FTM2_OBE_CTRLR {
|
||||
match value {
|
||||
false => FTM2_OBE_CTRLR::_0,
|
||||
true => FTM2_OBE_CTRLR::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == FTM2_OBE_CTRLR::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == FTM2_OBE_CTRLR::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `FTM3_OBE_CTRL`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM3_OBE_CTRLR {
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
|
||||
_0,
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
_1,
|
||||
}
|
||||
impl FTM3_OBE_CTRLR {
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
#[inline]
|
||||
pub fn bit_is_clear(&self) -> bool {
|
||||
!self.bit()
|
||||
}
|
||||
#[doc = r" Returns `true` if the bit is set (1)"]
|
||||
#[inline]
|
||||
pub fn bit_is_set(&self) -> bool {
|
||||
self.bit()
|
||||
}
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bit(&self) -> bool {
|
||||
match *self {
|
||||
FTM3_OBE_CTRLR::_0 => false,
|
||||
FTM3_OBE_CTRLR::_1 => true,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: bool) -> FTM3_OBE_CTRLR {
|
||||
match value {
|
||||
false => FTM3_OBE_CTRLR::_0,
|
||||
true => FTM3_OBE_CTRLR::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == FTM3_OBE_CTRLR::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == FTM3_OBE_CTRLR::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM0_OBE_CTRL`"]
|
||||
pub enum FTM0_OBE_CTRLW {
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
|
||||
_0,
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
_1,
|
||||
}
|
||||
impl FTM0_OBE_CTRLW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
FTM0_OBE_CTRLW::_0 => false,
|
||||
FTM0_OBE_CTRLW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _FTM0_OBE_CTRLW<'a> {
|
||||
#[doc = "Write proxy for field `FTM0_OBE_CTRL`"]
|
||||
pub struct FTM0_OBE_CTRL_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _FTM0_OBE_CTRLW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: FTM0_OBE_CTRLW) -> &'a mut W {
|
||||
impl<'a> FTM0_OBE_CTRL_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: FTM0_OBE_CTRL_A) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
self.bit(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
|
||||
#[inline]
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
|
||||
= 1'b1). Otherwise the channel output is tristated."]
|
||||
#[inline(always)]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(FTM0_OBE_CTRLW::_0)
|
||||
self.variant(FTM0_OBE_CTRL_A::_0)
|
||||
}
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
#[inline]
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
|
||||
or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
#[inline(always)]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(FTM0_OBE_CTRLW::_1)
|
||||
self.variant(FTM0_OBE_CTRL_A::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 16;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM1_OBE_CTRL`"]
|
||||
pub enum FTM1_OBE_CTRLW {
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
|
||||
_0,
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
_1,
|
||||
#[doc = "FTM1 OBE CTRL bit\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM1_OBE_CTRL_A {
|
||||
#[doc = "0: The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
|
||||
= 1'b1). Otherwise the channel output is tristated."]
|
||||
_0 = 0,
|
||||
#[doc = "1: The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
|
||||
or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
_1 = 1,
|
||||
}
|
||||
impl FTM1_OBE_CTRLW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
FTM1_OBE_CTRLW::_0 => false,
|
||||
FTM1_OBE_CTRLW::_1 => true,
|
||||
}
|
||||
impl From<FTM1_OBE_CTRL_A> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: FTM1_OBE_CTRL_A) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _FTM1_OBE_CTRLW<'a> {
|
||||
#[doc = "Reader of field `FTM1_OBE_CTRL`"]
|
||||
pub type FTM1_OBE_CTRL_R = crate::R<bool, FTM1_OBE_CTRL_A>;
|
||||
impl FTM1_OBE_CTRL_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> FTM1_OBE_CTRL_A {
|
||||
match self.bits {
|
||||
false => FTM1_OBE_CTRL_A::_0,
|
||||
true => FTM1_OBE_CTRL_A::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == FTM1_OBE_CTRL_A::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == FTM1_OBE_CTRL_A::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `FTM1_OBE_CTRL`"]
|
||||
pub struct FTM1_OBE_CTRL_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _FTM1_OBE_CTRLW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: FTM1_OBE_CTRLW) -> &'a mut W {
|
||||
impl<'a> FTM1_OBE_CTRL_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: FTM1_OBE_CTRL_A) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
self.bit(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
|
||||
#[inline]
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
|
||||
= 1'b1). Otherwise the channel output is tristated."]
|
||||
#[inline(always)]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(FTM1_OBE_CTRLW::_0)
|
||||
self.variant(FTM1_OBE_CTRL_A::_0)
|
||||
}
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
#[inline]
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
|
||||
or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
#[inline(always)]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(FTM1_OBE_CTRLW::_1)
|
||||
self.variant(FTM1_OBE_CTRL_A::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 17;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM2_OBE_CTRL`"]
|
||||
pub enum FTM2_OBE_CTRLW {
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
|
||||
_0,
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
_1,
|
||||
#[doc = "FTM2 OBE CTRL bit\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM2_OBE_CTRL_A {
|
||||
#[doc = "0: The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
|
||||
= 1'b1). Otherwise the channel output is tristated."]
|
||||
_0 = 0,
|
||||
#[doc = "1: The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
|
||||
or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
_1 = 1,
|
||||
}
|
||||
impl FTM2_OBE_CTRLW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
FTM2_OBE_CTRLW::_0 => false,
|
||||
FTM2_OBE_CTRLW::_1 => true,
|
||||
}
|
||||
impl From<FTM2_OBE_CTRL_A> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: FTM2_OBE_CTRL_A) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _FTM2_OBE_CTRLW<'a> {
|
||||
#[doc = "Reader of field `FTM2_OBE_CTRL`"]
|
||||
pub type FTM2_OBE_CTRL_R = crate::R<bool, FTM2_OBE_CTRL_A>;
|
||||
impl FTM2_OBE_CTRL_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> FTM2_OBE_CTRL_A {
|
||||
match self.bits {
|
||||
false => FTM2_OBE_CTRL_A::_0,
|
||||
true => FTM2_OBE_CTRL_A::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == FTM2_OBE_CTRL_A::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == FTM2_OBE_CTRL_A::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `FTM2_OBE_CTRL`"]
|
||||
pub struct FTM2_OBE_CTRL_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _FTM2_OBE_CTRLW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: FTM2_OBE_CTRLW) -> &'a mut W {
|
||||
impl<'a> FTM2_OBE_CTRL_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: FTM2_OBE_CTRL_A) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
self.bit(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
|
||||
#[inline]
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
|
||||
= 1'b1). Otherwise the channel output is tristated."]
|
||||
#[inline(always)]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(FTM2_OBE_CTRLW::_0)
|
||||
self.variant(FTM2_OBE_CTRL_A::_0)
|
||||
}
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
#[inline]
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
|
||||
or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
#[inline(always)]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(FTM2_OBE_CTRLW::_1)
|
||||
self.variant(FTM2_OBE_CTRL_A::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 18;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `FTM3_OBE_CTRL`"]
|
||||
pub enum FTM3_OBE_CTRLW {
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
|
||||
_0,
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
_1,
|
||||
#[doc = "FTM3 OBE CTRL bit\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum FTM3_OBE_CTRL_A {
|
||||
#[doc = "0: The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
|
||||
= 1'b1). Otherwise the channel output is tristated."]
|
||||
_0 = 0,
|
||||
#[doc = "1: The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
|
||||
or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
_1 = 1,
|
||||
}
|
||||
impl FTM3_OBE_CTRLW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
FTM3_OBE_CTRLW::_0 => false,
|
||||
FTM3_OBE_CTRLW::_1 => true,
|
||||
}
|
||||
impl From<FTM3_OBE_CTRL_A> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: FTM3_OBE_CTRL_A) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _FTM3_OBE_CTRLW<'a> {
|
||||
#[doc = "Reader of field `FTM3_OBE_CTRL`"]
|
||||
pub type FTM3_OBE_CTRL_R = crate::R<bool, FTM3_OBE_CTRL_A>;
|
||||
impl FTM3_OBE_CTRL_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> FTM3_OBE_CTRL_A {
|
||||
match self.bits {
|
||||
false => FTM3_OBE_CTRL_A::_0,
|
||||
true => FTM3_OBE_CTRL_A::_1,
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0(&self) -> bool {
|
||||
*self == FTM3_OBE_CTRL_A::_0
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1(&self) -> bool {
|
||||
*self == FTM3_OBE_CTRL_A::_1
|
||||
}
|
||||
}
|
||||
#[doc = "Write proxy for field `FTM3_OBE_CTRL`"]
|
||||
pub struct FTM3_OBE_CTRL_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _FTM3_OBE_CTRLW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: FTM3_OBE_CTRLW) -> &'a mut W {
|
||||
impl<'a> FTM3_OBE_CTRL_W<'a> {
|
||||
#[doc = r"Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: FTM3_OBE_CTRL_A) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
self.bit(variant.into())
|
||||
}
|
||||
}
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\] = 1'b1). Otherwise the channel output is tristated."]
|
||||
#[inline]
|
||||
#[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE\\[FAULTM\\]!=2'b00 and FTM_FLTCTRL\\[FSTATE\\]=1'b0) and PWM is enabled (FTM_SC\\[PWMENn\\]
|
||||
= 1'b1). Otherwise the channel output is tristated."]
|
||||
#[inline(always)]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(FTM3_OBE_CTRLW::_0)
|
||||
self.variant(FTM3_OBE_CTRL_A::_0)
|
||||
}
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\] or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
#[inline]
|
||||
#[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture \\[DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00\\]
|
||||
or dual edge capture mode \\[DECAPEN=1'b1\\]."]
|
||||
#[inline(always)]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(FTM3_OBE_CTRLW::_1)
|
||||
self.variant(FTM3_OBE_CTRL_A::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 19;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bit 16 - FTM0 OBE CTRL bit"]
|
||||
#[inline]
|
||||
pub fn ftm0_obe_ctrl(&self) -> FTM0_OBE_CTRLR {
|
||||
FTM0_OBE_CTRLR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 16;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
#[inline(always)]
|
||||
pub fn ftm0_obe_ctrl(&self) -> FTM0_OBE_CTRL_R {
|
||||
FTM0_OBE_CTRL_R::new(((self.bits >> 16) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 17 - FTM1 OBE CTRL bit"]
|
||||
#[inline]
|
||||
pub fn ftm1_obe_ctrl(&self) -> FTM1_OBE_CTRLR {
|
||||
FTM1_OBE_CTRLR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 17;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
#[inline(always)]
|
||||
pub fn ftm1_obe_ctrl(&self) -> FTM1_OBE_CTRL_R {
|
||||
FTM1_OBE_CTRL_R::new(((self.bits >> 17) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 18 - FTM2 OBE CTRL bit"]
|
||||
#[inline]
|
||||
pub fn ftm2_obe_ctrl(&self) -> FTM2_OBE_CTRLR {
|
||||
FTM2_OBE_CTRLR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 18;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
#[inline(always)]
|
||||
pub fn ftm2_obe_ctrl(&self) -> FTM2_OBE_CTRL_R {
|
||||
FTM2_OBE_CTRL_R::new(((self.bits >> 18) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 19 - FTM3 OBE CTRL bit"]
|
||||
#[inline]
|
||||
pub fn ftm3_obe_ctrl(&self) -> FTM3_OBE_CTRLR {
|
||||
FTM3_OBE_CTRLR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 19;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
#[inline(always)]
|
||||
pub fn ftm3_obe_ctrl(&self) -> FTM3_OBE_CTRL_R {
|
||||
FTM3_OBE_CTRL_R::new(((self.bits >> 19) & 0x01) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bit 16 - FTM0 OBE CTRL bit"]
|
||||
#[inline]
|
||||
pub fn ftm0_obe_ctrl(&mut self) -> _FTM0_OBE_CTRLW {
|
||||
_FTM0_OBE_CTRLW { w: self }
|
||||
#[inline(always)]
|
||||
pub fn ftm0_obe_ctrl(&mut self) -> FTM0_OBE_CTRL_W {
|
||||
FTM0_OBE_CTRL_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 17 - FTM1 OBE CTRL bit"]
|
||||
#[inline]
|
||||
pub fn ftm1_obe_ctrl(&mut self) -> _FTM1_OBE_CTRLW {
|
||||
_FTM1_OBE_CTRLW { w: self }
|
||||
#[inline(always)]
|
||||
pub fn ftm1_obe_ctrl(&mut self) -> FTM1_OBE_CTRL_W {
|
||||
FTM1_OBE_CTRL_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 18 - FTM2 OBE CTRL bit"]
|
||||
#[inline]
|
||||
pub fn ftm2_obe_ctrl(&mut self) -> _FTM2_OBE_CTRLW {
|
||||
_FTM2_OBE_CTRLW { w: self }
|
||||
#[inline(always)]
|
||||
pub fn ftm2_obe_ctrl(&mut self) -> FTM2_OBE_CTRL_W {
|
||||
FTM2_OBE_CTRL_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 19 - FTM3 OBE CTRL bit"]
|
||||
#[inline]
|
||||
pub fn ftm3_obe_ctrl(&mut self) -> _FTM3_OBE_CTRLW {
|
||||
_FTM3_OBE_CTRLW { w: self }
|
||||
#[inline(always)]
|
||||
pub fn ftm3_obe_ctrl(&mut self) -> FTM3_OBE_CTRL_W {
|
||||
FTM3_OBE_CTRL_W { w: self }
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,121 +1,50 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
#[doc = r" Value to write to the register"]
|
||||
pub struct W {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::MISCTRL1 {
|
||||
#[doc = r" Modifies the contents of the register"]
|
||||
#[inline]
|
||||
pub fn modify<F>(&self, f: F)
|
||||
where
|
||||
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let r = R { bits: bits };
|
||||
let mut w = W { bits: bits };
|
||||
f(&r, &mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
#[doc = r" Writes to the register"]
|
||||
#[inline]
|
||||
pub fn write<F>(&self, f: F)
|
||||
where
|
||||
F: FnOnce(&mut W) -> &mut W,
|
||||
{
|
||||
let mut w = W::reset_value();
|
||||
f(&mut w);
|
||||
self.register.set(w.bits);
|
||||
}
|
||||
#[doc = r" Writes the reset value to the register"]
|
||||
#[inline]
|
||||
pub fn reset(&self) {
|
||||
self.write(|w| w)
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct SW_TRGR {
|
||||
bits: bool,
|
||||
}
|
||||
impl SW_TRGR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bit(&self) -> bool {
|
||||
self.bits
|
||||
}
|
||||
#[doc = r" Returns `true` if the bit is clear (0)"]
|
||||
#[inline]
|
||||
pub fn bit_is_clear(&self) -> bool {
|
||||
!self.bit()
|
||||
}
|
||||
#[doc = r" Returns `true` if the bit is set (1)"]
|
||||
#[inline]
|
||||
pub fn bit_is_set(&self) -> bool {
|
||||
self.bit()
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _SW_TRGW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _SW_TRGW<'a> {
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bit 0 - Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity)."]
|
||||
#[inline]
|
||||
pub fn sw_trg(&self) -> SW_TRGR {
|
||||
let bits = {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
};
|
||||
SW_TRGR { bits }
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bit 0 - Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity)."]
|
||||
#[inline]
|
||||
pub fn sw_trg(&mut self) -> _SW_TRGW {
|
||||
_SW_TRGW { w: self }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register MISCTRL1"]
|
||||
pub type R = crate::R<u32, super::MISCTRL1>;
|
||||
#[doc = "Writer for register MISCTRL1"]
|
||||
pub type W = crate::W<u32, super::MISCTRL1>;
|
||||
#[doc = "Register MISCTRL1 `reset()`'s with value 0"]
|
||||
impl crate::ResetValue for super::MISCTRL1 {
|
||||
type Type = u32;
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Type {
|
||||
0
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `SW_TRG`"]
|
||||
pub type SW_TRG_R = crate::R<bool, bool>;
|
||||
#[doc = "Write proxy for field `SW_TRG`"]
|
||||
pub struct SW_TRG_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> SW_TRG_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity)."]
|
||||
#[inline(always)]
|
||||
pub fn sw_trg(&self) -> SW_TRG_R {
|
||||
SW_TRG_R::new((self.bits & 0x01) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity)."]
|
||||
#[inline(always)]
|
||||
pub fn sw_trg(&mut self) -> SW_TRG_W {
|
||||
SW_TRG_W { w: self }
|
||||
}
|
||||
}
|
||||
|
||||
1098
src/sim/platcgc.rs
1098
src/sim/platcgc.rs
File diff suppressed because it is too large
Load Diff
469
src/sim/sdid.rs
469
src/sim/sdid.rs
@ -1,286 +1,183 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::SDID {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct FEATURESR {
|
||||
bits: u8,
|
||||
}
|
||||
impl FEATURESR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `PACKAGE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum PACKAGER {
|
||||
#[doc = "48 LQFP"]
|
||||
_0010,
|
||||
#[doc = "64 LQFP"]
|
||||
_0011,
|
||||
#[doc = "100 LQFP"]
|
||||
_0100,
|
||||
#[doc = "144 LQFP"]
|
||||
_0110,
|
||||
#[doc = "176 LQFP"]
|
||||
_0111,
|
||||
#[doc = "100 MAP BGA"]
|
||||
_1000,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
}
|
||||
impl PACKAGER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
PACKAGER::_0010 => 2,
|
||||
PACKAGER::_0011 => 3,
|
||||
PACKAGER::_0100 => 4,
|
||||
PACKAGER::_0110 => 6,
|
||||
PACKAGER::_0111 => 7,
|
||||
PACKAGER::_1000 => 8,
|
||||
PACKAGER::_Reserved(bits) => bits,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> PACKAGER {
|
||||
match value {
|
||||
2 => PACKAGER::_0010,
|
||||
3 => PACKAGER::_0011,
|
||||
4 => PACKAGER::_0100,
|
||||
6 => PACKAGER::_0110,
|
||||
7 => PACKAGER::_0111,
|
||||
8 => PACKAGER::_1000,
|
||||
i => PACKAGER::_Reserved(i),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0010`"]
|
||||
#[inline]
|
||||
pub fn is_0010(&self) -> bool {
|
||||
*self == PACKAGER::_0010
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0011`"]
|
||||
#[inline]
|
||||
pub fn is_0011(&self) -> bool {
|
||||
*self == PACKAGER::_0011
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0100`"]
|
||||
#[inline]
|
||||
pub fn is_0100(&self) -> bool {
|
||||
*self == PACKAGER::_0100
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0110`"]
|
||||
#[inline]
|
||||
pub fn is_0110(&self) -> bool {
|
||||
*self == PACKAGER::_0110
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0111`"]
|
||||
#[inline]
|
||||
pub fn is_0111(&self) -> bool {
|
||||
*self == PACKAGER::_0111
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1000`"]
|
||||
#[inline]
|
||||
pub fn is_1000(&self) -> bool {
|
||||
*self == PACKAGER::_1000
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct REVIDR {
|
||||
bits: u8,
|
||||
}
|
||||
impl REVIDR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = "Possible values of the field `RAMSIZE`"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
pub enum RAMSIZER {
|
||||
#[doc = "128 KB (S32K148), Reserved (others)"]
|
||||
_0111,
|
||||
#[doc = "160 KB (S32K148) , Reserved (others)"]
|
||||
_1001,
|
||||
#[doc = "192 KB (S32K148), 16 KB (S32K142), Reserved (others)"]
|
||||
_1011,
|
||||
#[doc = "48 KB (S32K144), 24 KB (S32K142), Reserved (others)"]
|
||||
_1101,
|
||||
#[doc = "256 KB (S32K148), 64 KB (S32K144), 32 KB (S32K142)"]
|
||||
_1111,
|
||||
#[doc = r" Reserved"]
|
||||
_Reserved(u8),
|
||||
}
|
||||
impl RAMSIZER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
match *self {
|
||||
RAMSIZER::_0111 => 7,
|
||||
RAMSIZER::_1001 => 9,
|
||||
RAMSIZER::_1011 => 11,
|
||||
RAMSIZER::_1101 => 13,
|
||||
RAMSIZER::_1111 => 15,
|
||||
RAMSIZER::_Reserved(bits) => bits,
|
||||
}
|
||||
}
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _from(value: u8) -> RAMSIZER {
|
||||
match value {
|
||||
7 => RAMSIZER::_0111,
|
||||
9 => RAMSIZER::_1001,
|
||||
11 => RAMSIZER::_1011,
|
||||
13 => RAMSIZER::_1101,
|
||||
15 => RAMSIZER::_1111,
|
||||
i => RAMSIZER::_Reserved(i),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0111`"]
|
||||
#[inline]
|
||||
pub fn is_0111(&self) -> bool {
|
||||
*self == RAMSIZER::_0111
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1001`"]
|
||||
#[inline]
|
||||
pub fn is_1001(&self) -> bool {
|
||||
*self == RAMSIZER::_1001
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1011`"]
|
||||
#[inline]
|
||||
pub fn is_1011(&self) -> bool {
|
||||
*self == RAMSIZER::_1011
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1101`"]
|
||||
#[inline]
|
||||
pub fn is_1101(&self) -> bool {
|
||||
*self == RAMSIZER::_1101
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1111`"]
|
||||
#[inline]
|
||||
pub fn is_1111(&self) -> bool {
|
||||
*self == RAMSIZER::_1111
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct DERIVATER {
|
||||
bits: u8,
|
||||
}
|
||||
impl DERIVATER {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct SUBSERIESR {
|
||||
bits: u8,
|
||||
}
|
||||
impl SUBSERIESR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct GENERATIONR {
|
||||
bits: u8,
|
||||
}
|
||||
impl GENERATIONR {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u8 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:7 - Features"]
|
||||
#[inline]
|
||||
pub fn features(&self) -> FEATURESR {
|
||||
let bits = {
|
||||
const MASK: u8 = 255;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
FEATURESR { bits }
|
||||
}
|
||||
#[doc = "Bits 8:11 - Package"]
|
||||
#[inline]
|
||||
pub fn package(&self) -> PACKAGER {
|
||||
PACKAGER::_from({
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 8;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
#[doc = "Bits 12:15 - Device revision number"]
|
||||
#[inline]
|
||||
pub fn revid(&self) -> REVIDR {
|
||||
let bits = {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 12;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
REVIDR { bits }
|
||||
}
|
||||
#[doc = "Bits 16:19 - RAM size"]
|
||||
#[inline]
|
||||
pub fn ramsize(&self) -> RAMSIZER {
|
||||
RAMSIZER::_from({
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 16;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
})
|
||||
}
|
||||
#[doc = "Bits 20:23 - Derivate"]
|
||||
#[inline]
|
||||
pub fn derivate(&self) -> DERIVATER {
|
||||
let bits = {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 20;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
DERIVATER { bits }
|
||||
}
|
||||
#[doc = "Bits 24:27 - Subseries"]
|
||||
#[inline]
|
||||
pub fn subseries(&self) -> SUBSERIESR {
|
||||
let bits = {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 24;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
SUBSERIESR { bits }
|
||||
}
|
||||
#[doc = "Bits 28:31 - S32K product series generation"]
|
||||
#[inline]
|
||||
pub fn generation(&self) -> GENERATIONR {
|
||||
let bits = {
|
||||
const MASK: u8 = 15;
|
||||
const OFFSET: u8 = 28;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u8
|
||||
};
|
||||
GENERATIONR { bits }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register SDID"]
|
||||
pub type R = crate::R<u32, super::SDID>;
|
||||
#[doc = "Reader of field `FEATURES`"]
|
||||
pub type FEATURES_R = crate::R<u8, u8>;
|
||||
#[doc = "Package\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
#[repr(u8)]
|
||||
pub enum PACKAGE_A {
|
||||
#[doc = "2: 48 LQFP"]
|
||||
_0010 = 2,
|
||||
#[doc = "3: 64 LQFP"]
|
||||
_0011 = 3,
|
||||
#[doc = "4: 100 LQFP"]
|
||||
_0100 = 4,
|
||||
#[doc = "6: 144 LQFP"]
|
||||
_0110 = 6,
|
||||
#[doc = "7: 176 LQFP"]
|
||||
_0111 = 7,
|
||||
#[doc = "8: 100 MAP BGA"]
|
||||
_1000 = 8,
|
||||
}
|
||||
impl From<PACKAGE_A> for u8 {
|
||||
#[inline(always)]
|
||||
fn from(variant: PACKAGE_A) -> Self {
|
||||
variant as _
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `PACKAGE`"]
|
||||
pub type PACKAGE_R = crate::R<u8, PACKAGE_A>;
|
||||
impl PACKAGE_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> crate::Variant<u8, PACKAGE_A> {
|
||||
use crate::Variant::*;
|
||||
match self.bits {
|
||||
2 => Val(PACKAGE_A::_0010),
|
||||
3 => Val(PACKAGE_A::_0011),
|
||||
4 => Val(PACKAGE_A::_0100),
|
||||
6 => Val(PACKAGE_A::_0110),
|
||||
7 => Val(PACKAGE_A::_0111),
|
||||
8 => Val(PACKAGE_A::_1000),
|
||||
i => Res(i),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0010`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0010(&self) -> bool {
|
||||
*self == PACKAGE_A::_0010
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0011`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0011(&self) -> bool {
|
||||
*self == PACKAGE_A::_0011
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0100`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0100(&self) -> bool {
|
||||
*self == PACKAGE_A::_0100
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0110`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0110(&self) -> bool {
|
||||
*self == PACKAGE_A::_0110
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0111`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0111(&self) -> bool {
|
||||
*self == PACKAGE_A::_0111
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1000`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1000(&self) -> bool {
|
||||
*self == PACKAGE_A::_1000
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `REVID`"]
|
||||
pub type REVID_R = crate::R<u8, u8>;
|
||||
#[doc = "RAM size\n\nValue on reset: 0"]
|
||||
#[derive(Clone, Copy, Debug, PartialEq)]
|
||||
#[repr(u8)]
|
||||
pub enum RAMSIZE_A {
|
||||
#[doc = "7: 128 KB (S32K148), Reserved (others)"]
|
||||
_0111 = 7,
|
||||
#[doc = "9: 160 KB (S32K148) , Reserved (others)"]
|
||||
_1001 = 9,
|
||||
#[doc = "11: 192 KB (S32K148), 16 KB (S32K142), Reserved (others)"]
|
||||
_1011 = 11,
|
||||
#[doc = "13: 48 KB (S32K144), 24 KB (S32K142), Reserved (others)"]
|
||||
_1101 = 13,
|
||||
#[doc = "15: 256 KB (S32K148), 64 KB (S32K144), 32 KB (S32K142)"]
|
||||
_1111 = 15,
|
||||
}
|
||||
impl From<RAMSIZE_A> for u8 {
|
||||
#[inline(always)]
|
||||
fn from(variant: RAMSIZE_A) -> Self {
|
||||
variant as _
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `RAMSIZE`"]
|
||||
pub type RAMSIZE_R = crate::R<u8, RAMSIZE_A>;
|
||||
impl RAMSIZE_R {
|
||||
#[doc = r"Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub fn variant(&self) -> crate::Variant<u8, RAMSIZE_A> {
|
||||
use crate::Variant::*;
|
||||
match self.bits {
|
||||
7 => Val(RAMSIZE_A::_0111),
|
||||
9 => Val(RAMSIZE_A::_1001),
|
||||
11 => Val(RAMSIZE_A::_1011),
|
||||
13 => Val(RAMSIZE_A::_1101),
|
||||
15 => Val(RAMSIZE_A::_1111),
|
||||
i => Res(i),
|
||||
}
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_0111`"]
|
||||
#[inline(always)]
|
||||
pub fn is_0111(&self) -> bool {
|
||||
*self == RAMSIZE_A::_0111
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1001`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1001(&self) -> bool {
|
||||
*self == RAMSIZE_A::_1001
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1011`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1011(&self) -> bool {
|
||||
*self == RAMSIZE_A::_1011
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1101`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1101(&self) -> bool {
|
||||
*self == RAMSIZE_A::_1101
|
||||
}
|
||||
#[doc = "Checks if the value of the field is `_1111`"]
|
||||
#[inline(always)]
|
||||
pub fn is_1111(&self) -> bool {
|
||||
*self == RAMSIZE_A::_1111
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of field `DERIVATE`"]
|
||||
pub type DERIVATE_R = crate::R<u8, u8>;
|
||||
#[doc = "Reader of field `SUBSERIES`"]
|
||||
pub type SUBSERIES_R = crate::R<u8, u8>;
|
||||
#[doc = "Reader of field `GENERATION`"]
|
||||
pub type GENERATION_R = crate::R<u8, u8>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:7 - Features"]
|
||||
#[inline(always)]
|
||||
pub fn features(&self) -> FEATURES_R {
|
||||
FEATURES_R::new((self.bits & 0xff) as u8)
|
||||
}
|
||||
#[doc = "Bits 8:11 - Package"]
|
||||
#[inline(always)]
|
||||
pub fn package(&self) -> PACKAGE_R {
|
||||
PACKAGE_R::new(((self.bits >> 8) & 0x0f) as u8)
|
||||
}
|
||||
#[doc = "Bits 12:15 - Device revision number"]
|
||||
#[inline(always)]
|
||||
pub fn revid(&self) -> REVID_R {
|
||||
REVID_R::new(((self.bits >> 12) & 0x0f) as u8)
|
||||
}
|
||||
#[doc = "Bits 16:19 - RAM size"]
|
||||
#[inline(always)]
|
||||
pub fn ramsize(&self) -> RAMSIZE_R {
|
||||
RAMSIZE_R::new(((self.bits >> 16) & 0x0f) as u8)
|
||||
}
|
||||
#[doc = "Bits 20:23 - Derivate"]
|
||||
#[inline(always)]
|
||||
pub fn derivate(&self) -> DERIVATE_R {
|
||||
DERIVATE_R::new(((self.bits >> 20) & 0x0f) as u8)
|
||||
}
|
||||
#[doc = "Bits 24:27 - Subseries"]
|
||||
#[inline(always)]
|
||||
pub fn subseries(&self) -> SUBSERIES_R {
|
||||
SUBSERIES_R::new(((self.bits >> 24) & 0x0f) as u8)
|
||||
}
|
||||
#[doc = "Bits 28:31 - S32K product series generation"]
|
||||
#[inline(always)]
|
||||
pub fn generation(&self) -> GENERATION_R {
|
||||
GENERATION_R::new(((self.bits >> 28) & 0x0f) as u8)
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,39 +1,11 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::UIDH {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct UID127_96R {
|
||||
bits: u32,
|
||||
}
|
||||
impl UID127_96R {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:31 - Unique Identification"]
|
||||
#[inline]
|
||||
pub fn uid127_96(&self) -> UID127_96R {
|
||||
let bits = {
|
||||
const MASK: u32 = 4294967295;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u32
|
||||
};
|
||||
UID127_96R { bits }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register UIDH"]
|
||||
pub type R = crate::R<u32, super::UIDH>;
|
||||
#[doc = "Reader of field `UID127_96`"]
|
||||
pub type UID127_96_R = crate::R<u32, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:31 - Unique Identification"]
|
||||
#[inline(always)]
|
||||
pub fn uid127_96(&self) -> UID127_96_R {
|
||||
UID127_96_R::new((self.bits & 0xffff_ffff) as u32)
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,39 +1,11 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::UIDL {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct UID31_0R {
|
||||
bits: u32,
|
||||
}
|
||||
impl UID31_0R {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:31 - Unique Identification"]
|
||||
#[inline]
|
||||
pub fn uid31_0(&self) -> UID31_0R {
|
||||
let bits = {
|
||||
const MASK: u32 = 4294967295;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u32
|
||||
};
|
||||
UID31_0R { bits }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register UIDL"]
|
||||
pub type R = crate::R<u32, super::UIDL>;
|
||||
#[doc = "Reader of field `UID31_0`"]
|
||||
pub type UID31_0_R = crate::R<u32, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:31 - Unique Identification"]
|
||||
#[inline(always)]
|
||||
pub fn uid31_0(&self) -> UID31_0_R {
|
||||
UID31_0_R::new((self.bits & 0xffff_ffff) as u32)
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,39 +1,11 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::UIDMH {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct UID95_64R {
|
||||
bits: u32,
|
||||
}
|
||||
impl UID95_64R {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:31 - Unique Identification"]
|
||||
#[inline]
|
||||
pub fn uid95_64(&self) -> UID95_64R {
|
||||
let bits = {
|
||||
const MASK: u32 = 4294967295;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u32
|
||||
};
|
||||
UID95_64R { bits }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register UIDMH"]
|
||||
pub type R = crate::R<u32, super::UIDMH>;
|
||||
#[doc = "Reader of field `UID95_64`"]
|
||||
pub type UID95_64_R = crate::R<u32, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:31 - Unique Identification"]
|
||||
#[inline(always)]
|
||||
pub fn uid95_64(&self) -> UID95_64_R {
|
||||
UID95_64_R::new((self.bits & 0xffff_ffff) as u32)
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,39 +1,11 @@
|
||||
#[doc = r" Value read from the register"]
|
||||
pub struct R {
|
||||
bits: u32,
|
||||
}
|
||||
impl super::UIDML {
|
||||
#[doc = r" Reads the contents of the register"]
|
||||
#[inline]
|
||||
pub fn read(&self) -> R {
|
||||
R { bits: self.register.get() }
|
||||
}
|
||||
}
|
||||
#[doc = r" Value of the field"]
|
||||
pub struct UID63_32R {
|
||||
bits: u32,
|
||||
}
|
||||
impl UID63_32R {
|
||||
#[doc = r" Value of the field as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bits 0:31 - Unique Identification"]
|
||||
#[inline]
|
||||
pub fn uid63_32(&self) -> UID63_32R {
|
||||
let bits = {
|
||||
const MASK: u32 = 4294967295;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) as u32
|
||||
};
|
||||
UID63_32R { bits }
|
||||
}
|
||||
}
|
||||
#[doc = "Reader of register UIDML"]
|
||||
pub type R = crate::R<u32, super::UIDML>;
|
||||
#[doc = "Reader of field `UID63_32`"]
|
||||
pub type UID63_32_R = crate::R<u32, u32>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:31 - Unique Identification"]
|
||||
#[inline(always)]
|
||||
pub fn uid63_32(&self) -> UID63_32_R {
|
||||
UID63_32_R::new((self.bits & 0xffff_ffff) as u32)
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user