Same as last commit just run through the form tool (splits up large lib.rs files)

src/sim/adcopt/mod.rs

@@ -0,0 +1,948 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::ADCOPT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `ADC0TRGSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC0TRGSELR {
+    #[doc = "PDB output"]
+    _0,
+    #[doc = "TRGMUX output"]
+    _1,
+}
+impl ADC0TRGSELR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC0TRGSELR::_0 => false,
+            ADC0TRGSELR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC0TRGSELR {
+        match value {
+            false => ADC0TRGSELR::_0,
+            true => ADC0TRGSELR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ADC0TRGSELR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ADC0TRGSELR::_1
+    }
+}
+#[doc = "Possible values of the field `ADC0SWPRETRG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC0SWPRETRGR {
+    #[doc = "Software pretrigger disabled"]
+    _000,
+    #[doc = "Reserved (do not use)"]
+    _001,
+    #[doc = "Reserved (do not use)"]
+    _010,
+    #[doc = "Reserved (do not use)"]
+    _011,
+    #[doc = "Software pretrigger 0"]
+    _100,
+    #[doc = "Software pretrigger 1"]
+    _101,
+    #[doc = "Software pretrigger 2"]
+    _110,
+    #[doc = "Software pretrigger 3"]
+    _111,
+}
+impl ADC0SWPRETRGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC0SWPRETRGR::_000 => 0,
+            ADC0SWPRETRGR::_001 => 1,
+            ADC0SWPRETRGR::_010 => 2,
+            ADC0SWPRETRGR::_011 => 3,
+            ADC0SWPRETRGR::_100 => 4,
+            ADC0SWPRETRGR::_101 => 5,
+            ADC0SWPRETRGR::_110 => 6,
+            ADC0SWPRETRGR::_111 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC0SWPRETRGR {
+        match value {
+            0 => ADC0SWPRETRGR::_000,
+            1 => ADC0SWPRETRGR::_001,
+            2 => ADC0SWPRETRGR::_010,
+            3 => ADC0SWPRETRGR::_011,
+            4 => ADC0SWPRETRGR::_100,
+            5 => ADC0SWPRETRGR::_101,
+            6 => ADC0SWPRETRGR::_110,
+            7 => ADC0SWPRETRGR::_111,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_000`"]
+    #[inline]
+    pub fn is_000(&self) -> bool {
+        *self == ADC0SWPRETRGR::_000
+    }
+    #[doc = "Checks if the value of the field is `_001`"]
+    #[inline]
+    pub fn is_001(&self) -> bool {
+        *self == ADC0SWPRETRGR::_001
+    }
+    #[doc = "Checks if the value of the field is `_010`"]
+    #[inline]
+    pub fn is_010(&self) -> bool {
+        *self == ADC0SWPRETRGR::_010
+    }
+    #[doc = "Checks if the value of the field is `_011`"]
+    #[inline]
+    pub fn is_011(&self) -> bool {
+        *self == ADC0SWPRETRGR::_011
+    }
+    #[doc = "Checks if the value of the field is `_100`"]
+    #[inline]
+    pub fn is_100(&self) -> bool {
+        *self == ADC0SWPRETRGR::_100
+    }
+    #[doc = "Checks if the value of the field is `_101`"]
+    #[inline]
+    pub fn is_101(&self) -> bool {
+        *self == ADC0SWPRETRGR::_101
+    }
+    #[doc = "Checks if the value of the field is `_110`"]
+    #[inline]
+    pub fn is_110(&self) -> bool {
+        *self == ADC0SWPRETRGR::_110
+    }
+    #[doc = "Checks if the value of the field is `_111`"]
+    #[inline]
+    pub fn is_111(&self) -> bool {
+        *self == ADC0SWPRETRGR::_111
+    }
+}
+#[doc = "Possible values of the field `ADC0PRETRGSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC0PRETRGSELR {
+    #[doc = "PDB pretrigger (default)"]
+    _00,
+    #[doc = "TRGMUX pretrigger"]
+    _01,
+    #[doc = "Software pretrigger"]
+    _10,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl ADC0PRETRGSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC0PRETRGSELR::_00 => 0,
+            ADC0PRETRGSELR::_01 => 1,
+            ADC0PRETRGSELR::_10 => 2,
+            ADC0PRETRGSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC0PRETRGSELR {
+        match value {
+            0 => ADC0PRETRGSELR::_00,
+            1 => ADC0PRETRGSELR::_01,
+            2 => ADC0PRETRGSELR::_10,
+            i => ADC0PRETRGSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == ADC0PRETRGSELR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == ADC0PRETRGSELR::_01
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == ADC0PRETRGSELR::_10
+    }
+}
+#[doc = "Possible values of the field `ADC1TRGSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC1TRGSELR {
+    #[doc = "PDB output"]
+    _0,
+    #[doc = "TRGMUX output"]
+    _1,
+}
+impl ADC1TRGSELR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ADC1TRGSELR::_0 => false,
+            ADC1TRGSELR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ADC1TRGSELR {
+        match value {
+            false => ADC1TRGSELR::_0,
+            true => ADC1TRGSELR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ADC1TRGSELR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ADC1TRGSELR::_1
+    }
+}
+#[doc = "Possible values of the field `ADC1SWPRETRG`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC1SWPRETRGR {
+    #[doc = "Software pretrigger disabled"]
+    _000,
+    #[doc = "Reserved (do not use)"]
+    _001,
+    #[doc = "Reserved (do not use)"]
+    _010,
+    #[doc = "Reserved (do not use)"]
+    _011,
+    #[doc = "Software pretrigger 0"]
+    _100,
+    #[doc = "Software pretrigger 1"]
+    _101,
+    #[doc = "Software pretrigger 2"]
+    _110,
+    #[doc = "Software pretrigger 3"]
+    _111,
+}
+impl ADC1SWPRETRGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC1SWPRETRGR::_000 => 0,
+            ADC1SWPRETRGR::_001 => 1,
+            ADC1SWPRETRGR::_010 => 2,
+            ADC1SWPRETRGR::_011 => 3,
+            ADC1SWPRETRGR::_100 => 4,
+            ADC1SWPRETRGR::_101 => 5,
+            ADC1SWPRETRGR::_110 => 6,
+            ADC1SWPRETRGR::_111 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC1SWPRETRGR {
+        match value {
+            0 => ADC1SWPRETRGR::_000,
+            1 => ADC1SWPRETRGR::_001,
+            2 => ADC1SWPRETRGR::_010,
+            3 => ADC1SWPRETRGR::_011,
+            4 => ADC1SWPRETRGR::_100,
+            5 => ADC1SWPRETRGR::_101,
+            6 => ADC1SWPRETRGR::_110,
+            7 => ADC1SWPRETRGR::_111,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_000`"]
+    #[inline]
+    pub fn is_000(&self) -> bool {
+        *self == ADC1SWPRETRGR::_000
+    }
+    #[doc = "Checks if the value of the field is `_001`"]
+    #[inline]
+    pub fn is_001(&self) -> bool {
+        *self == ADC1SWPRETRGR::_001
+    }
+    #[doc = "Checks if the value of the field is `_010`"]
+    #[inline]
+    pub fn is_010(&self) -> bool {
+        *self == ADC1SWPRETRGR::_010
+    }
+    #[doc = "Checks if the value of the field is `_011`"]
+    #[inline]
+    pub fn is_011(&self) -> bool {
+        *self == ADC1SWPRETRGR::_011
+    }
+    #[doc = "Checks if the value of the field is `_100`"]
+    #[inline]
+    pub fn is_100(&self) -> bool {
+        *self == ADC1SWPRETRGR::_100
+    }
+    #[doc = "Checks if the value of the field is `_101`"]
+    #[inline]
+    pub fn is_101(&self) -> bool {
+        *self == ADC1SWPRETRGR::_101
+    }
+    #[doc = "Checks if the value of the field is `_110`"]
+    #[inline]
+    pub fn is_110(&self) -> bool {
+        *self == ADC1SWPRETRGR::_110
+    }
+    #[doc = "Checks if the value of the field is `_111`"]
+    #[inline]
+    pub fn is_111(&self) -> bool {
+        *self == ADC1SWPRETRGR::_111
+    }
+}
+#[doc = "Possible values of the field `ADC1PRETRGSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ADC1PRETRGSELR {
+    #[doc = "PDB pretrigger (default)"]
+    _00,
+    #[doc = "TRGMUX pretrigger"]
+    _01,
+    #[doc = "Software pretrigger"]
+    _10,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl ADC1PRETRGSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            ADC1PRETRGSELR::_00 => 0,
+            ADC1PRETRGSELR::_01 => 1,
+            ADC1PRETRGSELR::_10 => 2,
+            ADC1PRETRGSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> ADC1PRETRGSELR {
+        match value {
+            0 => ADC1PRETRGSELR::_00,
+            1 => ADC1PRETRGSELR::_01,
+            2 => ADC1PRETRGSELR::_10,
+            i => ADC1PRETRGSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == ADC1PRETRGSELR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == ADC1PRETRGSELR::_01
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == ADC1PRETRGSELR::_10
+    }
+}
+#[doc = "Values that can be written to the field `ADC0TRGSEL`"]
+pub enum ADC0TRGSELW {
+    #[doc = "PDB output"]
+    _0,
+    #[doc = "TRGMUX output"]
+    _1,
+}
+impl ADC0TRGSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC0TRGSELW::_0 => false,
+            ADC0TRGSELW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC0TRGSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC0TRGSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC0TRGSELW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "PDB output"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ADC0TRGSELW::_0)
+    }
+    #[doc = "TRGMUX output"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ADC0TRGSELW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC0SWPRETRG`"]
+pub enum ADC0SWPRETRGW {
+    #[doc = "Software pretrigger disabled"]
+    _000,
+    #[doc = "Reserved (do not use)"]
+    _001,
+    #[doc = "Reserved (do not use)"]
+    _010,
+    #[doc = "Reserved (do not use)"]
+    _011,
+    #[doc = "Software pretrigger 0"]
+    _100,
+    #[doc = "Software pretrigger 1"]
+    _101,
+    #[doc = "Software pretrigger 2"]
+    _110,
+    #[doc = "Software pretrigger 3"]
+    _111,
+}
+impl ADC0SWPRETRGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC0SWPRETRGW::_000 => 0,
+            ADC0SWPRETRGW::_001 => 1,
+            ADC0SWPRETRGW::_010 => 2,
+            ADC0SWPRETRGW::_011 => 3,
+            ADC0SWPRETRGW::_100 => 4,
+            ADC0SWPRETRGW::_101 => 5,
+            ADC0SWPRETRGW::_110 => 6,
+            ADC0SWPRETRGW::_111 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC0SWPRETRGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC0SWPRETRGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC0SWPRETRGW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Software pretrigger disabled"]
+    #[inline]
+    pub fn _000(self) -> &'a mut W {
+        self.variant(ADC0SWPRETRGW::_000)
+    }
+    #[doc = "Reserved (do not use)"]
+    #[inline]
+    pub fn _001(self) -> &'a mut W {
+        self.variant(ADC0SWPRETRGW::_001)
+    }
+    #[doc = "Reserved (do not use)"]
+    #[inline]
+    pub fn _010(self) -> &'a mut W {
+        self.variant(ADC0SWPRETRGW::_010)
+    }
+    #[doc = "Reserved (do not use)"]
+    #[inline]
+    pub fn _011(self) -> &'a mut W {
+        self.variant(ADC0SWPRETRGW::_011)
+    }
+    #[doc = "Software pretrigger 0"]
+    #[inline]
+    pub fn _100(self) -> &'a mut W {
+        self.variant(ADC0SWPRETRGW::_100)
+    }
+    #[doc = "Software pretrigger 1"]
+    #[inline]
+    pub fn _101(self) -> &'a mut W {
+        self.variant(ADC0SWPRETRGW::_101)
+    }
+    #[doc = "Software pretrigger 2"]
+    #[inline]
+    pub fn _110(self) -> &'a mut W {
+        self.variant(ADC0SWPRETRGW::_110)
+    }
+    #[doc = "Software pretrigger 3"]
+    #[inline]
+    pub fn _111(self) -> &'a mut W {
+        self.variant(ADC0SWPRETRGW::_111)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC0PRETRGSEL`"]
+pub enum ADC0PRETRGSELW {
+    #[doc = "PDB pretrigger (default)"]
+    _00,
+    #[doc = "TRGMUX pretrigger"]
+    _01,
+    #[doc = "Software pretrigger"]
+    _10,
+}
+impl ADC0PRETRGSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC0PRETRGSELW::_00 => 0,
+            ADC0PRETRGSELW::_01 => 1,
+            ADC0PRETRGSELW::_10 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC0PRETRGSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC0PRETRGSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC0PRETRGSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "PDB pretrigger (default)"]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(ADC0PRETRGSELW::_00)
+    }
+    #[doc = "TRGMUX pretrigger"]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(ADC0PRETRGSELW::_01)
+    }
+    #[doc = "Software pretrigger"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(ADC0PRETRGSELW::_10)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC1TRGSEL`"]
+pub enum ADC1TRGSELW {
+    #[doc = "PDB output"]
+    _0,
+    #[doc = "TRGMUX output"]
+    _1,
+}
+impl ADC1TRGSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ADC1TRGSELW::_0 => false,
+            ADC1TRGSELW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC1TRGSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC1TRGSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC1TRGSELW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "PDB output"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ADC1TRGSELW::_0)
+    }
+    #[doc = "TRGMUX output"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ADC1TRGSELW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC1SWPRETRG`"]
+pub enum ADC1SWPRETRGW {
+    #[doc = "Software pretrigger disabled"]
+    _000,
+    #[doc = "Reserved (do not use)"]
+    _001,
+    #[doc = "Reserved (do not use)"]
+    _010,
+    #[doc = "Reserved (do not use)"]
+    _011,
+    #[doc = "Software pretrigger 0"]
+    _100,
+    #[doc = "Software pretrigger 1"]
+    _101,
+    #[doc = "Software pretrigger 2"]
+    _110,
+    #[doc = "Software pretrigger 3"]
+    _111,
+}
+impl ADC1SWPRETRGW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC1SWPRETRGW::_000 => 0,
+            ADC1SWPRETRGW::_001 => 1,
+            ADC1SWPRETRGW::_010 => 2,
+            ADC1SWPRETRGW::_011 => 3,
+            ADC1SWPRETRGW::_100 => 4,
+            ADC1SWPRETRGW::_101 => 5,
+            ADC1SWPRETRGW::_110 => 6,
+            ADC1SWPRETRGW::_111 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC1SWPRETRGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC1SWPRETRGW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC1SWPRETRGW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Software pretrigger disabled"]
+    #[inline]
+    pub fn _000(self) -> &'a mut W {
+        self.variant(ADC1SWPRETRGW::_000)
+    }
+    #[doc = "Reserved (do not use)"]
+    #[inline]
+    pub fn _001(self) -> &'a mut W {
+        self.variant(ADC1SWPRETRGW::_001)
+    }
+    #[doc = "Reserved (do not use)"]
+    #[inline]
+    pub fn _010(self) -> &'a mut W {
+        self.variant(ADC1SWPRETRGW::_010)
+    }
+    #[doc = "Reserved (do not use)"]
+    #[inline]
+    pub fn _011(self) -> &'a mut W {
+        self.variant(ADC1SWPRETRGW::_011)
+    }
+    #[doc = "Software pretrigger 0"]
+    #[inline]
+    pub fn _100(self) -> &'a mut W {
+        self.variant(ADC1SWPRETRGW::_100)
+    }
+    #[doc = "Software pretrigger 1"]
+    #[inline]
+    pub fn _101(self) -> &'a mut W {
+        self.variant(ADC1SWPRETRGW::_101)
+    }
+    #[doc = "Software pretrigger 2"]
+    #[inline]
+    pub fn _110(self) -> &'a mut W {
+        self.variant(ADC1SWPRETRGW::_110)
+    }
+    #[doc = "Software pretrigger 3"]
+    #[inline]
+    pub fn _111(self) -> &'a mut W {
+        self.variant(ADC1SWPRETRGW::_111)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ADC1PRETRGSEL`"]
+pub enum ADC1PRETRGSELW {
+    #[doc = "PDB pretrigger (default)"]
+    _00,
+    #[doc = "TRGMUX pretrigger"]
+    _01,
+    #[doc = "Software pretrigger"]
+    _10,
+}
+impl ADC1PRETRGSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            ADC1PRETRGSELW::_00 => 0,
+            ADC1PRETRGSELW::_01 => 1,
+            ADC1PRETRGSELW::_10 => 2,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ADC1PRETRGSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ADC1PRETRGSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ADC1PRETRGSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "PDB pretrigger (default)"]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(ADC1PRETRGSELW::_00)
+    }
+    #[doc = "TRGMUX pretrigger"]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(ADC1PRETRGSELW::_01)
+    }
+    #[doc = "Software pretrigger"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(ADC1PRETRGSELW::_10)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - ADC0 trigger source select"]
+    #[inline]
+    pub fn adc0trgsel(&self) -> ADC0TRGSELR {
+        ADC0TRGSELR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 1:3 - ADC0 software pretrigger sources"]
+    #[inline]
+    pub fn adc0swpretrg(&self) -> ADC0SWPRETRGR {
+        ADC0SWPRETRGR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 4:5 - ADC0 pretrigger source select"]
+    #[inline]
+    pub fn adc0pretrgsel(&self) -> ADC0PRETRGSELR {
+        ADC0PRETRGSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 8 - ADC1 trigger source select"]
+    #[inline]
+    pub fn adc1trgsel(&self) -> ADC1TRGSELR {
+        ADC1TRGSELR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 9:11 - ADC1 software pretrigger sources"]
+    #[inline]
+    pub fn adc1swpretrg(&self) -> ADC1SWPRETRGR {
+        ADC1SWPRETRGR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 12:13 - ADC1 pretrigger source select"]
+    #[inline]
+    pub fn adc1pretrgsel(&self) -> ADC1PRETRGSELR {
+        ADC1PRETRGSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - ADC0 trigger source select"]
+    #[inline]
+    pub fn adc0trgsel(&mut self) -> _ADC0TRGSELW {
+        _ADC0TRGSELW { w: self }
+    }
+    #[doc = "Bits 1:3 - ADC0 software pretrigger sources"]
+    #[inline]
+    pub fn adc0swpretrg(&mut self) -> _ADC0SWPRETRGW {
+        _ADC0SWPRETRGW { w: self }
+    }
+    #[doc = "Bits 4:5 - ADC0 pretrigger source select"]
+    #[inline]
+    pub fn adc0pretrgsel(&mut self) -> _ADC0PRETRGSELW {
+        _ADC0PRETRGSELW { w: self }
+    }
+    #[doc = "Bit 8 - ADC1 trigger source select"]
+    #[inline]
+    pub fn adc1trgsel(&mut self) -> _ADC1TRGSELW {
+        _ADC1TRGSELW { w: self }
+    }
+    #[doc = "Bits 9:11 - ADC1 software pretrigger sources"]
+    #[inline]
+    pub fn adc1swpretrg(&mut self) -> _ADC1SWPRETRGW {
+        _ADC1SWPRETRGW { w: self }
+    }
+    #[doc = "Bits 12:13 - ADC1 pretrigger source select"]
+    #[inline]
+    pub fn adc1pretrgsel(&mut self) -> _ADC1PRETRGSELW {
+        _ADC1PRETRGSELW { w: self }
+    }
+}

src/sim/clkdiv4/mod.rs

@@ -0,0 +1,281 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CLKDIV4 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TRACEFRACR {
+    bits: bool,
+}
+impl TRACEFRACR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TRACEDIVR {
+    bits: u8,
+}
+impl TRACEDIVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `TRACEDIVEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRACEDIVENR {
+    #[doc = "Debug trace divider disabled"]
+    _0,
+    #[doc = "Debug trace divider enabled"]
+    _1,
+}
+impl TRACEDIVENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRACEDIVENR::_0 => false,
+            TRACEDIVENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRACEDIVENR {
+        match value {
+            false => TRACEDIVENR::_0,
+            true => TRACEDIVENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRACEDIVENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRACEDIVENR::_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRACEFRACW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRACEFRACW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRACEDIVW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRACEDIVW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRACEDIVEN`"]
+pub enum TRACEDIVENW {
+    #[doc = "Debug trace divider disabled"]
+    _0,
+    #[doc = "Debug trace divider enabled"]
+    _1,
+}
+impl TRACEDIVENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRACEDIVENW::_0 => false,
+            TRACEDIVENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRACEDIVENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRACEDIVENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRACEDIVENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Debug trace divider disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRACEDIVENW::_0)
+    }
+    #[doc = "Debug trace divider enabled"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRACEDIVENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 28;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear TRACEDIVEN to disable the trace clock divide function."]
+    #[inline]
+    pub fn tracefrac(&self) -> TRACEFRACR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        TRACEFRACR { bits }
+    }
+    #[doc = "Bits 1:3 - Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it after setting TRACEDIV."]
+    #[inline]
+    pub fn tracediv(&self) -> TRACEDIVR {
+        let bits = {
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TRACEDIVR { bits }
+    }
+    #[doc = "Bit 28 - Debug Trace Divider control"]
+    #[inline]
+    pub fn tracediven(&self) -> TRACEDIVENR {
+        TRACEDIVENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 268435456 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear TRACEDIVEN to disable the trace clock divide function."]
+    #[inline]
+    pub fn tracefrac(&mut self) -> _TRACEFRACW {
+        _TRACEFRACW { w: self }
+    }
+    #[doc = "Bits 1:3 - Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it after setting TRACEDIV."]
+    #[inline]
+    pub fn tracediv(&mut self) -> _TRACEDIVW {
+        _TRACEDIVW { w: self }
+    }
+    #[doc = "Bit 28 - Debug Trace Divider control"]
+    #[inline]
+    pub fn tracediven(&mut self) -> _TRACEDIVENW {
+        _TRACEDIVENW { w: self }
+    }
+}

src/sim/fcfg1/mod.rs

@@ -0,0 +1,196 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FCFG1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DEPARTR {
+    bits: u8,
+}
+impl DEPARTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `EEERAMSIZE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum EEERAMSIZER {
+    #[doc = "4 KB"]
+    _0010,
+    #[doc = "2 KB"]
+    _0011,
+    #[doc = "1 KB"]
+    _0100,
+    #[doc = "512 Bytes"]
+    _0101,
+    #[doc = "256 Bytes"]
+    _0110,
+    #[doc = "128 Bytes"]
+    _0111,
+    #[doc = "64 Bytes"]
+    _1000,
+    #[doc = "32 Bytes"]
+    _1001,
+    #[doc = "0 Bytes"]
+    _1111,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl EEERAMSIZER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            EEERAMSIZER::_0010 => 2,
+            EEERAMSIZER::_0011 => 3,
+            EEERAMSIZER::_0100 => 4,
+            EEERAMSIZER::_0101 => 5,
+            EEERAMSIZER::_0110 => 6,
+            EEERAMSIZER::_0111 => 7,
+            EEERAMSIZER::_1000 => 8,
+            EEERAMSIZER::_1001 => 9,
+            EEERAMSIZER::_1111 => 15,
+            EEERAMSIZER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> EEERAMSIZER {
+        match value {
+            2 => EEERAMSIZER::_0010,
+            3 => EEERAMSIZER::_0011,
+            4 => EEERAMSIZER::_0100,
+            5 => EEERAMSIZER::_0101,
+            6 => EEERAMSIZER::_0110,
+            7 => EEERAMSIZER::_0111,
+            8 => EEERAMSIZER::_1000,
+            9 => EEERAMSIZER::_1001,
+            15 => EEERAMSIZER::_1111,
+            i => EEERAMSIZER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0010`"]
+    #[inline]
+    pub fn is_0010(&self) -> bool {
+        *self == EEERAMSIZER::_0010
+    }
+    #[doc = "Checks if the value of the field is `_0011`"]
+    #[inline]
+    pub fn is_0011(&self) -> bool {
+        *self == EEERAMSIZER::_0011
+    }
+    #[doc = "Checks if the value of the field is `_0100`"]
+    #[inline]
+    pub fn is_0100(&self) -> bool {
+        *self == EEERAMSIZER::_0100
+    }
+    #[doc = "Checks if the value of the field is `_0101`"]
+    #[inline]
+    pub fn is_0101(&self) -> bool {
+        *self == EEERAMSIZER::_0101
+    }
+    #[doc = "Checks if the value of the field is `_0110`"]
+    #[inline]
+    pub fn is_0110(&self) -> bool {
+        *self == EEERAMSIZER::_0110
+    }
+    #[doc = "Checks if the value of the field is `_0111`"]
+    #[inline]
+    pub fn is_0111(&self) -> bool {
+        *self == EEERAMSIZER::_0111
+    }
+    #[doc = "Checks if the value of the field is `_1000`"]
+    #[inline]
+    pub fn is_1000(&self) -> bool {
+        *self == EEERAMSIZER::_1000
+    }
+    #[doc = "Checks if the value of the field is `_1001`"]
+    #[inline]
+    pub fn is_1001(&self) -> bool {
+        *self == EEERAMSIZER::_1001
+    }
+    #[doc = "Checks if the value of the field is `_1111`"]
+    #[inline]
+    pub fn is_1111(&self) -> bool {
+        *self == EEERAMSIZER::_1111
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 12:15 - FlexNVM partition"]
+    #[inline]
+    pub fn depart(&self) -> DEPARTR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DEPARTR { bits }
+    }
+    #[doc = "Bits 16:19 - EEE SRAM SIZE"]
+    #[inline]
+    pub fn eeeramsize(&self) -> EEERAMSIZER {
+        EEERAMSIZER::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}

src/sim/ftmopt1/mod.rs

@@ -0,0 +1,948 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FTMOPT1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct FTM0SYNCBITR {
+    bits: bool,
+}
+impl FTM0SYNCBITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct FTM1SYNCBITR {
+    bits: bool,
+}
+impl FTM1SYNCBITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct FTM2SYNCBITR {
+    bits: bool,
+}
+impl FTM2SYNCBITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct FTM3SYNCBITR {
+    bits: bool,
+}
+impl FTM3SYNCBITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `FTM1CH0SEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FTM1CH0SELR {
+    #[doc = "FTM1_CH0 input"]
+    _00,
+    #[doc = "CMP0 output"]
+    _01,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl FTM1CH0SELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            FTM1CH0SELR::_00 => 0,
+            FTM1CH0SELR::_01 => 1,
+            FTM1CH0SELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> FTM1CH0SELR {
+        match value {
+            0 => FTM1CH0SELR::_00,
+            1 => FTM1CH0SELR::_01,
+            i => FTM1CH0SELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == FTM1CH0SELR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == FTM1CH0SELR::_01
+    }
+}
+#[doc = "Possible values of the field `FTM2CH0SEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FTM2CH0SELR {
+    #[doc = "FTM2_CH0 input"]
+    _00,
+    #[doc = "CMP0 output"]
+    _01,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl FTM2CH0SELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            FTM2CH0SELR::_00 => 0,
+            FTM2CH0SELR::_01 => 1,
+            FTM2CH0SELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> FTM2CH0SELR {
+        match value {
+            0 => FTM2CH0SELR::_00,
+            1 => FTM2CH0SELR::_01,
+            i => FTM2CH0SELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == FTM2CH0SELR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == FTM2CH0SELR::_01
+    }
+}
+#[doc = "Possible values of the field `FTM2CH1SEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FTM2CH1SELR {
+    #[doc = "FTM2_CH1 input"]
+    _0,
+    #[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"]
+    _1,
+}
+impl FTM2CH1SELR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FTM2CH1SELR::_0 => false,
+            FTM2CH1SELR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FTM2CH1SELR {
+        match value {
+            false => FTM2CH1SELR::_0,
+            true => FTM2CH1SELR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FTM2CH1SELR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FTM2CH1SELR::_1
+    }
+}
+#[doc = "Possible values of the field `FTMGLDOK`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FTMGLDOKR {
+    #[doc = "FTM Global load mechanism disabled."]
+    _0,
+    #[doc = "FTM Global load mechanism enabled"]
+    _1,
+}
+impl FTMGLDOKR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FTMGLDOKR::_0 => false,
+            FTMGLDOKR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FTMGLDOKR {
+        match value {
+            false => FTMGLDOKR::_0,
+            true => FTMGLDOKR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FTMGLDOKR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FTMGLDOKR::_1
+    }
+}
+#[doc = "Possible values of the field `FTM0_OUTSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FTM0_OUTSELR {
+    #[doc = "No modulation with FTM1_CH1"]
+    _00000000,
+    #[doc = "Modulation with FTM1_CH1"]
+    _00000001,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl FTM0_OUTSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            FTM0_OUTSELR::_00000000 => 0,
+            FTM0_OUTSELR::_00000001 => 1,
+            FTM0_OUTSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> FTM0_OUTSELR {
+        match value {
+            0 => FTM0_OUTSELR::_00000000,
+            1 => FTM0_OUTSELR::_00000001,
+            i => FTM0_OUTSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00000000`"]
+    #[inline]
+    pub fn is_00000000(&self) -> bool {
+        *self == FTM0_OUTSELR::_00000000
+    }
+    #[doc = "Checks if the value of the field is `_00000001`"]
+    #[inline]
+    pub fn is_00000001(&self) -> bool {
+        *self == FTM0_OUTSELR::_00000001
+    }
+}
+#[doc = "Possible values of the field `FTM3_OUTSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FTM3_OUTSELR {
+    #[doc = "No modulation with FTM2_CH1"]
+    _00000000,
+    #[doc = "Modulation with FTM2_CH1"]
+    _00000001,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl FTM3_OUTSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            FTM3_OUTSELR::_00000000 => 0,
+            FTM3_OUTSELR::_00000001 => 1,
+            FTM3_OUTSELR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> FTM3_OUTSELR {
+        match value {
+            0 => FTM3_OUTSELR::_00000000,
+            1 => FTM3_OUTSELR::_00000001,
+            i => FTM3_OUTSELR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00000000`"]
+    #[inline]
+    pub fn is_00000000(&self) -> bool {
+        *self == FTM3_OUTSELR::_00000000
+    }
+    #[doc = "Checks if the value of the field is `_00000001`"]
+    #[inline]
+    pub fn is_00000001(&self) -> bool {
+        *self == FTM3_OUTSELR::_00000001
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM0SYNCBITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM0SYNCBITW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM1SYNCBITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM1SYNCBITW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM2SYNCBITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM2SYNCBITW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM3SYNCBITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM3SYNCBITW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FTM1CH0SEL`"]
+pub enum FTM1CH0SELW {
+    #[doc = "FTM1_CH0 input"]
+    _00,
+    #[doc = "CMP0 output"]
+    _01,
+}
+impl FTM1CH0SELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            FTM1CH0SELW::_00 => 0,
+            FTM1CH0SELW::_01 => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM1CH0SELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM1CH0SELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FTM1CH0SELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "FTM1_CH0 input"]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(FTM1CH0SELW::_00)
+    }
+    #[doc = "CMP0 output"]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(FTM1CH0SELW::_01)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FTM2CH0SEL`"]
+pub enum FTM2CH0SELW {
+    #[doc = "FTM2_CH0 input"]
+    _00,
+    #[doc = "CMP0 output"]
+    _01,
+}
+impl FTM2CH0SELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            FTM2CH0SELW::_00 => 0,
+            FTM2CH0SELW::_01 => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM2CH0SELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM2CH0SELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FTM2CH0SELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "FTM2_CH0 input"]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(FTM2CH0SELW::_00)
+    }
+    #[doc = "CMP0 output"]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(FTM2CH0SELW::_01)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FTM2CH1SEL`"]
+pub enum FTM2CH1SELW {
+    #[doc = "FTM2_CH1 input"]
+    _0,
+    #[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"]
+    _1,
+}
+impl FTM2CH1SELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FTM2CH1SELW::_0 => false,
+            FTM2CH1SELW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM2CH1SELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM2CH1SELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FTM2CH1SELW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FTM2_CH1 input"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FTM2CH1SELW::_0)
+    }
+    #[doc = "exclusive OR of FTM2_CH0,FTM2_CH1,and FTM1_CH1"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FTM2CH1SELW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FTMGLDOK`"]
+pub enum FTMGLDOKW {
+    #[doc = "FTM Global load mechanism disabled."]
+    _0,
+    #[doc = "FTM Global load mechanism enabled"]
+    _1,
+}
+impl FTMGLDOKW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FTMGLDOKW::_0 => false,
+            FTMGLDOKW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTMGLDOKW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTMGLDOKW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FTMGLDOKW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FTM Global load mechanism disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FTMGLDOKW::_0)
+    }
+    #[doc = "FTM Global load mechanism enabled"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FTMGLDOKW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 15;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FTM0_OUTSEL`"]
+pub enum FTM0_OUTSELW {
+    #[doc = "No modulation with FTM1_CH1"]
+    _00000000,
+    #[doc = "Modulation with FTM1_CH1"]
+    _00000001,
+}
+impl FTM0_OUTSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            FTM0_OUTSELW::_00000000 => 0,
+            FTM0_OUTSELW::_00000001 => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM0_OUTSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM0_OUTSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FTM0_OUTSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No modulation with FTM1_CH1"]
+    #[inline]
+    pub fn _00000000(self) -> &'a mut W {
+        self.variant(FTM0_OUTSELW::_00000000)
+    }
+    #[doc = "Modulation with FTM1_CH1"]
+    #[inline]
+    pub fn _00000001(self) -> &'a mut W {
+        self.variant(FTM0_OUTSELW::_00000001)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FTM3_OUTSEL`"]
+pub enum FTM3_OUTSELW {
+    #[doc = "No modulation with FTM2_CH1"]
+    _00000000,
+    #[doc = "Modulation with FTM2_CH1"]
+    _00000001,
+}
+impl FTM3_OUTSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            FTM3_OUTSELW::_00000000 => 0,
+            FTM3_OUTSELW::_00000001 => 1,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM3_OUTSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM3_OUTSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FTM3_OUTSELW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "No modulation with FTM2_CH1"]
+    #[inline]
+    pub fn _00000000(self) -> &'a mut W {
+        self.variant(FTM3_OUTSELW::_00000000)
+    }
+    #[doc = "Modulation with FTM2_CH1"]
+    #[inline]
+    pub fn _00000001(self) -> &'a mut W {
+        self.variant(FTM3_OUTSELW::_00000001)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - FTM0 Sync Bit"]
+    #[inline]
+    pub fn ftm0syncbit(&self) -> FTM0SYNCBITR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        FTM0SYNCBITR { bits }
+    }
+    #[doc = "Bit 1 - FTM1 Sync Bit"]
+    #[inline]
+    pub fn ftm1syncbit(&self) -> FTM1SYNCBITR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        FTM1SYNCBITR { bits }
+    }
+    #[doc = "Bit 2 - FTM2 Sync Bit"]
+    #[inline]
+    pub fn ftm2syncbit(&self) -> FTM2SYNCBITR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        FTM2SYNCBITR { bits }
+    }
+    #[doc = "Bit 3 - FTM3 Sync Bit"]
+    #[inline]
+    pub fn ftm3syncbit(&self) -> FTM3SYNCBITR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        FTM3SYNCBITR { bits }
+    }
+    #[doc = "Bits 4:5 - FTM1 CH0 Select"]
+    #[inline]
+    pub fn ftm1ch0sel(&self) -> FTM1CH0SELR {
+        FTM1CH0SELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 6:7 - FTM2 CH0 Select"]
+    #[inline]
+    pub fn ftm2ch0sel(&self) -> FTM2CH0SELR {
+        FTM2CH0SELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 8 - FTM2 CH1 Select"]
+    #[inline]
+    pub fn ftm2ch1sel(&self) -> FTM2CH1SELR {
+        FTM2CH1SELR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 15 - FTM global load enable"]
+    #[inline]
+    pub fn ftmgldok(&self) -> FTMGLDOKR {
+        FTMGLDOKR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 15;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 16:23 - FTM0 channel modulation select with FTM1_CH1"]
+    #[inline]
+    pub fn ftm0_outsel(&self) -> FTM0_OUTSELR {
+        FTM0_OUTSELR::_from({
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 24:31 - FTM3 channel modulation select with FTM2_CH1"]
+    #[inline]
+    pub fn ftm3_outsel(&self) -> FTM3_OUTSELR {
+        FTM3_OUTSELR::_from({
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - FTM0 Sync Bit"]
+    #[inline]
+    pub fn ftm0syncbit(&mut self) -> _FTM0SYNCBITW {
+        _FTM0SYNCBITW { w: self }
+    }
+    #[doc = "Bit 1 - FTM1 Sync Bit"]
+    #[inline]
+    pub fn ftm1syncbit(&mut self) -> _FTM1SYNCBITW {
+        _FTM1SYNCBITW { w: self }
+    }
+    #[doc = "Bit 2 - FTM2 Sync Bit"]
+    #[inline]
+    pub fn ftm2syncbit(&mut self) -> _FTM2SYNCBITW {
+        _FTM2SYNCBITW { w: self }
+    }
+    #[doc = "Bit 3 - FTM3 Sync Bit"]
+    #[inline]
+    pub fn ftm3syncbit(&mut self) -> _FTM3SYNCBITW {
+        _FTM3SYNCBITW { w: self }
+    }
+    #[doc = "Bits 4:5 - FTM1 CH0 Select"]
+    #[inline]
+    pub fn ftm1ch0sel(&mut self) -> _FTM1CH0SELW {
+        _FTM1CH0SELW { w: self }
+    }
+    #[doc = "Bits 6:7 - FTM2 CH0 Select"]
+    #[inline]
+    pub fn ftm2ch0sel(&mut self) -> _FTM2CH0SELW {
+        _FTM2CH0SELW { w: self }
+    }
+    #[doc = "Bit 8 - FTM2 CH1 Select"]
+    #[inline]
+    pub fn ftm2ch1sel(&mut self) -> _FTM2CH1SELW {
+        _FTM2CH1SELW { w: self }
+    }
+    #[doc = "Bit 15 - FTM global load enable"]
+    #[inline]
+    pub fn ftmgldok(&mut self) -> _FTMGLDOKW {
+        _FTMGLDOKW { w: self }
+    }
+    #[doc = "Bits 16:23 - FTM0 channel modulation select with FTM1_CH1"]
+    #[inline]
+    pub fn ftm0_outsel(&mut self) -> _FTM0_OUTSELW {
+        _FTM0_OUTSELW { w: self }
+    }
+    #[doc = "Bits 24:31 - FTM3 channel modulation select with FTM2_CH1"]
+    #[inline]
+    pub fn ftm3_outsel(&mut self) -> _FTM3_OUTSELW {
+        _FTM3_OUTSELW { w: self }
+    }
+}

src/sim/lpoclks/mod.rs

@@ -0,0 +1,572 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::LPOCLKS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `LPO1KCLKEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LPO1KCLKENR {
+    #[doc = "Disable 1 kHz LPO_CLK output"]
+    _0,
+    #[doc = "Enable 1 kHz LPO_CLK output"]
+    _1,
+}
+impl LPO1KCLKENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LPO1KCLKENR::_0 => false,
+            LPO1KCLKENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LPO1KCLKENR {
+        match value {
+            false => LPO1KCLKENR::_0,
+            true => LPO1KCLKENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == LPO1KCLKENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == LPO1KCLKENR::_1
+    }
+}
+#[doc = "Possible values of the field `LPO32KCLKEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LPO32KCLKENR {
+    #[doc = "Disable 32 kHz LPO_CLK output"]
+    _0,
+    #[doc = "Enable 32 kHz LPO_CLK output"]
+    _1,
+}
+impl LPO32KCLKENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LPO32KCLKENR::_0 => false,
+            LPO32KCLKENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LPO32KCLKENR {
+        match value {
+            false => LPO32KCLKENR::_0,
+            true => LPO32KCLKENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == LPO32KCLKENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == LPO32KCLKENR::_1
+    }
+}
+#[doc = "Possible values of the field `LPOCLKSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LPOCLKSELR {
+    #[doc = "128 kHz LPO_CLK"]
+    _00,
+    #[doc = "No clock"]
+    _01,
+    #[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
+    _10,
+    #[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
+    _11,
+}
+impl LPOCLKSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            LPOCLKSELR::_00 => 0,
+            LPOCLKSELR::_01 => 1,
+            LPOCLKSELR::_10 => 2,
+            LPOCLKSELR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> LPOCLKSELR {
+        match value {
+            0 => LPOCLKSELR::_00,
+            1 => LPOCLKSELR::_01,
+            2 => LPOCLKSELR::_10,
+            3 => LPOCLKSELR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == LPOCLKSELR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == LPOCLKSELR::_01
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == LPOCLKSELR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == LPOCLKSELR::_11
+    }
+}
+#[doc = "Possible values of the field `RTCCLKSEL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RTCCLKSELR {
+    #[doc = "SOSCDIV1_CLK"]
+    _00,
+    #[doc = "32 kHz LPO_CLK"]
+    _01,
+    #[doc = "RTC_CLKIN clock"]
+    _10,
+    #[doc = "FIRCDIV1_CLK"]
+    _11,
+}
+impl RTCCLKSELR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            RTCCLKSELR::_00 => 0,
+            RTCCLKSELR::_01 => 1,
+            RTCCLKSELR::_10 => 2,
+            RTCCLKSELR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> RTCCLKSELR {
+        match value {
+            0 => RTCCLKSELR::_00,
+            1 => RTCCLKSELR::_01,
+            2 => RTCCLKSELR::_10,
+            3 => RTCCLKSELR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == RTCCLKSELR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == RTCCLKSELR::_01
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == RTCCLKSELR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == RTCCLKSELR::_11
+    }
+}
+#[doc = "Values that can be written to the field `LPO1KCLKEN`"]
+pub enum LPO1KCLKENW {
+    #[doc = "Disable 1 kHz LPO_CLK output"]
+    _0,
+    #[doc = "Enable 1 kHz LPO_CLK output"]
+    _1,
+}
+impl LPO1KCLKENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            LPO1KCLKENW::_0 => false,
+            LPO1KCLKENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LPO1KCLKENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LPO1KCLKENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LPO1KCLKENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable 1 kHz LPO_CLK output"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(LPO1KCLKENW::_0)
+    }
+    #[doc = "Enable 1 kHz LPO_CLK output"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(LPO1KCLKENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `LPO32KCLKEN`"]
+pub enum LPO32KCLKENW {
+    #[doc = "Disable 32 kHz LPO_CLK output"]
+    _0,
+    #[doc = "Enable 32 kHz LPO_CLK output"]
+    _1,
+}
+impl LPO32KCLKENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            LPO32KCLKENW::_0 => false,
+            LPO32KCLKENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LPO32KCLKENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LPO32KCLKENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LPO32KCLKENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable 32 kHz LPO_CLK output"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(LPO32KCLKENW::_0)
+    }
+    #[doc = "Enable 32 kHz LPO_CLK output"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(LPO32KCLKENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `LPOCLKSEL`"]
+pub enum LPOCLKSELW {
+    #[doc = "128 kHz LPO_CLK"]
+    _00,
+    #[doc = "No clock"]
+    _01,
+    #[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
+    _10,
+    #[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
+    _11,
+}
+impl LPOCLKSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            LPOCLKSELW::_00 => 0,
+            LPOCLKSELW::_01 => 1,
+            LPOCLKSELW::_10 => 2,
+            LPOCLKSELW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LPOCLKSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LPOCLKSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LPOCLKSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "128 kHz LPO_CLK"]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(LPOCLKSELW::_00)
+    }
+    #[doc = "No clock"]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(LPOCLKSELW::_01)
+    }
+    #[doc = "32 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(LPOCLKSELW::_10)
+    }
+    #[doc = "1 kHz LPO_CLK which is derived from the 128 kHz LPO_CLK"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(LPOCLKSELW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `RTCCLKSEL`"]
+pub enum RTCCLKSELW {
+    #[doc = "SOSCDIV1_CLK"]
+    _00,
+    #[doc = "32 kHz LPO_CLK"]
+    _01,
+    #[doc = "RTC_CLKIN clock"]
+    _10,
+    #[doc = "FIRCDIV1_CLK"]
+    _11,
+}
+impl RTCCLKSELW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            RTCCLKSELW::_00 => 0,
+            RTCCLKSELW::_01 => 1,
+            RTCCLKSELW::_10 => 2,
+            RTCCLKSELW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _RTCCLKSELW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _RTCCLKSELW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: RTCCLKSELW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "SOSCDIV1_CLK"]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(RTCCLKSELW::_00)
+    }
+    #[doc = "32 kHz LPO_CLK"]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(RTCCLKSELW::_01)
+    }
+    #[doc = "RTC_CLKIN clock"]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(RTCCLKSELW::_10)
+    }
+    #[doc = "FIRCDIV1_CLK"]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(RTCCLKSELW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - 1 kHz LPO_CLK enable"]
+    #[inline]
+    pub fn lpo1kclken(&self) -> LPO1KCLKENR {
+        LPO1KCLKENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - 32 kHz LPO_CLK enable"]
+    #[inline]
+    pub fn lpo32kclken(&self) -> LPO32KCLKENR {
+        LPO32KCLKENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 2:3 - LPO clock source select"]
+    #[inline]
+    pub fn lpoclksel(&self) -> LPOCLKSELR {
+        LPOCLKSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 4:5 - 32 kHz clock source select"]
+    #[inline]
+    pub fn rtcclksel(&self) -> RTCCLKSELR {
+        RTCCLKSELR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 3 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - 1 kHz LPO_CLK enable"]
+    #[inline]
+    pub fn lpo1kclken(&mut self) -> _LPO1KCLKENW {
+        _LPO1KCLKENW { w: self }
+    }
+    #[doc = "Bit 1 - 32 kHz LPO_CLK enable"]
+    #[inline]
+    pub fn lpo32kclken(&mut self) -> _LPO32KCLKENW {
+        _LPO32KCLKENW { w: self }
+    }
+    #[doc = "Bits 2:3 - LPO clock source select"]
+    #[inline]
+    pub fn lpoclksel(&mut self) -> _LPOCLKSELW {
+        _LPOCLKSELW { w: self }
+    }
+    #[doc = "Bits 4:5 - 32 kHz clock source select"]
+    #[inline]
+    pub fn rtcclksel(&mut self) -> _RTCCLKSELW {
+        _RTCCLKSELW { w: self }
+    }
+}

src/sim/misctrl0/mod.rs

@@ -0,0 +1,538 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::MISCTRL0 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `FTM0_OBE_CTRL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FTM0_OBE_CTRLR {
+    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
+    _0,
+    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
+    _1,
+}
+impl FTM0_OBE_CTRLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FTM0_OBE_CTRLR::_0 => false,
+            FTM0_OBE_CTRLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FTM0_OBE_CTRLR {
+        match value {
+            false => FTM0_OBE_CTRLR::_0,
+            true => FTM0_OBE_CTRLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FTM0_OBE_CTRLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FTM0_OBE_CTRLR::_1
+    }
+}
+#[doc = "Possible values of the field `FTM1_OBE_CTRL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FTM1_OBE_CTRLR {
+    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
+    _0,
+    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
+    _1,
+}
+impl FTM1_OBE_CTRLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FTM1_OBE_CTRLR::_0 => false,
+            FTM1_OBE_CTRLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FTM1_OBE_CTRLR {
+        match value {
+            false => FTM1_OBE_CTRLR::_0,
+            true => FTM1_OBE_CTRLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FTM1_OBE_CTRLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FTM1_OBE_CTRLR::_1
+    }
+}
+#[doc = "Possible values of the field `FTM2_OBE_CTRL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FTM2_OBE_CTRLR {
+    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
+    _0,
+    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
+    _1,
+}
+impl FTM2_OBE_CTRLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FTM2_OBE_CTRLR::_0 => false,
+            FTM2_OBE_CTRLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FTM2_OBE_CTRLR {
+        match value {
+            false => FTM2_OBE_CTRLR::_0,
+            true => FTM2_OBE_CTRLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FTM2_OBE_CTRLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FTM2_OBE_CTRLR::_1
+    }
+}
+#[doc = "Possible values of the field `FTM3_OBE_CTRL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FTM3_OBE_CTRLR {
+    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
+    _0,
+    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
+    _1,
+}
+impl FTM3_OBE_CTRLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FTM3_OBE_CTRLR::_0 => false,
+            FTM3_OBE_CTRLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FTM3_OBE_CTRLR {
+        match value {
+            false => FTM3_OBE_CTRLR::_0,
+            true => FTM3_OBE_CTRLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FTM3_OBE_CTRLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FTM3_OBE_CTRLR::_1
+    }
+}
+#[doc = "Values that can be written to the field `FTM0_OBE_CTRL`"]
+pub enum FTM0_OBE_CTRLW {
+    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
+    _0,
+    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
+    _1,
+}
+impl FTM0_OBE_CTRLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FTM0_OBE_CTRLW::_0 => false,
+            FTM0_OBE_CTRLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM0_OBE_CTRLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM0_OBE_CTRLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FTM0_OBE_CTRLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FTM0_OBE_CTRLW::_0)
+    }
+    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FTM0_OBE_CTRLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FTM1_OBE_CTRL`"]
+pub enum FTM1_OBE_CTRLW {
+    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
+    _0,
+    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
+    _1,
+}
+impl FTM1_OBE_CTRLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FTM1_OBE_CTRLW::_0 => false,
+            FTM1_OBE_CTRLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM1_OBE_CTRLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM1_OBE_CTRLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FTM1_OBE_CTRLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FTM1_OBE_CTRLW::_0)
+    }
+    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FTM1_OBE_CTRLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 17;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FTM2_OBE_CTRL`"]
+pub enum FTM2_OBE_CTRLW {
+    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
+    _0,
+    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
+    _1,
+}
+impl FTM2_OBE_CTRLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FTM2_OBE_CTRLW::_0 => false,
+            FTM2_OBE_CTRLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM2_OBE_CTRLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM2_OBE_CTRLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FTM2_OBE_CTRLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FTM2_OBE_CTRLW::_0)
+    }
+    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FTM2_OBE_CTRLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 18;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FTM3_OBE_CTRL`"]
+pub enum FTM3_OBE_CTRLW {
+    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
+    _0,
+    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
+    _1,
+}
+impl FTM3_OBE_CTRLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FTM3_OBE_CTRLW::_0 => false,
+            FTM3_OBE_CTRLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTM3_OBE_CTRLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTM3_OBE_CTRLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FTM3_OBE_CTRLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The FTM channel output is put to safe state when the FTM counter is enabled and the FTM channel output is enabled by Fault Control (FTM_MODE[FAULTM]!=2'b00 and FTM_FLTCTRL[FSTATE]=1'b0) and PWM is enabled (FTM_SC[PWMENn] = 1'b1). Otherwise the channel output is tristated."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FTM3_OBE_CTRLW::_0)
+    }
+    #[doc = "The FTM channel output state is retained when the channel is in output mode. The output channel is tristated when the channel is in input capture [DECAPEN=1'b0, COMBINE=1'b0, MSnB:MSnA=2'b00] or dual edge capture mode [DECAPEN=1'b1]."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FTM3_OBE_CTRLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 19;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 16 - FTM0 OBE CTRL bit"]
+    #[inline]
+    pub fn ftm0_obe_ctrl(&self) -> FTM0_OBE_CTRLR {
+        FTM0_OBE_CTRLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 17 - FTM1 OBE CTRL bit"]
+    #[inline]
+    pub fn ftm1_obe_ctrl(&self) -> FTM1_OBE_CTRLR {
+        FTM1_OBE_CTRLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 17;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 18 - FTM2 OBE CTRL bit"]
+    #[inline]
+    pub fn ftm2_obe_ctrl(&self) -> FTM2_OBE_CTRLR {
+        FTM2_OBE_CTRLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 18;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 19 - FTM3 OBE CTRL bit"]
+    #[inline]
+    pub fn ftm3_obe_ctrl(&self) -> FTM3_OBE_CTRLR {
+        FTM3_OBE_CTRLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 19;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 16 - FTM0 OBE CTRL bit"]
+    #[inline]
+    pub fn ftm0_obe_ctrl(&mut self) -> _FTM0_OBE_CTRLW {
+        _FTM0_OBE_CTRLW { w: self }
+    }
+    #[doc = "Bit 17 - FTM1 OBE CTRL bit"]
+    #[inline]
+    pub fn ftm1_obe_ctrl(&mut self) -> _FTM1_OBE_CTRLW {
+        _FTM1_OBE_CTRLW { w: self }
+    }
+    #[doc = "Bit 18 - FTM2 OBE CTRL bit"]
+    #[inline]
+    pub fn ftm2_obe_ctrl(&mut self) -> _FTM2_OBE_CTRLW {
+        _FTM2_OBE_CTRLW { w: self }
+    }
+    #[doc = "Bit 19 - FTM3 OBE CTRL bit"]
+    #[inline]
+    pub fn ftm3_obe_ctrl(&mut self) -> _FTM3_OBE_CTRLW {
+        _FTM3_OBE_CTRLW { w: self }
+    }
+}

src/sim/misctrl1/mod.rs

@@ -0,0 +1,121 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::MISCTRL1 {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SW_TRGR {
+    bits: bool,
+}
+impl SW_TRGR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SW_TRGW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SW_TRGW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity)."]
+    #[inline]
+    pub fn sw_trg(&self) -> SW_TRGR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        SW_TRGR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity)."]
+    #[inline]
+    pub fn sw_trg(&mut self) -> _SW_TRGW {
+        _SW_TRGW { w: self }
+    }
+}

src/sim/mod.rs

@@ -0,0 +1,132 @@
+use vcell::VolatileCell;
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    _reserved0: [u8; 4usize],
+    #[doc = "0x04 - Chip Control register"]
+    pub chipctl: CHIPCTL,
+    _reserved1: [u8; 4usize],
+    #[doc = "0x0c - FTM Option Register 0"]
+    pub ftmopt0: FTMOPT0,
+    #[doc = "0x10 - LPO Clock Select Register"]
+    pub lpoclks: LPOCLKS,
+    _reserved2: [u8; 4usize],
+    #[doc = "0x18 - ADC Options Register"]
+    pub adcopt: ADCOPT,
+    #[doc = "0x1c - FTM Option Register 1"]
+    pub ftmopt1: FTMOPT1,
+    #[doc = "0x20 - Miscellaneous control register 0"]
+    pub misctrl0: MISCTRL0,
+    #[doc = "0x24 - System Device Identification Register"]
+    pub sdid: SDID,
+    _reserved3: [u8; 24usize],
+    #[doc = "0x40 - Platform Clock Gating Control Register"]
+    pub platcgc: PLATCGC,
+    _reserved4: [u8; 8usize],
+    #[doc = "0x4c - Flash Configuration Register 1"]
+    pub fcfg1: FCFG1,
+    _reserved5: [u8; 4usize],
+    #[doc = "0x54 - Unique Identification Register High"]
+    pub uidh: UIDH,
+    #[doc = "0x58 - Unique Identification Register Mid-High"]
+    pub uidmh: UIDMH,
+    #[doc = "0x5c - Unique Identification Register Mid Low"]
+    pub uidml: UIDML,
+    #[doc = "0x60 - Unique Identification Register Low"]
+    pub uidl: UIDL,
+    _reserved6: [u8; 4usize],
+    #[doc = "0x68 - System Clock Divider Register 4"]
+    pub clkdiv4: CLKDIV4,
+    #[doc = "0x6c - Miscellaneous Control register 1"]
+    pub misctrl1: MISCTRL1,
+}
+#[doc = "Chip Control register"]
+pub struct CHIPCTL {
+    register: VolatileCell<u32>,
+}
+#[doc = "Chip Control register"]
+pub mod chipctl;
+#[doc = "FTM Option Register 0"]
+pub struct FTMOPT0 {
+    register: VolatileCell<u32>,
+}
+#[doc = "FTM Option Register 0"]
+pub mod ftmopt0;
+#[doc = "LPO Clock Select Register"]
+pub struct LPOCLKS {
+    register: VolatileCell<u32>,
+}
+#[doc = "LPO Clock Select Register"]
+pub mod lpoclks;
+#[doc = "ADC Options Register"]
+pub struct ADCOPT {
+    register: VolatileCell<u32>,
+}
+#[doc = "ADC Options Register"]
+pub mod adcopt;
+#[doc = "FTM Option Register 1"]
+pub struct FTMOPT1 {
+    register: VolatileCell<u32>,
+}
+#[doc = "FTM Option Register 1"]
+pub mod ftmopt1;
+#[doc = "Miscellaneous control register 0"]
+pub struct MISCTRL0 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Miscellaneous control register 0"]
+pub mod misctrl0;
+#[doc = "System Device Identification Register"]
+pub struct SDID {
+    register: VolatileCell<u32>,
+}
+#[doc = "System Device Identification Register"]
+pub mod sdid;
+#[doc = "Platform Clock Gating Control Register"]
+pub struct PLATCGC {
+    register: VolatileCell<u32>,
+}
+#[doc = "Platform Clock Gating Control Register"]
+pub mod platcgc;
+#[doc = "Flash Configuration Register 1"]
+pub struct FCFG1 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Flash Configuration Register 1"]
+pub mod fcfg1;
+#[doc = "Unique Identification Register High"]
+pub struct UIDH {
+    register: VolatileCell<u32>,
+}
+#[doc = "Unique Identification Register High"]
+pub mod uidh;
+#[doc = "Unique Identification Register Mid-High"]
+pub struct UIDMH {
+    register: VolatileCell<u32>,
+}
+#[doc = "Unique Identification Register Mid-High"]
+pub mod uidmh;
+#[doc = "Unique Identification Register Mid Low"]
+pub struct UIDML {
+    register: VolatileCell<u32>,
+}
+#[doc = "Unique Identification Register Mid Low"]
+pub mod uidml;
+#[doc = "Unique Identification Register Low"]
+pub struct UIDL {
+    register: VolatileCell<u32>,
+}
+#[doc = "Unique Identification Register Low"]
+pub mod uidl;
+#[doc = "System Clock Divider Register 4"]
+pub struct CLKDIV4 {
+    register: VolatileCell<u32>,
+}
+#[doc = "System Clock Divider Register 4"]
+pub mod clkdiv4;
+#[doc = "Miscellaneous Control register 1"]
+pub struct MISCTRL1 {
+    register: VolatileCell<u32>,
+}
+#[doc = "Miscellaneous Control register 1"]
+pub mod misctrl1;

src/sim/platcgc/mod.rs

@@ -0,0 +1,657 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PLATCGC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `CGCMSCM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CGCMSCMR {
+    #[doc = "Clock disabled"]
+    _0,
+    #[doc = "Clock enabled"]
+    _1,
+}
+impl CGCMSCMR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CGCMSCMR::_0 => false,
+            CGCMSCMR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CGCMSCMR {
+        match value {
+            false => CGCMSCMR::_0,
+            true => CGCMSCMR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CGCMSCMR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CGCMSCMR::_1
+    }
+}
+#[doc = "Possible values of the field `CGCMPU`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CGCMPUR {
+    #[doc = "Clock disabled"]
+    _0,
+    #[doc = "Clock enabled"]
+    _1,
+}
+impl CGCMPUR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CGCMPUR::_0 => false,
+            CGCMPUR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CGCMPUR {
+        match value {
+            false => CGCMPUR::_0,
+            true => CGCMPUR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CGCMPUR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CGCMPUR::_1
+    }
+}
+#[doc = "Possible values of the field `CGCDMA`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CGCDMAR {
+    #[doc = "Clock disabled"]
+    _0,
+    #[doc = "Clock enabled"]
+    _1,
+}
+impl CGCDMAR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CGCDMAR::_0 => false,
+            CGCDMAR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CGCDMAR {
+        match value {
+            false => CGCDMAR::_0,
+            true => CGCDMAR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CGCDMAR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CGCDMAR::_1
+    }
+}
+#[doc = "Possible values of the field `CGCERM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CGCERMR {
+    #[doc = "Clock disabled"]
+    _0,
+    #[doc = "Clock enabled"]
+    _1,
+}
+impl CGCERMR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CGCERMR::_0 => false,
+            CGCERMR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CGCERMR {
+        match value {
+            false => CGCERMR::_0,
+            true => CGCERMR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CGCERMR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CGCERMR::_1
+    }
+}
+#[doc = "Possible values of the field `CGCEIM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CGCEIMR {
+    #[doc = "Clock disabled"]
+    _0,
+    #[doc = "Clock enabled"]
+    _1,
+}
+impl CGCEIMR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CGCEIMR::_0 => false,
+            CGCEIMR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CGCEIMR {
+        match value {
+            false => CGCEIMR::_0,
+            true => CGCEIMR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CGCEIMR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CGCEIMR::_1
+    }
+}
+#[doc = "Values that can be written to the field `CGCMSCM`"]
+pub enum CGCMSCMW {
+    #[doc = "Clock disabled"]
+    _0,
+    #[doc = "Clock enabled"]
+    _1,
+}
+impl CGCMSCMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CGCMSCMW::_0 => false,
+            CGCMSCMW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CGCMSCMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CGCMSCMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CGCMSCMW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Clock disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CGCMSCMW::_0)
+    }
+    #[doc = "Clock enabled"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CGCMSCMW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CGCMPU`"]
+pub enum CGCMPUW {
+    #[doc = "Clock disabled"]
+    _0,
+    #[doc = "Clock enabled"]
+    _1,
+}
+impl CGCMPUW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CGCMPUW::_0 => false,
+            CGCMPUW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CGCMPUW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CGCMPUW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CGCMPUW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Clock disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CGCMPUW::_0)
+    }
+    #[doc = "Clock enabled"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CGCMPUW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CGCDMA`"]
+pub enum CGCDMAW {
+    #[doc = "Clock disabled"]
+    _0,
+    #[doc = "Clock enabled"]
+    _1,
+}
+impl CGCDMAW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CGCDMAW::_0 => false,
+            CGCDMAW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CGCDMAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CGCDMAW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CGCDMAW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Clock disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CGCDMAW::_0)
+    }
+    #[doc = "Clock enabled"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CGCDMAW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CGCERM`"]
+pub enum CGCERMW {
+    #[doc = "Clock disabled"]
+    _0,
+    #[doc = "Clock enabled"]
+    _1,
+}
+impl CGCERMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CGCERMW::_0 => false,
+            CGCERMW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CGCERMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CGCERMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CGCERMW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Clock disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CGCERMW::_0)
+    }
+    #[doc = "Clock enabled"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CGCERMW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CGCEIM`"]
+pub enum CGCEIMW {
+    #[doc = "Clock disabled"]
+    _0,
+    #[doc = "Clock enabled"]
+    _1,
+}
+impl CGCEIMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CGCEIMW::_0 => false,
+            CGCEIMW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CGCEIMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CGCEIMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CGCEIMW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Clock disabled"]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CGCEIMW::_0)
+    }
+    #[doc = "Clock enabled"]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CGCEIMW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - MSCM Clock Gating Control"]
+    #[inline]
+    pub fn cgcmscm(&self) -> CGCMSCMR {
+        CGCMSCMR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - MPU Clock Gating Control"]
+    #[inline]
+    pub fn cgcmpu(&self) -> CGCMPUR {
+        CGCMPUR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - DMA Clock Gating Control"]
+    #[inline]
+    pub fn cgcdma(&self) -> CGCDMAR {
+        CGCDMAR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - ERM Clock Gating Control"]
+    #[inline]
+    pub fn cgcerm(&self) -> CGCERMR {
+        CGCERMR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - EIM Clock Gating Control"]
+    #[inline]
+    pub fn cgceim(&self) -> CGCEIMR {
+        CGCEIMR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 31 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - MSCM Clock Gating Control"]
+    #[inline]
+    pub fn cgcmscm(&mut self) -> _CGCMSCMW {
+        _CGCMSCMW { w: self }
+    }
+    #[doc = "Bit 1 - MPU Clock Gating Control"]
+    #[inline]
+    pub fn cgcmpu(&mut self) -> _CGCMPUW {
+        _CGCMPUW { w: self }
+    }
+    #[doc = "Bit 2 - DMA Clock Gating Control"]
+    #[inline]
+    pub fn cgcdma(&mut self) -> _CGCDMAW {
+        _CGCDMAW { w: self }
+    }
+    #[doc = "Bit 3 - ERM Clock Gating Control"]
+    #[inline]
+    pub fn cgcerm(&mut self) -> _CGCERMW {
+        _CGCERMW { w: self }
+    }
+    #[doc = "Bit 4 - EIM Clock Gating Control"]
+    #[inline]
+    pub fn cgceim(&mut self) -> _CGCEIMW {
+        _CGCEIMW { w: self }
+    }
+}

src/sim/sdid/mod.rs

@@ -0,0 +1,286 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::SDID {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct FEATURESR {
+    bits: u8,
+}
+impl FEATURESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `PACKAGE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PACKAGER {
+    #[doc = "48 LQFP"]
+    _0010,
+    #[doc = "64 LQFP"]
+    _0011,
+    #[doc = "100 LQFP"]
+    _0100,
+    #[doc = "144 LQFP"]
+    _0110,
+    #[doc = "176 LQFP"]
+    _0111,
+    #[doc = "100 MAP BGA"]
+    _1000,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl PACKAGER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            PACKAGER::_0010 => 2,
+            PACKAGER::_0011 => 3,
+            PACKAGER::_0100 => 4,
+            PACKAGER::_0110 => 6,
+            PACKAGER::_0111 => 7,
+            PACKAGER::_1000 => 8,
+            PACKAGER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> PACKAGER {
+        match value {
+            2 => PACKAGER::_0010,
+            3 => PACKAGER::_0011,
+            4 => PACKAGER::_0100,
+            6 => PACKAGER::_0110,
+            7 => PACKAGER::_0111,
+            8 => PACKAGER::_1000,
+            i => PACKAGER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0010`"]
+    #[inline]
+    pub fn is_0010(&self) -> bool {
+        *self == PACKAGER::_0010
+    }
+    #[doc = "Checks if the value of the field is `_0011`"]
+    #[inline]
+    pub fn is_0011(&self) -> bool {
+        *self == PACKAGER::_0011
+    }
+    #[doc = "Checks if the value of the field is `_0100`"]
+    #[inline]
+    pub fn is_0100(&self) -> bool {
+        *self == PACKAGER::_0100
+    }
+    #[doc = "Checks if the value of the field is `_0110`"]
+    #[inline]
+    pub fn is_0110(&self) -> bool {
+        *self == PACKAGER::_0110
+    }
+    #[doc = "Checks if the value of the field is `_0111`"]
+    #[inline]
+    pub fn is_0111(&self) -> bool {
+        *self == PACKAGER::_0111
+    }
+    #[doc = "Checks if the value of the field is `_1000`"]
+    #[inline]
+    pub fn is_1000(&self) -> bool {
+        *self == PACKAGER::_1000
+    }
+}
+#[doc = r" Value of the field"]
+pub struct REVIDR {
+    bits: u8,
+}
+impl REVIDR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `RAMSIZE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum RAMSIZER {
+    #[doc = "128 KB (S32K148), Reserved (others)"]
+    _0111,
+    #[doc = "160 KB (S32K148) , Reserved (others)"]
+    _1001,
+    #[doc = "192 KB (S32K148), 16 KB (S32K142), Reserved (others)"]
+    _1011,
+    #[doc = "48 KB (S32K144), 24 KB (S32K142), Reserved (others)"]
+    _1101,
+    #[doc = "256 KB (S32K148), 64 KB (S32K144), 32 KB (S32K142)"]
+    _1111,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl RAMSIZER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            RAMSIZER::_0111 => 7,
+            RAMSIZER::_1001 => 9,
+            RAMSIZER::_1011 => 11,
+            RAMSIZER::_1101 => 13,
+            RAMSIZER::_1111 => 15,
+            RAMSIZER::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> RAMSIZER {
+        match value {
+            7 => RAMSIZER::_0111,
+            9 => RAMSIZER::_1001,
+            11 => RAMSIZER::_1011,
+            13 => RAMSIZER::_1101,
+            15 => RAMSIZER::_1111,
+            i => RAMSIZER::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0111`"]
+    #[inline]
+    pub fn is_0111(&self) -> bool {
+        *self == RAMSIZER::_0111
+    }
+    #[doc = "Checks if the value of the field is `_1001`"]
+    #[inline]
+    pub fn is_1001(&self) -> bool {
+        *self == RAMSIZER::_1001
+    }
+    #[doc = "Checks if the value of the field is `_1011`"]
+    #[inline]
+    pub fn is_1011(&self) -> bool {
+        *self == RAMSIZER::_1011
+    }
+    #[doc = "Checks if the value of the field is `_1101`"]
+    #[inline]
+    pub fn is_1101(&self) -> bool {
+        *self == RAMSIZER::_1101
+    }
+    #[doc = "Checks if the value of the field is `_1111`"]
+    #[inline]
+    pub fn is_1111(&self) -> bool {
+        *self == RAMSIZER::_1111
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DERIVATER {
+    bits: u8,
+}
+impl DERIVATER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct SUBSERIESR {
+    bits: u8,
+}
+impl SUBSERIESR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct GENERATIONR {
+    bits: u8,
+}
+impl GENERATIONR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Features"]
+    #[inline]
+    pub fn features(&self) -> FEATURESR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        FEATURESR { bits }
+    }
+    #[doc = "Bits 8:11 - Package"]
+    #[inline]
+    pub fn package(&self) -> PACKAGER {
+        PACKAGER::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 12:15 - Device revision number"]
+    #[inline]
+    pub fn revid(&self) -> REVIDR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        REVIDR { bits }
+    }
+    #[doc = "Bits 16:19 - RAM size"]
+    #[inline]
+    pub fn ramsize(&self) -> RAMSIZER {
+        RAMSIZER::_from({
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 20:23 - Derivate"]
+    #[inline]
+    pub fn derivate(&self) -> DERIVATER {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 20;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DERIVATER { bits }
+    }
+    #[doc = "Bits 24:27 - Subseries"]
+    #[inline]
+    pub fn subseries(&self) -> SUBSERIESR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        SUBSERIESR { bits }
+    }
+    #[doc = "Bits 28:31 - S32K product series generation"]
+    #[inline]
+    pub fn generation(&self) -> GENERATIONR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 28;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        GENERATIONR { bits }
+    }
+}

src/sim/uidh/mod.rs

@@ -0,0 +1,39 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::UIDH {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UID127_96R {
+    bits: u32,
+}
+impl UID127_96R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Unique Identification"]
+    #[inline]
+    pub fn uid127_96(&self) -> UID127_96R {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        UID127_96R { bits }
+    }
+}

src/sim/uidl/mod.rs

@@ -0,0 +1,39 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::UIDL {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UID31_0R {
+    bits: u32,
+}
+impl UID31_0R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Unique Identification"]
+    #[inline]
+    pub fn uid31_0(&self) -> UID31_0R {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        UID31_0R { bits }
+    }
+}

src/sim/uidmh/mod.rs

@@ -0,0 +1,39 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::UIDMH {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UID95_64R {
+    bits: u32,
+}
+impl UID95_64R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Unique Identification"]
+    #[inline]
+    pub fn uid95_64(&self) -> UID95_64R {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        UID95_64R { bits }
+    }
+}

src/sim/uidml/mod.rs

@@ -0,0 +1,39 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::UIDML {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+}
+#[doc = r" Value of the field"]
+pub struct UID63_32R {
+    bits: u32,
+}
+impl UID63_32R {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Unique Identification"]
+    #[inline]
+    pub fn uid63_32(&self) -> UID63_32R {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        UID63_32R { bits }
+    }
+}