Same as last commit just run through the form tool (splits up large lib.rs files)
This commit is contained in:
Kjetil Kjeka
769
src/scg/sosccsr/mod.rs
Normal file
769
src/scg/sosccsr/mod.rs
Normal file
@ -0,0 +1,769 @@
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#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::SOSCCSR {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `SOSCEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SOSCENR {
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#[doc = "System OSC is disabled"]
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_0,
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#[doc = "System OSC is enabled"]
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_1,
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}
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impl SOSCENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SOSCENR::_0 => false,
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SOSCENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SOSCENR {
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match value {
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false => SOSCENR::_0,
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true => SOSCENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SOSCENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SOSCENR::_1
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}
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}
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#[doc = "Possible values of the field `SOSCCM`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SOSCCMR {
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#[doc = "System OSC Clock Monitor is disabled"]
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_0,
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#[doc = "System OSC Clock Monitor is enabled"]
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_1,
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}
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impl SOSCCMR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SOSCCMR::_0 => false,
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SOSCCMR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SOSCCMR {
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match value {
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false => SOSCCMR::_0,
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true => SOSCCMR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SOSCCMR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SOSCCMR::_1
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}
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}
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#[doc = "Possible values of the field `SOSCCMRE`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SOSCCMRER {
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#[doc = "Clock Monitor generates interrupt when error detected"]
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_0,
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#[doc = "Clock Monitor generates reset when error detected"]
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_1,
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}
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impl SOSCCMRER {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SOSCCMRER::_0 => false,
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SOSCCMRER::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SOSCCMRER {
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match value {
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false => SOSCCMRER::_0,
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true => SOSCCMRER::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SOSCCMRER::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SOSCCMRER::_1
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}
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}
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#[doc = "Possible values of the field `LK`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum LKR {
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#[doc = "This Control Status Register can be written."]
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_0,
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#[doc = "This Control Status Register cannot be written."]
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_1,
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}
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impl LKR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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LKR::_0 => false,
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LKR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> LKR {
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match value {
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false => LKR::_0,
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true => LKR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == LKR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == LKR::_1
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}
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}
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#[doc = "Possible values of the field `SOSCVLD`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SOSCVLDR {
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#[doc = "System OSC is not enabled or clock is not valid"]
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_0,
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#[doc = "System OSC is enabled and output clock is valid"]
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_1,
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}
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impl SOSCVLDR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SOSCVLDR::_0 => false,
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SOSCVLDR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SOSCVLDR {
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match value {
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false => SOSCVLDR::_0,
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true => SOSCVLDR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SOSCVLDR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SOSCVLDR::_1
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}
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}
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#[doc = "Possible values of the field `SOSCSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SOSCSELR {
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#[doc = "System OSC is not the system clock source"]
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_0,
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#[doc = "System OSC is the system clock source"]
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_1,
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}
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impl SOSCSELR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SOSCSELR::_0 => false,
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SOSCSELR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SOSCSELR {
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match value {
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false => SOSCSELR::_0,
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true => SOSCSELR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SOSCSELR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SOSCSELR::_1
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}
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}
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#[doc = "Possible values of the field `SOSCERR`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SOSCERRR {
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#[doc = "System OSC Clock Monitor is disabled or has not detected an error"]
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_0,
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#[doc = "System OSC Clock Monitor is enabled and detected an error"]
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_1,
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}
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impl SOSCERRR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SOSCERRR::_0 => false,
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SOSCERRR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SOSCERRR {
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match value {
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false => SOSCERRR::_0,
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true => SOSCERRR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SOSCERRR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SOSCERRR::_1
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}
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}
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#[doc = "Values that can be written to the field `SOSCEN`"]
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pub enum SOSCENW {
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#[doc = "System OSC is disabled"]
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_0,
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#[doc = "System OSC is enabled"]
|
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_1,
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}
|
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impl SOSCENW {
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#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
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#[inline]
|
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pub fn _bits(&self) -> bool {
|
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match *self {
|
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SOSCENW::_0 => false,
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SOSCENW::_1 => true,
|
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}
|
||||
}
|
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}
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#[doc = r" Proxy"]
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pub struct _SOSCENW<'a> {
|
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w: &'a mut W,
|
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}
|
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impl<'a> _SOSCENW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
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pub fn variant(self, variant: SOSCENW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "System OSC is disabled"]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(SOSCENW::_0)
|
||||
}
|
||||
#[doc = "System OSC is enabled"]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(SOSCENW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SOSCCM`"]
|
||||
pub enum SOSCCMW {
|
||||
#[doc = "System OSC Clock Monitor is disabled"]
|
||||
_0,
|
||||
#[doc = "System OSC Clock Monitor is enabled"]
|
||||
_1,
|
||||
}
|
||||
impl SOSCCMW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
SOSCCMW::_0 => false,
|
||||
SOSCCMW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _SOSCCMW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _SOSCCMW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: SOSCCMW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "System OSC Clock Monitor is disabled"]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(SOSCCMW::_0)
|
||||
}
|
||||
#[doc = "System OSC Clock Monitor is enabled"]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(SOSCCMW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 16;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SOSCCMRE`"]
|
||||
pub enum SOSCCMREW {
|
||||
#[doc = "Clock Monitor generates interrupt when error detected"]
|
||||
_0,
|
||||
#[doc = "Clock Monitor generates reset when error detected"]
|
||||
_1,
|
||||
}
|
||||
impl SOSCCMREW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
SOSCCMREW::_0 => false,
|
||||
SOSCCMREW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _SOSCCMREW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _SOSCCMREW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: SOSCCMREW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Clock Monitor generates interrupt when error detected"]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(SOSCCMREW::_0)
|
||||
}
|
||||
#[doc = "Clock Monitor generates reset when error detected"]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(SOSCCMREW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 17;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `LK`"]
|
||||
pub enum LKW {
|
||||
#[doc = "This Control Status Register can be written."]
|
||||
_0,
|
||||
#[doc = "This Control Status Register cannot be written."]
|
||||
_1,
|
||||
}
|
||||
impl LKW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
LKW::_0 => false,
|
||||
LKW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _LKW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _LKW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: LKW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "This Control Status Register can be written."]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(LKW::_0)
|
||||
}
|
||||
#[doc = "This Control Status Register cannot be written."]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(LKW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 23;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SOSCERR`"]
|
||||
pub enum SOSCERRW {
|
||||
#[doc = "System OSC Clock Monitor is disabled or has not detected an error"]
|
||||
_0,
|
||||
#[doc = "System OSC Clock Monitor is enabled and detected an error"]
|
||||
_1,
|
||||
}
|
||||
impl SOSCERRW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
SOSCERRW::_0 => false,
|
||||
SOSCERRW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _SOSCERRW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _SOSCERRW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: SOSCERRW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "System OSC Clock Monitor is disabled or has not detected an error"]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(SOSCERRW::_0)
|
||||
}
|
||||
#[doc = "System OSC Clock Monitor is enabled and detected an error"]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(SOSCERRW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 26;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bit 0 - System OSC Enable"]
|
||||
#[inline]
|
||||
pub fn soscen(&self) -> SOSCENR {
|
||||
SOSCENR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 16 - System OSC Clock Monitor"]
|
||||
#[inline]
|
||||
pub fn sosccm(&self) -> SOSCCMR {
|
||||
SOSCCMR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 16;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 17 - System OSC Clock Monitor Reset Enable"]
|
||||
#[inline]
|
||||
pub fn sosccmre(&self) -> SOSCCMRER {
|
||||
SOSCCMRER::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 17;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 23 - Lock Register"]
|
||||
#[inline]
|
||||
pub fn lk(&self) -> LKR {
|
||||
LKR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 23;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 24 - System OSC Valid"]
|
||||
#[inline]
|
||||
pub fn soscvld(&self) -> SOSCVLDR {
|
||||
SOSCVLDR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 24;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 25 - System OSC Selected"]
|
||||
#[inline]
|
||||
pub fn soscsel(&self) -> SOSCSELR {
|
||||
SOSCSELR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 25;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 26 - System OSC Clock Error"]
|
||||
#[inline]
|
||||
pub fn soscerr(&self) -> SOSCERRR {
|
||||
SOSCERRR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 26;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 0 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bit 0 - System OSC Enable"]
|
||||
#[inline]
|
||||
pub fn soscen(&mut self) -> _SOSCENW {
|
||||
_SOSCENW { w: self }
|
||||
}
|
||||
#[doc = "Bit 16 - System OSC Clock Monitor"]
|
||||
#[inline]
|
||||
pub fn sosccm(&mut self) -> _SOSCCMW {
|
||||
_SOSCCMW { w: self }
|
||||
}
|
||||
#[doc = "Bit 17 - System OSC Clock Monitor Reset Enable"]
|
||||
#[inline]
|
||||
pub fn sosccmre(&mut self) -> _SOSCCMREW {
|
||||
_SOSCCMREW { w: self }
|
||||
}
|
||||
#[doc = "Bit 23 - Lock Register"]
|
||||
#[inline]
|
||||
pub fn lk(&mut self) -> _LKW {
|
||||
_LKW { w: self }
|
||||
}
|
||||
#[doc = "Bit 26 - System OSC Clock Error"]
|
||||
#[inline]
|
||||
pub fn soscerr(&mut self) -> _SOSCERRW {
|
||||
_SOSCERRW { w: self }
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user