Same as last commit just run through the form tool (splits up large lib.rs files)
This commit is contained in:
Kjetil Kjeka
650
src/scg/sirccsr/mod.rs
Normal file
650
src/scg/sirccsr/mod.rs
Normal file
@ -0,0 +1,650 @@
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#[doc = r" Value read from the register"]
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pub struct R {
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bits: u32,
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}
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#[doc = r" Value to write to the register"]
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pub struct W {
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bits: u32,
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}
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impl super::SIRCCSR {
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#[doc = r" Modifies the contents of the register"]
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#[inline]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
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{
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let bits = self.register.get();
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let r = R { bits: bits };
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let mut w = W { bits: bits };
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f(&r, &mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Reads the contents of the register"]
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#[inline]
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pub fn read(&self) -> R {
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R { bits: self.register.get() }
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}
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#[doc = r" Writes to the register"]
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#[inline]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut W) -> &mut W,
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{
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let mut w = W::reset_value();
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f(&mut w);
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self.register.set(w.bits);
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}
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#[doc = r" Writes the reset value to the register"]
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#[inline]
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pub fn reset(&self) {
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self.write(|w| w)
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}
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}
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#[doc = "Possible values of the field `SIRCEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SIRCENR {
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#[doc = "Slow IRC is disabled"]
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_0,
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#[doc = "Slow IRC is enabled"]
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_1,
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}
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impl SIRCENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SIRCENR::_0 => false,
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SIRCENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SIRCENR {
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match value {
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false => SIRCENR::_0,
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true => SIRCENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SIRCENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SIRCENR::_1
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}
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}
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#[doc = "Possible values of the field `SIRCSTEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SIRCSTENR {
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#[doc = "Slow IRC is disabled in supported Stop modes"]
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_0,
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#[doc = "Slow IRC is enabled in supported Stop modes"]
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_1,
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}
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impl SIRCSTENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SIRCSTENR::_0 => false,
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SIRCSTENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SIRCSTENR {
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match value {
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false => SIRCSTENR::_0,
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true => SIRCSTENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SIRCSTENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SIRCSTENR::_1
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}
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}
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#[doc = "Possible values of the field `SIRCLPEN`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SIRCLPENR {
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#[doc = "Slow IRC is disabled in VLP modes"]
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_0,
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#[doc = "Slow IRC is enabled in VLP modes"]
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_1,
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}
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impl SIRCLPENR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SIRCLPENR::_0 => false,
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SIRCLPENR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SIRCLPENR {
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match value {
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false => SIRCLPENR::_0,
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true => SIRCLPENR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SIRCLPENR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SIRCLPENR::_1
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}
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}
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#[doc = "Possible values of the field `LK`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum LKR {
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#[doc = "Control Status Register can be written."]
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_0,
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#[doc = "Control Status Register cannot be written."]
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_1,
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}
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impl LKR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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LKR::_0 => false,
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LKR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> LKR {
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match value {
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false => LKR::_0,
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true => LKR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == LKR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == LKR::_1
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}
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}
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#[doc = "Possible values of the field `SIRCVLD`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SIRCVLDR {
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#[doc = "Slow IRC is not enabled or clock is not valid"]
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_0,
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#[doc = "Slow IRC is enabled and output clock is valid"]
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_1,
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}
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impl SIRCVLDR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SIRCVLDR::_0 => false,
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SIRCVLDR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SIRCVLDR {
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match value {
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false => SIRCVLDR::_0,
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true => SIRCVLDR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SIRCVLDR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SIRCVLDR::_1
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}
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}
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#[doc = "Possible values of the field `SIRCSEL`"]
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub enum SIRCSELR {
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#[doc = "Slow IRC is not the system clock source"]
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_0,
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#[doc = "Slow IRC is the system clock source"]
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_1,
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}
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impl SIRCSELR {
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#[doc = r" Returns `true` if the bit is clear (0)"]
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#[inline]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = r" Returns `true` if the bit is set (1)"]
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#[inline]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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#[doc = r" Value of the field as raw bits"]
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#[inline]
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pub fn bit(&self) -> bool {
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match *self {
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SIRCSELR::_0 => false,
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SIRCSELR::_1 => true,
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}
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}
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _from(value: bool) -> SIRCSELR {
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match value {
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false => SIRCSELR::_0,
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true => SIRCSELR::_1,
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}
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}
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#[doc = "Checks if the value of the field is `_0`"]
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#[inline]
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pub fn is_0(&self) -> bool {
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*self == SIRCSELR::_0
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}
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#[doc = "Checks if the value of the field is `_1`"]
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#[inline]
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pub fn is_1(&self) -> bool {
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*self == SIRCSELR::_1
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}
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}
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#[doc = "Values that can be written to the field `SIRCEN`"]
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pub enum SIRCENW {
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#[doc = "Slow IRC is disabled"]
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_0,
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#[doc = "Slow IRC is enabled"]
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_1,
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}
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impl SIRCENW {
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#[allow(missing_docs)]
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#[doc(hidden)]
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#[inline]
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pub fn _bits(&self) -> bool {
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match *self {
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SIRCENW::_0 => false,
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SIRCENW::_1 => true,
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}
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}
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}
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#[doc = r" Proxy"]
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pub struct _SIRCENW<'a> {
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w: &'a mut W,
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}
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impl<'a> _SIRCENW<'a> {
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#[doc = r" Writes `variant` to the field"]
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#[inline]
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pub fn variant(self, variant: SIRCENW) -> &'a mut W {
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{
|
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self.bit(variant._bits())
|
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}
|
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}
|
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#[doc = "Slow IRC is disabled"]
|
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#[inline]
|
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pub fn _0(self) -> &'a mut W {
|
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self.variant(SIRCENW::_0)
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}
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#[doc = "Slow IRC is enabled"]
|
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#[inline]
|
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pub fn _1(self) -> &'a mut W {
|
||||
self.variant(SIRCENW::_1)
|
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}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
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self.bit(true)
|
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}
|
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#[doc = r" Clears the field bit"]
|
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pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 0;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
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self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SIRCSTEN`"]
|
||||
pub enum SIRCSTENW {
|
||||
#[doc = "Slow IRC is disabled in supported Stop modes"]
|
||||
_0,
|
||||
#[doc = "Slow IRC is enabled in supported Stop modes"]
|
||||
_1,
|
||||
}
|
||||
impl SIRCSTENW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
SIRCSTENW::_0 => false,
|
||||
SIRCSTENW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _SIRCSTENW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _SIRCSTENW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: SIRCSTENW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Slow IRC is disabled in supported Stop modes"]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(SIRCSTENW::_0)
|
||||
}
|
||||
#[doc = "Slow IRC is enabled in supported Stop modes"]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(SIRCSTENW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 1;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `SIRCLPEN`"]
|
||||
pub enum SIRCLPENW {
|
||||
#[doc = "Slow IRC is disabled in VLP modes"]
|
||||
_0,
|
||||
#[doc = "Slow IRC is enabled in VLP modes"]
|
||||
_1,
|
||||
}
|
||||
impl SIRCLPENW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
SIRCLPENW::_0 => false,
|
||||
SIRCLPENW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _SIRCLPENW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _SIRCLPENW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: SIRCLPENW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Slow IRC is disabled in VLP modes"]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(SIRCLPENW::_0)
|
||||
}
|
||||
#[doc = "Slow IRC is enabled in VLP modes"]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(SIRCLPENW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 2;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Values that can be written to the field `LK`"]
|
||||
pub enum LKW {
|
||||
#[doc = "Control Status Register can be written."]
|
||||
_0,
|
||||
#[doc = "Control Status Register cannot be written."]
|
||||
_1,
|
||||
}
|
||||
impl LKW {
|
||||
#[allow(missing_docs)]
|
||||
#[doc(hidden)]
|
||||
#[inline]
|
||||
pub fn _bits(&self) -> bool {
|
||||
match *self {
|
||||
LKW::_0 => false,
|
||||
LKW::_1 => true,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[doc = r" Proxy"]
|
||||
pub struct _LKW<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> _LKW<'a> {
|
||||
#[doc = r" Writes `variant` to the field"]
|
||||
#[inline]
|
||||
pub fn variant(self, variant: LKW) -> &'a mut W {
|
||||
{
|
||||
self.bit(variant._bits())
|
||||
}
|
||||
}
|
||||
#[doc = "Control Status Register can be written."]
|
||||
#[inline]
|
||||
pub fn _0(self) -> &'a mut W {
|
||||
self.variant(LKW::_0)
|
||||
}
|
||||
#[doc = "Control Status Register cannot be written."]
|
||||
#[inline]
|
||||
pub fn _1(self) -> &'a mut W {
|
||||
self.variant(LKW::_1)
|
||||
}
|
||||
#[doc = r" Sets the field bit"]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r" Clears the field bit"]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r" Writes raw bits to the field"]
|
||||
#[inline]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 23;
|
||||
self.w.bits &= !((MASK as u32) << OFFSET);
|
||||
self.w.bits |= ((value & MASK) as u32) << OFFSET;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = r" Value of the register as raw bits"]
|
||||
#[inline]
|
||||
pub fn bits(&self) -> u32 {
|
||||
self.bits
|
||||
}
|
||||
#[doc = "Bit 0 - Slow IRC Enable"]
|
||||
#[inline]
|
||||
pub fn sircen(&self) -> SIRCENR {
|
||||
SIRCENR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 0;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 1 - Slow IRC Stop Enable"]
|
||||
#[inline]
|
||||
pub fn sircsten(&self) -> SIRCSTENR {
|
||||
SIRCSTENR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 1;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 2 - Slow IRC Low Power Enable"]
|
||||
#[inline]
|
||||
pub fn sirclpen(&self) -> SIRCLPENR {
|
||||
SIRCLPENR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 2;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 23 - Lock Register"]
|
||||
#[inline]
|
||||
pub fn lk(&self) -> LKR {
|
||||
LKR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 23;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 24 - Slow IRC Valid"]
|
||||
#[inline]
|
||||
pub fn sircvld(&self) -> SIRCVLDR {
|
||||
SIRCVLDR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 24;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
#[doc = "Bit 25 - Slow IRC Selected"]
|
||||
#[inline]
|
||||
pub fn sircsel(&self) -> SIRCSELR {
|
||||
SIRCSELR::_from({
|
||||
const MASK: bool = true;
|
||||
const OFFSET: u8 = 25;
|
||||
((self.bits >> OFFSET) & MASK as u32) != 0
|
||||
})
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = r" Reset value of the register"]
|
||||
#[inline]
|
||||
pub fn reset_value() -> W {
|
||||
W { bits: 16777221 }
|
||||
}
|
||||
#[doc = r" Writes raw bits to the register"]
|
||||
#[inline]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
#[doc = "Bit 0 - Slow IRC Enable"]
|
||||
#[inline]
|
||||
pub fn sircen(&mut self) -> _SIRCENW {
|
||||
_SIRCENW { w: self }
|
||||
}
|
||||
#[doc = "Bit 1 - Slow IRC Stop Enable"]
|
||||
#[inline]
|
||||
pub fn sircsten(&mut self) -> _SIRCSTENW {
|
||||
_SIRCSTENW { w: self }
|
||||
}
|
||||
#[doc = "Bit 2 - Slow IRC Low Power Enable"]
|
||||
#[inline]
|
||||
pub fn sirclpen(&mut self) -> _SIRCLPENW {
|
||||
_SIRCLPENW { w: self }
|
||||
}
|
||||
#[doc = "Bit 23 - Lock Register"]
|
||||
#[inline]
|
||||
pub fn lk(&mut self) -> _LKW {
|
||||
_LKW { w: self }
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user