xobs/s32k118.rs
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Same as last commit just run through the form tool (splits up large lib.rs files)

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This commit is contained in:
Kjetil Kjeka
2017-09-23 20:09:53 +02:00
parent 63efe927e5
commit 7facea48b2
1680 changed files with 666069 additions and 667757 deletions
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216
src/scg/clkoutcnfg/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::CLKOUTCNFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `CLKOUTSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum CLKOUTSELR {
#[doc = "SCG SLOW Clock"]
_0000,
#[doc = "System OSC (SOSC_CLK)"]
_0001,
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Fast IRC (FIRC_CLK)"]
_0011,
#[doc = "System PLL (SPLL_CLK)"]
_0110,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl CLKOUTSELR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
CLKOUTSELR::_0000 => 0,
CLKOUTSELR::_0001 => 1,
CLKOUTSELR::_0010 => 2,
CLKOUTSELR::_0011 => 3,
CLKOUTSELR::_0110 => 6,
CLKOUTSELR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> CLKOUTSELR {
match value {
0 => CLKOUTSELR::_0000,
1 => CLKOUTSELR::_0001,
2 => CLKOUTSELR::_0010,
3 => CLKOUTSELR::_0011,
6 => CLKOUTSELR::_0110,
i => CLKOUTSELR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_0000`"]
#[inline]
pub fn is_0000(&self) -> bool {
*self == CLKOUTSELR::_0000
}
#[doc = "Checks if the value of the field is `_0001`"]
#[inline]
pub fn is_0001(&self) -> bool {
*self == CLKOUTSELR::_0001
}
#[doc = "Checks if the value of the field is `_0010`"]
#[inline]
pub fn is_0010(&self) -> bool {
*self == CLKOUTSELR::_0010
}
#[doc = "Checks if the value of the field is `_0011`"]
#[inline]
pub fn is_0011(&self) -> bool {
*self == CLKOUTSELR::_0011
}
#[doc = "Checks if the value of the field is `_0110`"]
#[inline]
pub fn is_0110(&self) -> bool {
*self == CLKOUTSELR::_0110
}
}
#[doc = "Values that can be written to the field `CLKOUTSEL`"]
pub enum CLKOUTSELW {
#[doc = "SCG SLOW Clock"]
_0000,
#[doc = "System OSC (SOSC_CLK)"]
_0001,
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Fast IRC (FIRC_CLK)"]
_0011,
#[doc = "System PLL (SPLL_CLK)"]
_0110,
}
impl CLKOUTSELW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
CLKOUTSELW::_0000 => 0,
CLKOUTSELW::_0001 => 1,
CLKOUTSELW::_0010 => 2,
CLKOUTSELW::_0011 => 3,
CLKOUTSELW::_0110 => 6,
}
}
}
#[doc = r" Proxy"]
pub struct _CLKOUTSELW<'a> {
w: &'a mut W,
}
impl<'a> _CLKOUTSELW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: CLKOUTSELW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "SCG SLOW Clock"]
#[inline]
pub fn _0000(self) -> &'a mut W {
self.variant(CLKOUTSELW::_0000)
}
#[doc = "System OSC (SOSC_CLK)"]
#[inline]
pub fn _0001(self) -> &'a mut W {
self.variant(CLKOUTSELW::_0001)
}
#[doc = "Slow IRC (SIRC_CLK)"]
#[inline]
pub fn _0010(self) -> &'a mut W {
self.variant(CLKOUTSELW::_0010)
}
#[doc = "Fast IRC (FIRC_CLK)"]
#[inline]
pub fn _0011(self) -> &'a mut W {
self.variant(CLKOUTSELW::_0011)
}
#[doc = "System PLL (SPLL_CLK)"]
#[inline]
pub fn _0110(self) -> &'a mut W {
self.variant(CLKOUTSELW::_0110)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 15;
const OFFSET: u8 = 24;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 24:27 - SCG Clkout Select"]
#[inline]
pub fn clkoutsel(&self) -> CLKOUTSELR {
CLKOUTSELR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 50331648 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 24:27 - SCG Clkout Select"]
#[inline]
pub fn clkoutsel(&mut self) -> _CLKOUTSELW {
_CLKOUTSELW { w: self }
}
}

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src/scg/csr/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::CSR {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
#[doc = "Possible values of the field `DIVSLOW`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVSLOWR {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl DIVSLOWR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
DIVSLOWR::_0000 => 0,
DIVSLOWR::_0001 => 1,
DIVSLOWR::_0010 => 2,
DIVSLOWR::_0011 => 3,
DIVSLOWR::_0100 => 4,
DIVSLOWR::_0101 => 5,
DIVSLOWR::_0110 => 6,
DIVSLOWR::_0111 => 7,
DIVSLOWR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> DIVSLOWR {
match value {
0 => DIVSLOWR::_0000,
1 => DIVSLOWR::_0001,
2 => DIVSLOWR::_0010,
3 => DIVSLOWR::_0011,
4 => DIVSLOWR::_0100,
5 => DIVSLOWR::_0101,
6 => DIVSLOWR::_0110,
7 => DIVSLOWR::_0111,
i => DIVSLOWR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_0000`"]
#[inline]
pub fn is_0000(&self) -> bool {
*self == DIVSLOWR::_0000
}
#[doc = "Checks if the value of the field is `_0001`"]
#[inline]
pub fn is_0001(&self) -> bool {
*self == DIVSLOWR::_0001
}
#[doc = "Checks if the value of the field is `_0010`"]
#[inline]
pub fn is_0010(&self) -> bool {
*self == DIVSLOWR::_0010
}
#[doc = "Checks if the value of the field is `_0011`"]
#[inline]
pub fn is_0011(&self) -> bool {
*self == DIVSLOWR::_0011
}
#[doc = "Checks if the value of the field is `_0100`"]
#[inline]
pub fn is_0100(&self) -> bool {
*self == DIVSLOWR::_0100
}
#[doc = "Checks if the value of the field is `_0101`"]
#[inline]
pub fn is_0101(&self) -> bool {
*self == DIVSLOWR::_0101
}
#[doc = "Checks if the value of the field is `_0110`"]
#[inline]
pub fn is_0110(&self) -> bool {
*self == DIVSLOWR::_0110
}
#[doc = "Checks if the value of the field is `_0111`"]
#[inline]
pub fn is_0111(&self) -> bool {
*self == DIVSLOWR::_0111
}
}
#[doc = "Possible values of the field `DIVBUS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVBUSR {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
}
impl DIVBUSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
DIVBUSR::_0000 => 0,
DIVBUSR::_0001 => 1,
DIVBUSR::_0010 => 2,
DIVBUSR::_0011 => 3,
DIVBUSR::_0100 => 4,
DIVBUSR::_0101 => 5,
DIVBUSR::_0110 => 6,
DIVBUSR::_0111 => 7,
DIVBUSR::_1000 => 8,
DIVBUSR::_1001 => 9,
DIVBUSR::_1010 => 10,
DIVBUSR::_1011 => 11,
DIVBUSR::_1100 => 12,
DIVBUSR::_1101 => 13,
DIVBUSR::_1110 => 14,
DIVBUSR::_1111 => 15,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> DIVBUSR {
match value {
0 => DIVBUSR::_0000,
1 => DIVBUSR::_0001,
2 => DIVBUSR::_0010,
3 => DIVBUSR::_0011,
4 => DIVBUSR::_0100,
5 => DIVBUSR::_0101,
6 => DIVBUSR::_0110,
7 => DIVBUSR::_0111,
8 => DIVBUSR::_1000,
9 => DIVBUSR::_1001,
10 => DIVBUSR::_1010,
11 => DIVBUSR::_1011,
12 => DIVBUSR::_1100,
13 => DIVBUSR::_1101,
14 => DIVBUSR::_1110,
15 => DIVBUSR::_1111,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_0000`"]
#[inline]
pub fn is_0000(&self) -> bool {
*self == DIVBUSR::_0000
}
#[doc = "Checks if the value of the field is `_0001`"]
#[inline]
pub fn is_0001(&self) -> bool {
*self == DIVBUSR::_0001
}
#[doc = "Checks if the value of the field is `_0010`"]
#[inline]
pub fn is_0010(&self) -> bool {
*self == DIVBUSR::_0010
}
#[doc = "Checks if the value of the field is `_0011`"]
#[inline]
pub fn is_0011(&self) -> bool {
*self == DIVBUSR::_0011
}
#[doc = "Checks if the value of the field is `_0100`"]
#[inline]
pub fn is_0100(&self) -> bool {
*self == DIVBUSR::_0100
}
#[doc = "Checks if the value of the field is `_0101`"]
#[inline]
pub fn is_0101(&self) -> bool {
*self == DIVBUSR::_0101
}
#[doc = "Checks if the value of the field is `_0110`"]
#[inline]
pub fn is_0110(&self) -> bool {
*self == DIVBUSR::_0110
}
#[doc = "Checks if the value of the field is `_0111`"]
#[inline]
pub fn is_0111(&self) -> bool {
*self == DIVBUSR::_0111
}
#[doc = "Checks if the value of the field is `_1000`"]
#[inline]
pub fn is_1000(&self) -> bool {
*self == DIVBUSR::_1000
}
#[doc = "Checks if the value of the field is `_1001`"]
#[inline]
pub fn is_1001(&self) -> bool {
*self == DIVBUSR::_1001
}
#[doc = "Checks if the value of the field is `_1010`"]
#[inline]
pub fn is_1010(&self) -> bool {
*self == DIVBUSR::_1010
}
#[doc = "Checks if the value of the field is `_1011`"]
#[inline]
pub fn is_1011(&self) -> bool {
*self == DIVBUSR::_1011
}
#[doc = "Checks if the value of the field is `_1100`"]
#[inline]
pub fn is_1100(&self) -> bool {
*self == DIVBUSR::_1100
}
#[doc = "Checks if the value of the field is `_1101`"]
#[inline]
pub fn is_1101(&self) -> bool {
*self == DIVBUSR::_1101
}
#[doc = "Checks if the value of the field is `_1110`"]
#[inline]
pub fn is_1110(&self) -> bool {
*self == DIVBUSR::_1110
}
#[doc = "Checks if the value of the field is `_1111`"]
#[inline]
pub fn is_1111(&self) -> bool {
*self == DIVBUSR::_1111
}
}
#[doc = "Possible values of the field `DIVCORE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum DIVCORER {
#[doc = "Divide-by-1"]
_0000,
#[doc = "Divide-by-2"]
_0001,
#[doc = "Divide-by-3"]
_0010,
#[doc = "Divide-by-4"]
_0011,
#[doc = "Divide-by-5"]
_0100,
#[doc = "Divide-by-6"]
_0101,
#[doc = "Divide-by-7"]
_0110,
#[doc = "Divide-by-8"]
_0111,
#[doc = "Divide-by-9"]
_1000,
#[doc = "Divide-by-10"]
_1001,
#[doc = "Divide-by-11"]
_1010,
#[doc = "Divide-by-12"]
_1011,
#[doc = "Divide-by-13"]
_1100,
#[doc = "Divide-by-14"]
_1101,
#[doc = "Divide-by-15"]
_1110,
#[doc = "Divide-by-16"]
_1111,
}
impl DIVCORER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
DIVCORER::_0000 => 0,
DIVCORER::_0001 => 1,
DIVCORER::_0010 => 2,
DIVCORER::_0011 => 3,
DIVCORER::_0100 => 4,
DIVCORER::_0101 => 5,
DIVCORER::_0110 => 6,
DIVCORER::_0111 => 7,
DIVCORER::_1000 => 8,
DIVCORER::_1001 => 9,
DIVCORER::_1010 => 10,
DIVCORER::_1011 => 11,
DIVCORER::_1100 => 12,
DIVCORER::_1101 => 13,
DIVCORER::_1110 => 14,
DIVCORER::_1111 => 15,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> DIVCORER {
match value {
0 => DIVCORER::_0000,
1 => DIVCORER::_0001,
2 => DIVCORER::_0010,
3 => DIVCORER::_0011,
4 => DIVCORER::_0100,
5 => DIVCORER::_0101,
6 => DIVCORER::_0110,
7 => DIVCORER::_0111,
8 => DIVCORER::_1000,
9 => DIVCORER::_1001,
10 => DIVCORER::_1010,
11 => DIVCORER::_1011,
12 => DIVCORER::_1100,
13 => DIVCORER::_1101,
14 => DIVCORER::_1110,
15 => DIVCORER::_1111,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_0000`"]
#[inline]
pub fn is_0000(&self) -> bool {
*self == DIVCORER::_0000
}
#[doc = "Checks if the value of the field is `_0001`"]
#[inline]
pub fn is_0001(&self) -> bool {
*self == DIVCORER::_0001
}
#[doc = "Checks if the value of the field is `_0010`"]
#[inline]
pub fn is_0010(&self) -> bool {
*self == DIVCORER::_0010
}
#[doc = "Checks if the value of the field is `_0011`"]
#[inline]
pub fn is_0011(&self) -> bool {
*self == DIVCORER::_0011
}
#[doc = "Checks if the value of the field is `_0100`"]
#[inline]
pub fn is_0100(&self) -> bool {
*self == DIVCORER::_0100
}
#[doc = "Checks if the value of the field is `_0101`"]
#[inline]
pub fn is_0101(&self) -> bool {
*self == DIVCORER::_0101
}
#[doc = "Checks if the value of the field is `_0110`"]
#[inline]
pub fn is_0110(&self) -> bool {
*self == DIVCORER::_0110
}
#[doc = "Checks if the value of the field is `_0111`"]
#[inline]
pub fn is_0111(&self) -> bool {
*self == DIVCORER::_0111
}
#[doc = "Checks if the value of the field is `_1000`"]
#[inline]
pub fn is_1000(&self) -> bool {
*self == DIVCORER::_1000
}
#[doc = "Checks if the value of the field is `_1001`"]
#[inline]
pub fn is_1001(&self) -> bool {
*self == DIVCORER::_1001
}
#[doc = "Checks if the value of the field is `_1010`"]
#[inline]
pub fn is_1010(&self) -> bool {
*self == DIVCORER::_1010
}
#[doc = "Checks if the value of the field is `_1011`"]
#[inline]
pub fn is_1011(&self) -> bool {
*self == DIVCORER::_1011
}
#[doc = "Checks if the value of the field is `_1100`"]
#[inline]
pub fn is_1100(&self) -> bool {
*self == DIVCORER::_1100
}
#[doc = "Checks if the value of the field is `_1101`"]
#[inline]
pub fn is_1101(&self) -> bool {
*self == DIVCORER::_1101
}
#[doc = "Checks if the value of the field is `_1110`"]
#[inline]
pub fn is_1110(&self) -> bool {
*self == DIVCORER::_1110
}
#[doc = "Checks if the value of the field is `_1111`"]
#[inline]
pub fn is_1111(&self) -> bool {
*self == DIVCORER::_1111
}
}
#[doc = "Possible values of the field `SCS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SCSR {
#[doc = "System OSC (SOSC_CLK)"]
_0001,
#[doc = "Slow IRC (SIRC_CLK)"]
_0010,
#[doc = "Fast IRC (FIRC_CLK)"]
_0011,
#[doc = "System PLL (SPLL_CLK)"]
_0110,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl SCSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
SCSR::_0001 => 1,
SCSR::_0010 => 2,
SCSR::_0011 => 3,
SCSR::_0110 => 6,
SCSR::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> SCSR {
match value {
1 => SCSR::_0001,
2 => SCSR::_0010,
3 => SCSR::_0011,
6 => SCSR::_0110,
i => SCSR::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_0001`"]
#[inline]
pub fn is_0001(&self) -> bool {
*self == SCSR::_0001
}
#[doc = "Checks if the value of the field is `_0010`"]
#[inline]
pub fn is_0010(&self) -> bool {
*self == SCSR::_0010
}
#[doc = "Checks if the value of the field is `_0011`"]
#[inline]
pub fn is_0011(&self) -> bool {
*self == SCSR::_0011
}
#[doc = "Checks if the value of the field is `_0110`"]
#[inline]
pub fn is_0110(&self) -> bool {
*self == SCSR::_0110
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:3 - Slow Clock Divide Ratio"]
#[inline]
pub fn divslow(&self) -> DIVSLOWR {
DIVSLOWR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 4:7 - Bus Clock Divide Ratio"]
#[inline]
pub fn divbus(&self) -> DIVBUSR {
DIVBUSR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 16:19 - Core Clock Divide Ratio"]
#[inline]
pub fn divcore(&self) -> DIVCORER {
DIVCORER::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 24:27 - System Clock Source"]
#[inline]
pub fn scs(&self) -> SCSR {
SCSR::_from({
const MASK: u8 = 15;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}

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src/scg/firccfg/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FIRCCFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `RANGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RANGER {
#[doc = "Fast IRC is trimmed to 48 MHz"]
_00,
#[doc = "Fast IRC is trimmed to 52 MHz"]
_01,
#[doc = "Fast IRC is trimmed to 56 MHz"]
_10,
#[doc = "Fast IRC is trimmed to 60 MHz"]
_11,
}
impl RANGER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
RANGER::_00 => 0,
RANGER::_01 => 1,
RANGER::_10 => 2,
RANGER::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> RANGER {
match value {
0 => RANGER::_00,
1 => RANGER::_01,
2 => RANGER::_10,
3 => RANGER::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == RANGER::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == RANGER::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == RANGER::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == RANGER::_11
}
}
#[doc = "Values that can be written to the field `RANGE`"]
pub enum RANGEW {
#[doc = "Fast IRC is trimmed to 48 MHz"]
_00,
#[doc = "Fast IRC is trimmed to 52 MHz"]
_01,
#[doc = "Fast IRC is trimmed to 56 MHz"]
_10,
#[doc = "Fast IRC is trimmed to 60 MHz"]
_11,
}
impl RANGEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
RANGEW::_00 => 0,
RANGEW::_01 => 1,
RANGEW::_10 => 2,
RANGEW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _RANGEW<'a> {
w: &'a mut W,
}
impl<'a> _RANGEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RANGEW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Fast IRC is trimmed to 48 MHz"]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(RANGEW::_00)
}
#[doc = "Fast IRC is trimmed to 52 MHz"]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(RANGEW::_01)
}
#[doc = "Fast IRC is trimmed to 56 MHz"]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(RANGEW::_10)
}
#[doc = "Fast IRC is trimmed to 60 MHz"]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(RANGEW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:1 - Frequency Range"]
#[inline]
pub fn range(&self) -> RANGER {
RANGER::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:1 - Frequency Range"]
#[inline]
pub fn range(&mut self) -> _RANGEW {
_RANGEW { w: self }
}
}

650
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@ -0,0 +1,650 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FIRCCSR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `FIRCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCENR {
#[doc = "Fast IRC is disabled"]
_0,
#[doc = "Fast IRC is enabled"]
_1,
}
impl FIRCENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FIRCENR::_0 => false,
FIRCENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FIRCENR {
match value {
false => FIRCENR::_0,
true => FIRCENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == FIRCENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == FIRCENR::_1
}
}
#[doc = "Possible values of the field `FIRCREGOFF`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCREGOFFR {
#[doc = "Fast IRC Regulator is enabled."]
_0,
#[doc = "Fast IRC Regulator is disabled."]
_1,
}
impl FIRCREGOFFR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FIRCREGOFFR::_0 => false,
FIRCREGOFFR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FIRCREGOFFR {
match value {
false => FIRCREGOFFR::_0,
true => FIRCREGOFFR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == FIRCREGOFFR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == FIRCREGOFFR::_1
}
}
#[doc = "Possible values of the field `LK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LKR {
#[doc = "Control Status Register can be written."]
_0,
#[doc = "Control Status Register cannot be written."]
_1,
}
impl LKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
LKR::_0 => false,
LKR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> LKR {
match value {
false => LKR::_0,
true => LKR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == LKR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == LKR::_1
}
}
#[doc = "Possible values of the field `FIRCVLD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCVLDR {
#[doc = "Fast IRC is not enabled or clock is not valid."]
_0,
#[doc = "Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog."]
_1,
}
impl FIRCVLDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FIRCVLDR::_0 => false,
FIRCVLDR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FIRCVLDR {
match value {
false => FIRCVLDR::_0,
true => FIRCVLDR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == FIRCVLDR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == FIRCVLDR::_1
}
}
#[doc = "Possible values of the field `FIRCSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCSELR {
#[doc = "Fast IRC is not the system clock source"]
_0,
#[doc = "Fast IRC is the system clock source"]
_1,
}
impl FIRCSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FIRCSELR::_0 => false,
FIRCSELR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FIRCSELR {
match value {
false => FIRCSELR::_0,
true => FIRCSELR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == FIRCSELR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == FIRCSELR::_1
}
}
#[doc = "Possible values of the field `FIRCERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCERRR {
#[doc = "Error not detected with the Fast IRC trimming."]
_0,
#[doc = "Error detected with the Fast IRC trimming."]
_1,
}
impl FIRCERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FIRCERRR::_0 => false,
FIRCERRR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FIRCERRR {
match value {
false => FIRCERRR::_0,
true => FIRCERRR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == FIRCERRR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == FIRCERRR::_1
}
}
#[doc = "Values that can be written to the field `FIRCEN`"]
pub enum FIRCENW {
#[doc = "Fast IRC is disabled"]
_0,
#[doc = "Fast IRC is enabled"]
_1,
}
impl FIRCENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
FIRCENW::_0 => false,
FIRCENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _FIRCENW<'a> {
w: &'a mut W,
}
impl<'a> _FIRCENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FIRCENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Fast IRC is disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FIRCENW::_0)
}
#[doc = "Fast IRC is enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FIRCENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `FIRCREGOFF`"]
pub enum FIRCREGOFFW {
#[doc = "Fast IRC Regulator is enabled."]
_0,
#[doc = "Fast IRC Regulator is disabled."]
_1,
}
impl FIRCREGOFFW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
FIRCREGOFFW::_0 => false,
FIRCREGOFFW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _FIRCREGOFFW<'a> {
w: &'a mut W,
}
impl<'a> _FIRCREGOFFW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FIRCREGOFFW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Fast IRC Regulator is enabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FIRCREGOFFW::_0)
}
#[doc = "Fast IRC Regulator is disabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FIRCREGOFFW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `LK`"]
pub enum LKW {
#[doc = "Control Status Register can be written."]
_0,
#[doc = "Control Status Register cannot be written."]
_1,
}
impl LKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
LKW::_0 => false,
LKW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _LKW<'a> {
w: &'a mut W,
}
impl<'a> _LKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: LKW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Control Status Register can be written."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(LKW::_0)
}
#[doc = "Control Status Register cannot be written."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(LKW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `FIRCERR`"]
pub enum FIRCERRW {
#[doc = "Error not detected with the Fast IRC trimming."]
_0,
#[doc = "Error detected with the Fast IRC trimming."]
_1,
}
impl FIRCERRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
FIRCERRW::_0 => false,
FIRCERRW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _FIRCERRW<'a> {
w: &'a mut W,
}
impl<'a> _FIRCERRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FIRCERRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Error not detected with the Fast IRC trimming."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FIRCERRW::_0)
}
#[doc = "Error detected with the Fast IRC trimming."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FIRCERRW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Fast IRC Enable"]
#[inline]
pub fn fircen(&self) -> FIRCENR {
FIRCENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - Fast IRC Regulator Enable"]
#[inline]
pub fn fircregoff(&self) -> FIRCREGOFFR {
FIRCREGOFFR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 23 - Lock Register"]
#[inline]
pub fn lk(&self) -> LKR {
LKR::_from({
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 24 - Fast IRC Valid status"]
#[inline]
pub fn fircvld(&self) -> FIRCVLDR {
FIRCVLDR::_from({
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 25 - Fast IRC Selected status"]
#[inline]
pub fn fircsel(&self) -> FIRCSELR {
FIRCSELR::_from({
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 26 - Fast IRC Clock Error"]
#[inline]
pub fn fircerr(&self) -> FIRCERRR {
FIRCERRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 50331649 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Fast IRC Enable"]
#[inline]
pub fn fircen(&mut self) -> _FIRCENW {
_FIRCENW { w: self }
}
#[doc = "Bit 3 - Fast IRC Regulator Enable"]
#[inline]
pub fn fircregoff(&mut self) -> _FIRCREGOFFW {
_FIRCREGOFFW { w: self }
}
#[doc = "Bit 23 - Lock Register"]
#[inline]
pub fn lk(&mut self) -> _LKW {
_LKW { w: self }
}
#[doc = "Bit 26 - Fast IRC Clock Error"]
#[inline]
pub fn fircerr(&mut self) -> _FIRCERRW {
_FIRCERRW { w: self }
}
}

470
src/scg/fircdiv/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::FIRCDIV {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `FIRCDIV1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCDIV1R {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl FIRCDIV1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
FIRCDIV1R::_000 => 0,
FIRCDIV1R::_001 => 1,
FIRCDIV1R::_010 => 2,
FIRCDIV1R::_011 => 3,
FIRCDIV1R::_100 => 4,
FIRCDIV1R::_101 => 5,
FIRCDIV1R::_110 => 6,
FIRCDIV1R::_111 => 7,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> FIRCDIV1R {
match value {
0 => FIRCDIV1R::_000,
1 => FIRCDIV1R::_001,
2 => FIRCDIV1R::_010,
3 => FIRCDIV1R::_011,
4 => FIRCDIV1R::_100,
5 => FIRCDIV1R::_101,
6 => FIRCDIV1R::_110,
7 => FIRCDIV1R::_111,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_000`"]
#[inline]
pub fn is_000(&self) -> bool {
*self == FIRCDIV1R::_000
}
#[doc = "Checks if the value of the field is `_001`"]
#[inline]
pub fn is_001(&self) -> bool {
*self == FIRCDIV1R::_001
}
#[doc = "Checks if the value of the field is `_010`"]
#[inline]
pub fn is_010(&self) -> bool {
*self == FIRCDIV1R::_010
}
#[doc = "Checks if the value of the field is `_011`"]
#[inline]
pub fn is_011(&self) -> bool {
*self == FIRCDIV1R::_011
}
#[doc = "Checks if the value of the field is `_100`"]
#[inline]
pub fn is_100(&self) -> bool {
*self == FIRCDIV1R::_100
}
#[doc = "Checks if the value of the field is `_101`"]
#[inline]
pub fn is_101(&self) -> bool {
*self == FIRCDIV1R::_101
}
#[doc = "Checks if the value of the field is `_110`"]
#[inline]
pub fn is_110(&self) -> bool {
*self == FIRCDIV1R::_110
}
#[doc = "Checks if the value of the field is `_111`"]
#[inline]
pub fn is_111(&self) -> bool {
*self == FIRCDIV1R::_111
}
}
#[doc = "Possible values of the field `FIRCDIV2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FIRCDIV2R {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl FIRCDIV2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
FIRCDIV2R::_000 => 0,
FIRCDIV2R::_001 => 1,
FIRCDIV2R::_010 => 2,
FIRCDIV2R::_011 => 3,
FIRCDIV2R::_100 => 4,
FIRCDIV2R::_101 => 5,
FIRCDIV2R::_110 => 6,
FIRCDIV2R::_111 => 7,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> FIRCDIV2R {
match value {
0 => FIRCDIV2R::_000,
1 => FIRCDIV2R::_001,
2 => FIRCDIV2R::_010,
3 => FIRCDIV2R::_011,
4 => FIRCDIV2R::_100,
5 => FIRCDIV2R::_101,
6 => FIRCDIV2R::_110,
7 => FIRCDIV2R::_111,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_000`"]
#[inline]
pub fn is_000(&self) -> bool {
*self == FIRCDIV2R::_000
}
#[doc = "Checks if the value of the field is `_001`"]
#[inline]
pub fn is_001(&self) -> bool {
*self == FIRCDIV2R::_001
}
#[doc = "Checks if the value of the field is `_010`"]
#[inline]
pub fn is_010(&self) -> bool {
*self == FIRCDIV2R::_010
}
#[doc = "Checks if the value of the field is `_011`"]
#[inline]
pub fn is_011(&self) -> bool {
*self == FIRCDIV2R::_011
}
#[doc = "Checks if the value of the field is `_100`"]
#[inline]
pub fn is_100(&self) -> bool {
*self == FIRCDIV2R::_100
}
#[doc = "Checks if the value of the field is `_101`"]
#[inline]
pub fn is_101(&self) -> bool {
*self == FIRCDIV2R::_101
}
#[doc = "Checks if the value of the field is `_110`"]
#[inline]
pub fn is_110(&self) -> bool {
*self == FIRCDIV2R::_110
}
#[doc = "Checks if the value of the field is `_111`"]
#[inline]
pub fn is_111(&self) -> bool {
*self == FIRCDIV2R::_111
}
}
#[doc = "Values that can be written to the field `FIRCDIV1`"]
pub enum FIRCDIV1W {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl FIRCDIV1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
FIRCDIV1W::_000 => 0,
FIRCDIV1W::_001 => 1,
FIRCDIV1W::_010 => 2,
FIRCDIV1W::_011 => 3,
FIRCDIV1W::_100 => 4,
FIRCDIV1W::_101 => 5,
FIRCDIV1W::_110 => 6,
FIRCDIV1W::_111 => 7,
}
}
}
#[doc = r" Proxy"]
pub struct _FIRCDIV1W<'a> {
w: &'a mut W,
}
impl<'a> _FIRCDIV1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FIRCDIV1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Output disabled"]
#[inline]
pub fn _000(self) -> &'a mut W {
self.variant(FIRCDIV1W::_000)
}
#[doc = "Divide by 1"]
#[inline]
pub fn _001(self) -> &'a mut W {
self.variant(FIRCDIV1W::_001)
}
#[doc = "Divide by 2"]
#[inline]
pub fn _010(self) -> &'a mut W {
self.variant(FIRCDIV1W::_010)
}
#[doc = "Divide by 4"]
#[inline]
pub fn _011(self) -> &'a mut W {
self.variant(FIRCDIV1W::_011)
}
#[doc = "Divide by 8"]
#[inline]
pub fn _100(self) -> &'a mut W {
self.variant(FIRCDIV1W::_100)
}
#[doc = "Divide by 16"]
#[inline]
pub fn _101(self) -> &'a mut W {
self.variant(FIRCDIV1W::_101)
}
#[doc = "Divide by 32"]
#[inline]
pub fn _110(self) -> &'a mut W {
self.variant(FIRCDIV1W::_110)
}
#[doc = "Divide by 64"]
#[inline]
pub fn _111(self) -> &'a mut W {
self.variant(FIRCDIV1W::_111)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `FIRCDIV2`"]
pub enum FIRCDIV2W {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl FIRCDIV2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
FIRCDIV2W::_000 => 0,
FIRCDIV2W::_001 => 1,
FIRCDIV2W::_010 => 2,
FIRCDIV2W::_011 => 3,
FIRCDIV2W::_100 => 4,
FIRCDIV2W::_101 => 5,
FIRCDIV2W::_110 => 6,
FIRCDIV2W::_111 => 7,
}
}
}
#[doc = r" Proxy"]
pub struct _FIRCDIV2W<'a> {
w: &'a mut W,
}
impl<'a> _FIRCDIV2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FIRCDIV2W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Output disabled"]
#[inline]
pub fn _000(self) -> &'a mut W {
self.variant(FIRCDIV2W::_000)
}
#[doc = "Divide by 1"]
#[inline]
pub fn _001(self) -> &'a mut W {
self.variant(FIRCDIV2W::_001)
}
#[doc = "Divide by 2"]
#[inline]
pub fn _010(self) -> &'a mut W {
self.variant(FIRCDIV2W::_010)
}
#[doc = "Divide by 4"]
#[inline]
pub fn _011(self) -> &'a mut W {
self.variant(FIRCDIV2W::_011)
}
#[doc = "Divide by 8"]
#[inline]
pub fn _100(self) -> &'a mut W {
self.variant(FIRCDIV2W::_100)
}
#[doc = "Divide by 16"]
#[inline]
pub fn _101(self) -> &'a mut W {
self.variant(FIRCDIV2W::_101)
}
#[doc = "Divide by 32"]
#[inline]
pub fn _110(self) -> &'a mut W {
self.variant(FIRCDIV2W::_110)
}
#[doc = "Divide by 64"]
#[inline]
pub fn _111(self) -> &'a mut W {
self.variant(FIRCDIV2W::_111)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:2 - Fast IRC Clock Divide 1"]
#[inline]
pub fn fircdiv1(&self) -> FIRCDIV1R {
FIRCDIV1R::_from({
const MASK: u8 = 7;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:10 - Fast IRC Clock Divide 2"]
#[inline]
pub fn fircdiv2(&self) -> FIRCDIV2R {
FIRCDIV2R::_from({
const MASK: u8 = 7;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:2 - Fast IRC Clock Divide 1"]
#[inline]
pub fn fircdiv1(&mut self) -> _FIRCDIV1W {
_FIRCDIV1W { w: self }
}
#[doc = "Bits 8:10 - Fast IRC Clock Divide 2"]
#[inline]
pub fn fircdiv2(&mut self) -> _FIRCDIV2W {
_FIRCDIV2W { w: self }
}
}

1084
src/scg/hccr/mod.rs Normal file
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use vcell::VolatileCell;
#[doc = r" Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - Version ID Register"]
pub verid: VERID,
#[doc = "0x04 - Parameter Register"]
pub param: PARAM,
_reserved0: [u8; 8usize],
#[doc = "0x10 - Clock Status Register"]
pub csr: CSR,
#[doc = "0x14 - Run Clock Control Register"]
pub rccr: RCCR,
#[doc = "0x18 - VLPR Clock Control Register"]
pub vccr: VCCR,
#[doc = "0x1c - HSRUN Clock Control Register"]
pub hccr: HCCR,
#[doc = "0x20 - SCG CLKOUT Configuration Register"]
pub clkoutcnfg: CLKOUTCNFG,
_reserved1: [u8; 220usize],
#[doc = "0x100 - System OSC Control Status Register"]
pub sosccsr: SOSCCSR,
#[doc = "0x104 - System OSC Divide Register"]
pub soscdiv: SOSCDIV,
#[doc = "0x108 - System Oscillator Configuration Register"]
pub sosccfg: SOSCCFG,
_reserved2: [u8; 244usize],
#[doc = "0x200 - Slow IRC Control Status Register"]
pub sirccsr: SIRCCSR,
#[doc = "0x204 - Slow IRC Divide Register"]
pub sircdiv: SIRCDIV,
#[doc = "0x208 - Slow IRC Configuration Register"]
pub sirccfg: SIRCCFG,
_reserved3: [u8; 244usize],
#[doc = "0x300 - Fast IRC Control Status Register"]
pub firccsr: FIRCCSR,
#[doc = "0x304 - Fast IRC Divide Register"]
pub fircdiv: FIRCDIV,
#[doc = "0x308 - Fast IRC Configuration Register"]
pub firccfg: FIRCCFG,
_reserved4: [u8; 756usize],
#[doc = "0x600 - System PLL Control Status Register"]
pub spllcsr: SPLLCSR,
#[doc = "0x604 - System PLL Divide Register"]
pub splldiv: SPLLDIV,
#[doc = "0x608 - System PLL Configuration Register"]
pub spllcfg: SPLLCFG,
}
#[doc = "Version ID Register"]
pub struct VERID {
register: VolatileCell<u32>,
}
#[doc = "Version ID Register"]
pub mod verid;
#[doc = "Parameter Register"]
pub struct PARAM {
register: VolatileCell<u32>,
}
#[doc = "Parameter Register"]
pub mod param;
#[doc = "Clock Status Register"]
pub struct CSR {
register: VolatileCell<u32>,
}
#[doc = "Clock Status Register"]
pub mod csr;
#[doc = "Run Clock Control Register"]
pub struct RCCR {
register: VolatileCell<u32>,
}
#[doc = "Run Clock Control Register"]
pub mod rccr;
#[doc = "VLPR Clock Control Register"]
pub struct VCCR {
register: VolatileCell<u32>,
}
#[doc = "VLPR Clock Control Register"]
pub mod vccr;
#[doc = "HSRUN Clock Control Register"]
pub struct HCCR {
register: VolatileCell<u32>,
}
#[doc = "HSRUN Clock Control Register"]
pub mod hccr;
#[doc = "SCG CLKOUT Configuration Register"]
pub struct CLKOUTCNFG {
register: VolatileCell<u32>,
}
#[doc = "SCG CLKOUT Configuration Register"]
pub mod clkoutcnfg;
#[doc = "System OSC Control Status Register"]
pub struct SOSCCSR {
register: VolatileCell<u32>,
}
#[doc = "System OSC Control Status Register"]
pub mod sosccsr;
#[doc = "System OSC Divide Register"]
pub struct SOSCDIV {
register: VolatileCell<u32>,
}
#[doc = "System OSC Divide Register"]
pub mod soscdiv;
#[doc = "System Oscillator Configuration Register"]
pub struct SOSCCFG {
register: VolatileCell<u32>,
}
#[doc = "System Oscillator Configuration Register"]
pub mod sosccfg;
#[doc = "Slow IRC Control Status Register"]
pub struct SIRCCSR {
register: VolatileCell<u32>,
}
#[doc = "Slow IRC Control Status Register"]
pub mod sirccsr;
#[doc = "Slow IRC Divide Register"]
pub struct SIRCDIV {
register: VolatileCell<u32>,
}
#[doc = "Slow IRC Divide Register"]
pub mod sircdiv;
#[doc = "Slow IRC Configuration Register"]
pub struct SIRCCFG {
register: VolatileCell<u32>,
}
#[doc = "Slow IRC Configuration Register"]
pub mod sirccfg;
#[doc = "Fast IRC Control Status Register"]
pub struct FIRCCSR {
register: VolatileCell<u32>,
}
#[doc = "Fast IRC Control Status Register"]
pub mod firccsr;
#[doc = "Fast IRC Divide Register"]
pub struct FIRCDIV {
register: VolatileCell<u32>,
}
#[doc = "Fast IRC Divide Register"]
pub mod fircdiv;
#[doc = "Fast IRC Configuration Register"]
pub struct FIRCCFG {
register: VolatileCell<u32>,
}
#[doc = "Fast IRC Configuration Register"]
pub mod firccfg;
#[doc = "System PLL Control Status Register"]
pub struct SPLLCSR {
register: VolatileCell<u32>,
}
#[doc = "System PLL Control Status Register"]
pub mod spllcsr;
#[doc = "System PLL Divide Register"]
pub struct SPLLDIV {
register: VolatileCell<u32>,
}
#[doc = "System PLL Divide Register"]
pub mod splldiv;
#[doc = "System PLL Configuration Register"]
pub struct SPLLCFG {
register: VolatileCell<u32>,
}
#[doc = "System PLL Configuration Register"]
pub mod spllcfg;

60
src/scg/param/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::PARAM {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]
pub struct CLKPRESR {
bits: u8,
}
impl CLKPRESR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct DIVPRESR {
bits: u8,
}
impl DIVPRESR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:7 - Clock Present"]
#[inline]
pub fn clkpres(&self) -> CLKPRESR {
let bits = {
const MASK: u8 = 255;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CLKPRESR { bits }
}
#[doc = "Bits 27:31 - Divider Present"]
#[inline]
pub fn divpres(&self) -> DIVPRESR {
let bits = {
const MASK: u8 = 31;
const OFFSET: u8 = 27;
((self.bits >> OFFSET) & MASK as u32) as u8
};
DIVPRESR { bits }
}
}

1084
src/scg/rccr/mod.rs Normal file
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src/scg/sirccfg/mod.rs Normal file
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SIRCCFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `RANGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RANGER {
#[doc = "Slow IRC low range clock (2 MHz)"]
_0,
#[doc = "Slow IRC high range clock (8 MHz )"]
_1,
}
impl RANGER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RANGER::_0 => false,
RANGER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RANGER {
match value {
false => RANGER::_0,
true => RANGER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == RANGER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == RANGER::_1
}
}
#[doc = "Values that can be written to the field `RANGE`"]
pub enum RANGEW {
#[doc = "Slow IRC low range clock (2 MHz)"]
_0,
#[doc = "Slow IRC high range clock (8 MHz )"]
_1,
}
impl RANGEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
RANGEW::_0 => false,
RANGEW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _RANGEW<'a> {
w: &'a mut W,
}
impl<'a> _RANGEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RANGEW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Slow IRC low range clock (2 MHz)"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(RANGEW::_0)
}
#[doc = "Slow IRC high range clock (8 MHz )"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(RANGEW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Frequency Range"]
#[inline]
pub fn range(&self) -> RANGER {
RANGER::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 1 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Frequency Range"]
#[inline]
pub fn range(&mut self) -> _RANGEW {
_RANGEW { w: self }
}
}

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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SIRCCSR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `SIRCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCENR {
#[doc = "Slow IRC is disabled"]
_0,
#[doc = "Slow IRC is enabled"]
_1,
}
impl SIRCENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SIRCENR::_0 => false,
SIRCENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SIRCENR {
match value {
false => SIRCENR::_0,
true => SIRCENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SIRCENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SIRCENR::_1
}
}
#[doc = "Possible values of the field `SIRCSTEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCSTENR {
#[doc = "Slow IRC is disabled in supported Stop modes"]
_0,
#[doc = "Slow IRC is enabled in supported Stop modes"]
_1,
}
impl SIRCSTENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SIRCSTENR::_0 => false,
SIRCSTENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SIRCSTENR {
match value {
false => SIRCSTENR::_0,
true => SIRCSTENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SIRCSTENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SIRCSTENR::_1
}
}
#[doc = "Possible values of the field `SIRCLPEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCLPENR {
#[doc = "Slow IRC is disabled in VLP modes"]
_0,
#[doc = "Slow IRC is enabled in VLP modes"]
_1,
}
impl SIRCLPENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SIRCLPENR::_0 => false,
SIRCLPENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SIRCLPENR {
match value {
false => SIRCLPENR::_0,
true => SIRCLPENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SIRCLPENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SIRCLPENR::_1
}
}
#[doc = "Possible values of the field `LK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LKR {
#[doc = "Control Status Register can be written."]
_0,
#[doc = "Control Status Register cannot be written."]
_1,
}
impl LKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
LKR::_0 => false,
LKR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> LKR {
match value {
false => LKR::_0,
true => LKR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == LKR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == LKR::_1
}
}
#[doc = "Possible values of the field `SIRCVLD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCVLDR {
#[doc = "Slow IRC is not enabled or clock is not valid"]
_0,
#[doc = "Slow IRC is enabled and output clock is valid"]
_1,
}
impl SIRCVLDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SIRCVLDR::_0 => false,
SIRCVLDR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SIRCVLDR {
match value {
false => SIRCVLDR::_0,
true => SIRCVLDR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SIRCVLDR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SIRCVLDR::_1
}
}
#[doc = "Possible values of the field `SIRCSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCSELR {
#[doc = "Slow IRC is not the system clock source"]
_0,
#[doc = "Slow IRC is the system clock source"]
_1,
}
impl SIRCSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SIRCSELR::_0 => false,
SIRCSELR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SIRCSELR {
match value {
false => SIRCSELR::_0,
true => SIRCSELR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SIRCSELR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SIRCSELR::_1
}
}
#[doc = "Values that can be written to the field `SIRCEN`"]
pub enum SIRCENW {
#[doc = "Slow IRC is disabled"]
_0,
#[doc = "Slow IRC is enabled"]
_1,
}
impl SIRCENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SIRCENW::_0 => false,
SIRCENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SIRCENW<'a> {
w: &'a mut W,
}
impl<'a> _SIRCENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SIRCENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Slow IRC is disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SIRCENW::_0)
}
#[doc = "Slow IRC is enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SIRCENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SIRCSTEN`"]
pub enum SIRCSTENW {
#[doc = "Slow IRC is disabled in supported Stop modes"]
_0,
#[doc = "Slow IRC is enabled in supported Stop modes"]
_1,
}
impl SIRCSTENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SIRCSTENW::_0 => false,
SIRCSTENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SIRCSTENW<'a> {
w: &'a mut W,
}
impl<'a> _SIRCSTENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SIRCSTENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Slow IRC is disabled in supported Stop modes"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SIRCSTENW::_0)
}
#[doc = "Slow IRC is enabled in supported Stop modes"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SIRCSTENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SIRCLPEN`"]
pub enum SIRCLPENW {
#[doc = "Slow IRC is disabled in VLP modes"]
_0,
#[doc = "Slow IRC is enabled in VLP modes"]
_1,
}
impl SIRCLPENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SIRCLPENW::_0 => false,
SIRCLPENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SIRCLPENW<'a> {
w: &'a mut W,
}
impl<'a> _SIRCLPENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SIRCLPENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Slow IRC is disabled in VLP modes"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SIRCLPENW::_0)
}
#[doc = "Slow IRC is enabled in VLP modes"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SIRCLPENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `LK`"]
pub enum LKW {
#[doc = "Control Status Register can be written."]
_0,
#[doc = "Control Status Register cannot be written."]
_1,
}
impl LKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
LKW::_0 => false,
LKW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _LKW<'a> {
w: &'a mut W,
}
impl<'a> _LKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: LKW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Control Status Register can be written."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(LKW::_0)
}
#[doc = "Control Status Register cannot be written."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(LKW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Slow IRC Enable"]
#[inline]
pub fn sircen(&self) -> SIRCENR {
SIRCENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Slow IRC Stop Enable"]
#[inline]
pub fn sircsten(&self) -> SIRCSTENR {
SIRCSTENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 2 - Slow IRC Low Power Enable"]
#[inline]
pub fn sirclpen(&self) -> SIRCLPENR {
SIRCLPENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 23 - Lock Register"]
#[inline]
pub fn lk(&self) -> LKR {
LKR::_from({
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 24 - Slow IRC Valid"]
#[inline]
pub fn sircvld(&self) -> SIRCVLDR {
SIRCVLDR::_from({
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 25 - Slow IRC Selected"]
#[inline]
pub fn sircsel(&self) -> SIRCSELR {
SIRCSELR::_from({
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 16777221 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Slow IRC Enable"]
#[inline]
pub fn sircen(&mut self) -> _SIRCENW {
_SIRCENW { w: self }
}
#[doc = "Bit 1 - Slow IRC Stop Enable"]
#[inline]
pub fn sircsten(&mut self) -> _SIRCSTENW {
_SIRCSTENW { w: self }
}
#[doc = "Bit 2 - Slow IRC Low Power Enable"]
#[inline]
pub fn sirclpen(&mut self) -> _SIRCLPENW {
_SIRCLPENW { w: self }
}
#[doc = "Bit 23 - Lock Register"]
#[inline]
pub fn lk(&mut self) -> _LKW {
_LKW { w: self }
}
}

470
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#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SIRCDIV {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `SIRCDIV1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCDIV1R {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl SIRCDIV1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
SIRCDIV1R::_000 => 0,
SIRCDIV1R::_001 => 1,
SIRCDIV1R::_010 => 2,
SIRCDIV1R::_011 => 3,
SIRCDIV1R::_100 => 4,
SIRCDIV1R::_101 => 5,
SIRCDIV1R::_110 => 6,
SIRCDIV1R::_111 => 7,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> SIRCDIV1R {
match value {
0 => SIRCDIV1R::_000,
1 => SIRCDIV1R::_001,
2 => SIRCDIV1R::_010,
3 => SIRCDIV1R::_011,
4 => SIRCDIV1R::_100,
5 => SIRCDIV1R::_101,
6 => SIRCDIV1R::_110,
7 => SIRCDIV1R::_111,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_000`"]
#[inline]
pub fn is_000(&self) -> bool {
*self == SIRCDIV1R::_000
}
#[doc = "Checks if the value of the field is `_001`"]
#[inline]
pub fn is_001(&self) -> bool {
*self == SIRCDIV1R::_001
}
#[doc = "Checks if the value of the field is `_010`"]
#[inline]
pub fn is_010(&self) -> bool {
*self == SIRCDIV1R::_010
}
#[doc = "Checks if the value of the field is `_011`"]
#[inline]
pub fn is_011(&self) -> bool {
*self == SIRCDIV1R::_011
}
#[doc = "Checks if the value of the field is `_100`"]
#[inline]
pub fn is_100(&self) -> bool {
*self == SIRCDIV1R::_100
}
#[doc = "Checks if the value of the field is `_101`"]
#[inline]
pub fn is_101(&self) -> bool {
*self == SIRCDIV1R::_101
}
#[doc = "Checks if the value of the field is `_110`"]
#[inline]
pub fn is_110(&self) -> bool {
*self == SIRCDIV1R::_110
}
#[doc = "Checks if the value of the field is `_111`"]
#[inline]
pub fn is_111(&self) -> bool {
*self == SIRCDIV1R::_111
}
}
#[doc = "Possible values of the field `SIRCDIV2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SIRCDIV2R {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl SIRCDIV2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
SIRCDIV2R::_000 => 0,
SIRCDIV2R::_001 => 1,
SIRCDIV2R::_010 => 2,
SIRCDIV2R::_011 => 3,
SIRCDIV2R::_100 => 4,
SIRCDIV2R::_101 => 5,
SIRCDIV2R::_110 => 6,
SIRCDIV2R::_111 => 7,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> SIRCDIV2R {
match value {
0 => SIRCDIV2R::_000,
1 => SIRCDIV2R::_001,
2 => SIRCDIV2R::_010,
3 => SIRCDIV2R::_011,
4 => SIRCDIV2R::_100,
5 => SIRCDIV2R::_101,
6 => SIRCDIV2R::_110,
7 => SIRCDIV2R::_111,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_000`"]
#[inline]
pub fn is_000(&self) -> bool {
*self == SIRCDIV2R::_000
}
#[doc = "Checks if the value of the field is `_001`"]
#[inline]
pub fn is_001(&self) -> bool {
*self == SIRCDIV2R::_001
}
#[doc = "Checks if the value of the field is `_010`"]
#[inline]
pub fn is_010(&self) -> bool {
*self == SIRCDIV2R::_010
}
#[doc = "Checks if the value of the field is `_011`"]
#[inline]
pub fn is_011(&self) -> bool {
*self == SIRCDIV2R::_011
}
#[doc = "Checks if the value of the field is `_100`"]
#[inline]
pub fn is_100(&self) -> bool {
*self == SIRCDIV2R::_100
}
#[doc = "Checks if the value of the field is `_101`"]
#[inline]
pub fn is_101(&self) -> bool {
*self == SIRCDIV2R::_101
}
#[doc = "Checks if the value of the field is `_110`"]
#[inline]
pub fn is_110(&self) -> bool {
*self == SIRCDIV2R::_110
}
#[doc = "Checks if the value of the field is `_111`"]
#[inline]
pub fn is_111(&self) -> bool {
*self == SIRCDIV2R::_111
}
}
#[doc = "Values that can be written to the field `SIRCDIV1`"]
pub enum SIRCDIV1W {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl SIRCDIV1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
SIRCDIV1W::_000 => 0,
SIRCDIV1W::_001 => 1,
SIRCDIV1W::_010 => 2,
SIRCDIV1W::_011 => 3,
SIRCDIV1W::_100 => 4,
SIRCDIV1W::_101 => 5,
SIRCDIV1W::_110 => 6,
SIRCDIV1W::_111 => 7,
}
}
}
#[doc = r" Proxy"]
pub struct _SIRCDIV1W<'a> {
w: &'a mut W,
}
impl<'a> _SIRCDIV1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SIRCDIV1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Output disabled"]
#[inline]
pub fn _000(self) -> &'a mut W {
self.variant(SIRCDIV1W::_000)
}
#[doc = "Divide by 1"]
#[inline]
pub fn _001(self) -> &'a mut W {
self.variant(SIRCDIV1W::_001)
}
#[doc = "Divide by 2"]
#[inline]
pub fn _010(self) -> &'a mut W {
self.variant(SIRCDIV1W::_010)
}
#[doc = "Divide by 4"]
#[inline]
pub fn _011(self) -> &'a mut W {
self.variant(SIRCDIV1W::_011)
}
#[doc = "Divide by 8"]
#[inline]
pub fn _100(self) -> &'a mut W {
self.variant(SIRCDIV1W::_100)
}
#[doc = "Divide by 16"]
#[inline]
pub fn _101(self) -> &'a mut W {
self.variant(SIRCDIV1W::_101)
}
#[doc = "Divide by 32"]
#[inline]
pub fn _110(self) -> &'a mut W {
self.variant(SIRCDIV1W::_110)
}
#[doc = "Divide by 64"]
#[inline]
pub fn _111(self) -> &'a mut W {
self.variant(SIRCDIV1W::_111)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SIRCDIV2`"]
pub enum SIRCDIV2W {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl SIRCDIV2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
SIRCDIV2W::_000 => 0,
SIRCDIV2W::_001 => 1,
SIRCDIV2W::_010 => 2,
SIRCDIV2W::_011 => 3,
SIRCDIV2W::_100 => 4,
SIRCDIV2W::_101 => 5,
SIRCDIV2W::_110 => 6,
SIRCDIV2W::_111 => 7,
}
}
}
#[doc = r" Proxy"]
pub struct _SIRCDIV2W<'a> {
w: &'a mut W,
}
impl<'a> _SIRCDIV2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SIRCDIV2W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Output disabled"]
#[inline]
pub fn _000(self) -> &'a mut W {
self.variant(SIRCDIV2W::_000)
}
#[doc = "Divide by 1"]
#[inline]
pub fn _001(self) -> &'a mut W {
self.variant(SIRCDIV2W::_001)
}
#[doc = "Divide by 2"]
#[inline]
pub fn _010(self) -> &'a mut W {
self.variant(SIRCDIV2W::_010)
}
#[doc = "Divide by 4"]
#[inline]
pub fn _011(self) -> &'a mut W {
self.variant(SIRCDIV2W::_011)
}
#[doc = "Divide by 8"]
#[inline]
pub fn _100(self) -> &'a mut W {
self.variant(SIRCDIV2W::_100)
}
#[doc = "Divide by 16"]
#[inline]
pub fn _101(self) -> &'a mut W {
self.variant(SIRCDIV2W::_101)
}
#[doc = "Divide by 32"]
#[inline]
pub fn _110(self) -> &'a mut W {
self.variant(SIRCDIV2W::_110)
}
#[doc = "Divide by 64"]
#[inline]
pub fn _111(self) -> &'a mut W {
self.variant(SIRCDIV2W::_111)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:2 - Slow IRC Clock Divide 1"]
#[inline]
pub fn sircdiv1(&self) -> SIRCDIV1R {
SIRCDIV1R::_from({
const MASK: u8 = 7;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:10 - Slow IRC Clock Divide 2"]
#[inline]
pub fn sircdiv2(&self) -> SIRCDIV2R {
SIRCDIV2R::_from({
const MASK: u8 = 7;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:2 - Slow IRC Clock Divide 1"]
#[inline]
pub fn sircdiv1(&mut self) -> _SIRCDIV1W {
_SIRCDIV1W { w: self }
}
#[doc = "Bits 8:10 - Slow IRC Clock Divide 2"]
#[inline]
pub fn sircdiv2(&mut self) -> _SIRCDIV2W {
_SIRCDIV2W { w: self }
}
}

420
src/scg/sosccfg/mod.rs Normal file
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@ -0,0 +1,420 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SOSCCFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `EREFS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum EREFSR {
#[doc = "External reference clock selected"]
_0,
#[doc = "Internal crystal oscillator of OSC selected."]
_1,
}
impl EREFSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
EREFSR::_0 => false,
EREFSR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> EREFSR {
match value {
false => EREFSR::_0,
true => EREFSR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == EREFSR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == EREFSR::_1
}
}
#[doc = "Possible values of the field `HGO`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum HGOR {
#[doc = "Configure crystal oscillator for low-gain operation"]
_0,
#[doc = "Configure crystal oscillator for high-gain operation"]
_1,
}
impl HGOR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
HGOR::_0 => false,
HGOR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> HGOR {
match value {
false => HGOR::_0,
true => HGOR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == HGOR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == HGOR::_1
}
}
#[doc = "Possible values of the field `RANGE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RANGER {
#[doc = "Low frequency range selected for the crystal oscillator"]
_01,
#[doc = "Medium frequency range selected for the crytstal oscillator"]
_10,
#[doc = "High frequency range selected for the crystal oscillator"]
_11,
#[doc = r" Reserved"]
_Reserved(u8),
}
impl RANGER {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
RANGER::_01 => 1,
RANGER::_10 => 2,
RANGER::_11 => 3,
RANGER::_Reserved(bits) => bits,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> RANGER {
match value {
1 => RANGER::_01,
2 => RANGER::_10,
3 => RANGER::_11,
i => RANGER::_Reserved(i),
}
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == RANGER::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == RANGER::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == RANGER::_11
}
}
#[doc = "Values that can be written to the field `EREFS`"]
pub enum EREFSW {
#[doc = "External reference clock selected"]
_0,
#[doc = "Internal crystal oscillator of OSC selected."]
_1,
}
impl EREFSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
EREFSW::_0 => false,
EREFSW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _EREFSW<'a> {
w: &'a mut W,
}
impl<'a> _EREFSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: EREFSW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "External reference clock selected"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(EREFSW::_0)
}
#[doc = "Internal crystal oscillator of OSC selected."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(EREFSW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 2;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `HGO`"]
pub enum HGOW {
#[doc = "Configure crystal oscillator for low-gain operation"]
_0,
#[doc = "Configure crystal oscillator for high-gain operation"]
_1,
}
impl HGOW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
HGOW::_0 => false,
HGOW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _HGOW<'a> {
w: &'a mut W,
}
impl<'a> _HGOW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: HGOW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Configure crystal oscillator for low-gain operation"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(HGOW::_0)
}
#[doc = "Configure crystal oscillator for high-gain operation"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(HGOW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RANGE`"]
pub enum RANGEW {
#[doc = "Low frequency range selected for the crystal oscillator"]
_01,
#[doc = "Medium frequency range selected for the crytstal oscillator"]
_10,
#[doc = "High frequency range selected for the crystal oscillator"]
_11,
}
impl RANGEW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
RANGEW::_01 => 1,
RANGEW::_10 => 2,
RANGEW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _RANGEW<'a> {
w: &'a mut W,
}
impl<'a> _RANGEW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: RANGEW) -> &'a mut W {
unsafe { self.bits(variant._bits()) }
}
#[doc = "Low frequency range selected for the crystal oscillator"]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(RANGEW::_01)
}
#[doc = "Medium frequency range selected for the crytstal oscillator"]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(RANGEW::_10)
}
#[doc = "High frequency range selected for the crystal oscillator"]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(RANGEW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 2 - External Reference Select"]
#[inline]
pub fn erefs(&self) -> EREFSR {
EREFSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 2;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 3 - High Gain Oscillator Select"]
#[inline]
pub fn hgo(&self) -> HGOR {
HGOR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 4:5 - System OSC Range Select"]
#[inline]
pub fn range(&self) -> RANGER {
RANGER::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 16 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 2 - External Reference Select"]
#[inline]
pub fn erefs(&mut self) -> _EREFSW {
_EREFSW { w: self }
}
#[doc = "Bit 3 - High Gain Oscillator Select"]
#[inline]
pub fn hgo(&mut self) -> _HGOW {
_HGOW { w: self }
}
#[doc = "Bits 4:5 - System OSC Range Select"]
#[inline]
pub fn range(&mut self) -> _RANGEW {
_RANGEW { w: self }
}
}

769
src/scg/sosccsr/mod.rs Normal file
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@ -0,0 +1,769 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SOSCCSR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `SOSCEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCENR {
#[doc = "System OSC is disabled"]
_0,
#[doc = "System OSC is enabled"]
_1,
}
impl SOSCENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SOSCENR::_0 => false,
SOSCENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SOSCENR {
match value {
false => SOSCENR::_0,
true => SOSCENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SOSCENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SOSCENR::_1
}
}
#[doc = "Possible values of the field `SOSCCM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCCMR {
#[doc = "System OSC Clock Monitor is disabled"]
_0,
#[doc = "System OSC Clock Monitor is enabled"]
_1,
}
impl SOSCCMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SOSCCMR::_0 => false,
SOSCCMR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SOSCCMR {
match value {
false => SOSCCMR::_0,
true => SOSCCMR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SOSCCMR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SOSCCMR::_1
}
}
#[doc = "Possible values of the field `SOSCCMRE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCCMRER {
#[doc = "Clock Monitor generates interrupt when error detected"]
_0,
#[doc = "Clock Monitor generates reset when error detected"]
_1,
}
impl SOSCCMRER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SOSCCMRER::_0 => false,
SOSCCMRER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SOSCCMRER {
match value {
false => SOSCCMRER::_0,
true => SOSCCMRER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SOSCCMRER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SOSCCMRER::_1
}
}
#[doc = "Possible values of the field `LK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LKR {
#[doc = "This Control Status Register can be written."]
_0,
#[doc = "This Control Status Register cannot be written."]
_1,
}
impl LKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
LKR::_0 => false,
LKR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> LKR {
match value {
false => LKR::_0,
true => LKR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == LKR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == LKR::_1
}
}
#[doc = "Possible values of the field `SOSCVLD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCVLDR {
#[doc = "System OSC is not enabled or clock is not valid"]
_0,
#[doc = "System OSC is enabled and output clock is valid"]
_1,
}
impl SOSCVLDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SOSCVLDR::_0 => false,
SOSCVLDR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SOSCVLDR {
match value {
false => SOSCVLDR::_0,
true => SOSCVLDR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SOSCVLDR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SOSCVLDR::_1
}
}
#[doc = "Possible values of the field `SOSCSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCSELR {
#[doc = "System OSC is not the system clock source"]
_0,
#[doc = "System OSC is the system clock source"]
_1,
}
impl SOSCSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SOSCSELR::_0 => false,
SOSCSELR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SOSCSELR {
match value {
false => SOSCSELR::_0,
true => SOSCSELR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SOSCSELR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SOSCSELR::_1
}
}
#[doc = "Possible values of the field `SOSCERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCERRR {
#[doc = "System OSC Clock Monitor is disabled or has not detected an error"]
_0,
#[doc = "System OSC Clock Monitor is enabled and detected an error"]
_1,
}
impl SOSCERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SOSCERRR::_0 => false,
SOSCERRR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SOSCERRR {
match value {
false => SOSCERRR::_0,
true => SOSCERRR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SOSCERRR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SOSCERRR::_1
}
}
#[doc = "Values that can be written to the field `SOSCEN`"]
pub enum SOSCENW {
#[doc = "System OSC is disabled"]
_0,
#[doc = "System OSC is enabled"]
_1,
}
impl SOSCENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SOSCENW::_0 => false,
SOSCENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SOSCENW<'a> {
w: &'a mut W,
}
impl<'a> _SOSCENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SOSCENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "System OSC is disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SOSCENW::_0)
}
#[doc = "System OSC is enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SOSCENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SOSCCM`"]
pub enum SOSCCMW {
#[doc = "System OSC Clock Monitor is disabled"]
_0,
#[doc = "System OSC Clock Monitor is enabled"]
_1,
}
impl SOSCCMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SOSCCMW::_0 => false,
SOSCCMW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SOSCCMW<'a> {
w: &'a mut W,
}
impl<'a> _SOSCCMW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SOSCCMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "System OSC Clock Monitor is disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SOSCCMW::_0)
}
#[doc = "System OSC Clock Monitor is enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SOSCCMW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SOSCCMRE`"]
pub enum SOSCCMREW {
#[doc = "Clock Monitor generates interrupt when error detected"]
_0,
#[doc = "Clock Monitor generates reset when error detected"]
_1,
}
impl SOSCCMREW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SOSCCMREW::_0 => false,
SOSCCMREW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SOSCCMREW<'a> {
w: &'a mut W,
}
impl<'a> _SOSCCMREW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SOSCCMREW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock Monitor generates interrupt when error detected"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SOSCCMREW::_0)
}
#[doc = "Clock Monitor generates reset when error detected"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SOSCCMREW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `LK`"]
pub enum LKW {
#[doc = "This Control Status Register can be written."]
_0,
#[doc = "This Control Status Register cannot be written."]
_1,
}
impl LKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
LKW::_0 => false,
LKW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _LKW<'a> {
w: &'a mut W,
}
impl<'a> _LKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: LKW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "This Control Status Register can be written."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(LKW::_0)
}
#[doc = "This Control Status Register cannot be written."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(LKW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SOSCERR`"]
pub enum SOSCERRW {
#[doc = "System OSC Clock Monitor is disabled or has not detected an error"]
_0,
#[doc = "System OSC Clock Monitor is enabled and detected an error"]
_1,
}
impl SOSCERRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SOSCERRW::_0 => false,
SOSCERRW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SOSCERRW<'a> {
w: &'a mut W,
}
impl<'a> _SOSCERRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SOSCERRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "System OSC Clock Monitor is disabled or has not detected an error"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SOSCERRW::_0)
}
#[doc = "System OSC Clock Monitor is enabled and detected an error"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SOSCERRW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - System OSC Enable"]
#[inline]
pub fn soscen(&self) -> SOSCENR {
SOSCENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 16 - System OSC Clock Monitor"]
#[inline]
pub fn sosccm(&self) -> SOSCCMR {
SOSCCMR::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 17 - System OSC Clock Monitor Reset Enable"]
#[inline]
pub fn sosccmre(&self) -> SOSCCMRER {
SOSCCMRER::_from({
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 23 - Lock Register"]
#[inline]
pub fn lk(&self) -> LKR {
LKR::_from({
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 24 - System OSC Valid"]
#[inline]
pub fn soscvld(&self) -> SOSCVLDR {
SOSCVLDR::_from({
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 25 - System OSC Selected"]
#[inline]
pub fn soscsel(&self) -> SOSCSELR {
SOSCSELR::_from({
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 26 - System OSC Clock Error"]
#[inline]
pub fn soscerr(&self) -> SOSCERRR {
SOSCERRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - System OSC Enable"]
#[inline]
pub fn soscen(&mut self) -> _SOSCENW {
_SOSCENW { w: self }
}
#[doc = "Bit 16 - System OSC Clock Monitor"]
#[inline]
pub fn sosccm(&mut self) -> _SOSCCMW {
_SOSCCMW { w: self }
}
#[doc = "Bit 17 - System OSC Clock Monitor Reset Enable"]
#[inline]
pub fn sosccmre(&mut self) -> _SOSCCMREW {
_SOSCCMREW { w: self }
}
#[doc = "Bit 23 - Lock Register"]
#[inline]
pub fn lk(&mut self) -> _LKW {
_LKW { w: self }
}
#[doc = "Bit 26 - System OSC Clock Error"]
#[inline]
pub fn soscerr(&mut self) -> _SOSCERRW {
_SOSCERRW { w: self }
}
}

470
src/scg/soscdiv/mod.rs Normal file
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@ -0,0 +1,470 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SOSCDIV {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `SOSCDIV1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCDIV1R {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl SOSCDIV1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
SOSCDIV1R::_000 => 0,
SOSCDIV1R::_001 => 1,
SOSCDIV1R::_010 => 2,
SOSCDIV1R::_011 => 3,
SOSCDIV1R::_100 => 4,
SOSCDIV1R::_101 => 5,
SOSCDIV1R::_110 => 6,
SOSCDIV1R::_111 => 7,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> SOSCDIV1R {
match value {
0 => SOSCDIV1R::_000,
1 => SOSCDIV1R::_001,
2 => SOSCDIV1R::_010,
3 => SOSCDIV1R::_011,
4 => SOSCDIV1R::_100,
5 => SOSCDIV1R::_101,
6 => SOSCDIV1R::_110,
7 => SOSCDIV1R::_111,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_000`"]
#[inline]
pub fn is_000(&self) -> bool {
*self == SOSCDIV1R::_000
}
#[doc = "Checks if the value of the field is `_001`"]
#[inline]
pub fn is_001(&self) -> bool {
*self == SOSCDIV1R::_001
}
#[doc = "Checks if the value of the field is `_010`"]
#[inline]
pub fn is_010(&self) -> bool {
*self == SOSCDIV1R::_010
}
#[doc = "Checks if the value of the field is `_011`"]
#[inline]
pub fn is_011(&self) -> bool {
*self == SOSCDIV1R::_011
}
#[doc = "Checks if the value of the field is `_100`"]
#[inline]
pub fn is_100(&self) -> bool {
*self == SOSCDIV1R::_100
}
#[doc = "Checks if the value of the field is `_101`"]
#[inline]
pub fn is_101(&self) -> bool {
*self == SOSCDIV1R::_101
}
#[doc = "Checks if the value of the field is `_110`"]
#[inline]
pub fn is_110(&self) -> bool {
*self == SOSCDIV1R::_110
}
#[doc = "Checks if the value of the field is `_111`"]
#[inline]
pub fn is_111(&self) -> bool {
*self == SOSCDIV1R::_111
}
}
#[doc = "Possible values of the field `SOSCDIV2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SOSCDIV2R {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl SOSCDIV2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
SOSCDIV2R::_000 => 0,
SOSCDIV2R::_001 => 1,
SOSCDIV2R::_010 => 2,
SOSCDIV2R::_011 => 3,
SOSCDIV2R::_100 => 4,
SOSCDIV2R::_101 => 5,
SOSCDIV2R::_110 => 6,
SOSCDIV2R::_111 => 7,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> SOSCDIV2R {
match value {
0 => SOSCDIV2R::_000,
1 => SOSCDIV2R::_001,
2 => SOSCDIV2R::_010,
3 => SOSCDIV2R::_011,
4 => SOSCDIV2R::_100,
5 => SOSCDIV2R::_101,
6 => SOSCDIV2R::_110,
7 => SOSCDIV2R::_111,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_000`"]
#[inline]
pub fn is_000(&self) -> bool {
*self == SOSCDIV2R::_000
}
#[doc = "Checks if the value of the field is `_001`"]
#[inline]
pub fn is_001(&self) -> bool {
*self == SOSCDIV2R::_001
}
#[doc = "Checks if the value of the field is `_010`"]
#[inline]
pub fn is_010(&self) -> bool {
*self == SOSCDIV2R::_010
}
#[doc = "Checks if the value of the field is `_011`"]
#[inline]
pub fn is_011(&self) -> bool {
*self == SOSCDIV2R::_011
}
#[doc = "Checks if the value of the field is `_100`"]
#[inline]
pub fn is_100(&self) -> bool {
*self == SOSCDIV2R::_100
}
#[doc = "Checks if the value of the field is `_101`"]
#[inline]
pub fn is_101(&self) -> bool {
*self == SOSCDIV2R::_101
}
#[doc = "Checks if the value of the field is `_110`"]
#[inline]
pub fn is_110(&self) -> bool {
*self == SOSCDIV2R::_110
}
#[doc = "Checks if the value of the field is `_111`"]
#[inline]
pub fn is_111(&self) -> bool {
*self == SOSCDIV2R::_111
}
}
#[doc = "Values that can be written to the field `SOSCDIV1`"]
pub enum SOSCDIV1W {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl SOSCDIV1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
SOSCDIV1W::_000 => 0,
SOSCDIV1W::_001 => 1,
SOSCDIV1W::_010 => 2,
SOSCDIV1W::_011 => 3,
SOSCDIV1W::_100 => 4,
SOSCDIV1W::_101 => 5,
SOSCDIV1W::_110 => 6,
SOSCDIV1W::_111 => 7,
}
}
}
#[doc = r" Proxy"]
pub struct _SOSCDIV1W<'a> {
w: &'a mut W,
}
impl<'a> _SOSCDIV1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SOSCDIV1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Output disabled"]
#[inline]
pub fn _000(self) -> &'a mut W {
self.variant(SOSCDIV1W::_000)
}
#[doc = "Divide by 1"]
#[inline]
pub fn _001(self) -> &'a mut W {
self.variant(SOSCDIV1W::_001)
}
#[doc = "Divide by 2"]
#[inline]
pub fn _010(self) -> &'a mut W {
self.variant(SOSCDIV1W::_010)
}
#[doc = "Divide by 4"]
#[inline]
pub fn _011(self) -> &'a mut W {
self.variant(SOSCDIV1W::_011)
}
#[doc = "Divide by 8"]
#[inline]
pub fn _100(self) -> &'a mut W {
self.variant(SOSCDIV1W::_100)
}
#[doc = "Divide by 16"]
#[inline]
pub fn _101(self) -> &'a mut W {
self.variant(SOSCDIV1W::_101)
}
#[doc = "Divide by 32"]
#[inline]
pub fn _110(self) -> &'a mut W {
self.variant(SOSCDIV1W::_110)
}
#[doc = "Divide by 64"]
#[inline]
pub fn _111(self) -> &'a mut W {
self.variant(SOSCDIV1W::_111)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SOSCDIV2`"]
pub enum SOSCDIV2W {
#[doc = "Output disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl SOSCDIV2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
SOSCDIV2W::_000 => 0,
SOSCDIV2W::_001 => 1,
SOSCDIV2W::_010 => 2,
SOSCDIV2W::_011 => 3,
SOSCDIV2W::_100 => 4,
SOSCDIV2W::_101 => 5,
SOSCDIV2W::_110 => 6,
SOSCDIV2W::_111 => 7,
}
}
}
#[doc = r" Proxy"]
pub struct _SOSCDIV2W<'a> {
w: &'a mut W,
}
impl<'a> _SOSCDIV2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SOSCDIV2W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Output disabled"]
#[inline]
pub fn _000(self) -> &'a mut W {
self.variant(SOSCDIV2W::_000)
}
#[doc = "Divide by 1"]
#[inline]
pub fn _001(self) -> &'a mut W {
self.variant(SOSCDIV2W::_001)
}
#[doc = "Divide by 2"]
#[inline]
pub fn _010(self) -> &'a mut W {
self.variant(SOSCDIV2W::_010)
}
#[doc = "Divide by 4"]
#[inline]
pub fn _011(self) -> &'a mut W {
self.variant(SOSCDIV2W::_011)
}
#[doc = "Divide by 8"]
#[inline]
pub fn _100(self) -> &'a mut W {
self.variant(SOSCDIV2W::_100)
}
#[doc = "Divide by 16"]
#[inline]
pub fn _101(self) -> &'a mut W {
self.variant(SOSCDIV2W::_101)
}
#[doc = "Divide by 32"]
#[inline]
pub fn _110(self) -> &'a mut W {
self.variant(SOSCDIV2W::_110)
}
#[doc = "Divide by 64"]
#[inline]
pub fn _111(self) -> &'a mut W {
self.variant(SOSCDIV2W::_111)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:2 - System OSC Clock Divide 1"]
#[inline]
pub fn soscdiv1(&self) -> SOSCDIV1R {
SOSCDIV1R::_from({
const MASK: u8 = 7;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:10 - System OSC Clock Divide 2"]
#[inline]
pub fn soscdiv2(&self) -> SOSCDIV2R {
SOSCDIV2R::_from({
const MASK: u8 = 7;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:2 - System OSC Clock Divide 1"]
#[inline]
pub fn soscdiv1(&mut self) -> _SOSCDIV1W {
_SOSCDIV1W { w: self }
}
#[doc = "Bits 8:10 - System OSC Clock Divide 2"]
#[inline]
pub fn soscdiv2(&mut self) -> _SOSCDIV2W {
_SOSCDIV2W { w: self }
}
}

144
src/scg/spllcfg/mod.rs Normal file
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@ -0,0 +1,144 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SPLLCFG {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = r" Value of the field"]
pub struct PREDIVR {
bits: u8,
}
impl PREDIVR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct MULTR {
bits: u8,
}
impl MULTR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Proxy"]
pub struct _PREDIVW<'a> {
w: &'a mut W,
}
impl<'a> _PREDIVW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _MULTW<'a> {
w: &'a mut W,
}
impl<'a> _MULTW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 31;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 8:10 - PLL Reference Clock Divider"]
#[inline]
pub fn prediv(&self) -> PREDIVR {
let bits = {
const MASK: u8 = 7;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
PREDIVR { bits }
}
#[doc = "Bits 16:20 - System PLL Multiplier"]
#[inline]
pub fn mult(&self) -> MULTR {
let bits = {
const MASK: u8 = 31;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) as u8
};
MULTR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 8:10 - PLL Reference Clock Divider"]
#[inline]
pub fn prediv(&mut self) -> _PREDIVW {
_PREDIVW { w: self }
}
#[doc = "Bits 16:20 - System PLL Multiplier"]
#[inline]
pub fn mult(&mut self) -> _MULTW {
_MULTW { w: self }
}
}

769
src/scg/spllcsr/mod.rs Normal file
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@ -0,0 +1,769 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SPLLCSR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `SPLLEN`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLENR {
#[doc = "System PLL is disabled"]
_0,
#[doc = "System PLL is enabled"]
_1,
}
impl SPLLENR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SPLLENR::_0 => false,
SPLLENR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SPLLENR {
match value {
false => SPLLENR::_0,
true => SPLLENR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SPLLENR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SPLLENR::_1
}
}
#[doc = "Possible values of the field `SPLLCM`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLCMR {
#[doc = "System PLL Clock Monitor is disabled"]
_0,
#[doc = "System PLL Clock Monitor is enabled"]
_1,
}
impl SPLLCMR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SPLLCMR::_0 => false,
SPLLCMR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SPLLCMR {
match value {
false => SPLLCMR::_0,
true => SPLLCMR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SPLLCMR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SPLLCMR::_1
}
}
#[doc = "Possible values of the field `SPLLCMRE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLCMRER {
#[doc = "Clock Monitor generates interrupt when error detected"]
_0,
#[doc = "Clock Monitor generates reset when error detected"]
_1,
}
impl SPLLCMRER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SPLLCMRER::_0 => false,
SPLLCMRER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SPLLCMRER {
match value {
false => SPLLCMRER::_0,
true => SPLLCMRER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SPLLCMRER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SPLLCMRER::_1
}
}
#[doc = "Possible values of the field `LK`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum LKR {
#[doc = "Control Status Register can be written."]
_0,
#[doc = "Control Status Register cannot be written."]
_1,
}
impl LKR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
LKR::_0 => false,
LKR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> LKR {
match value {
false => LKR::_0,
true => LKR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == LKR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == LKR::_1
}
}
#[doc = "Possible values of the field `SPLLVLD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLVLDR {
#[doc = "System PLL is not enabled or clock is not valid"]
_0,
#[doc = "System PLL is enabled and output clock is valid"]
_1,
}
impl SPLLVLDR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SPLLVLDR::_0 => false,
SPLLVLDR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SPLLVLDR {
match value {
false => SPLLVLDR::_0,
true => SPLLVLDR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SPLLVLDR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SPLLVLDR::_1
}
}
#[doc = "Possible values of the field `SPLLSEL`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLSELR {
#[doc = "System PLL is not the system clock source"]
_0,
#[doc = "System PLL is the system clock source"]
_1,
}
impl SPLLSELR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SPLLSELR::_0 => false,
SPLLSELR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SPLLSELR {
match value {
false => SPLLSELR::_0,
true => SPLLSELR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SPLLSELR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SPLLSELR::_1
}
}
#[doc = "Possible values of the field `SPLLERR`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLERRR {
#[doc = "System PLL Clock Monitor is disabled or has not detected an error"]
_0,
#[doc = "System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set."]
_1,
}
impl SPLLERRR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
SPLLERRR::_0 => false,
SPLLERRR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> SPLLERRR {
match value {
false => SPLLERRR::_0,
true => SPLLERRR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == SPLLERRR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == SPLLERRR::_1
}
}
#[doc = "Values that can be written to the field `SPLLEN`"]
pub enum SPLLENW {
#[doc = "System PLL is disabled"]
_0,
#[doc = "System PLL is enabled"]
_1,
}
impl SPLLENW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SPLLENW::_0 => false,
SPLLENW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SPLLENW<'a> {
w: &'a mut W,
}
impl<'a> _SPLLENW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SPLLENW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "System PLL is disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SPLLENW::_0)
}
#[doc = "System PLL is enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SPLLENW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SPLLCM`"]
pub enum SPLLCMW {
#[doc = "System PLL Clock Monitor is disabled"]
_0,
#[doc = "System PLL Clock Monitor is enabled"]
_1,
}
impl SPLLCMW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SPLLCMW::_0 => false,
SPLLCMW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SPLLCMW<'a> {
w: &'a mut W,
}
impl<'a> _SPLLCMW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SPLLCMW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "System PLL Clock Monitor is disabled"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SPLLCMW::_0)
}
#[doc = "System PLL Clock Monitor is enabled"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SPLLCMW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 16;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SPLLCMRE`"]
pub enum SPLLCMREW {
#[doc = "Clock Monitor generates interrupt when error detected"]
_0,
#[doc = "Clock Monitor generates reset when error detected"]
_1,
}
impl SPLLCMREW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SPLLCMREW::_0 => false,
SPLLCMREW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SPLLCMREW<'a> {
w: &'a mut W,
}
impl<'a> _SPLLCMREW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SPLLCMREW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock Monitor generates interrupt when error detected"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SPLLCMREW::_0)
}
#[doc = "Clock Monitor generates reset when error detected"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SPLLCMREW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 17;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `LK`"]
pub enum LKW {
#[doc = "Control Status Register can be written."]
_0,
#[doc = "Control Status Register cannot be written."]
_1,
}
impl LKW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
LKW::_0 => false,
LKW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _LKW<'a> {
w: &'a mut W,
}
impl<'a> _LKW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: LKW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Control Status Register can be written."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(LKW::_0)
}
#[doc = "Control Status Register cannot be written."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(LKW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 23;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SPLLERR`"]
pub enum SPLLERRW {
#[doc = "System PLL Clock Monitor is disabled or has not detected an error"]
_0,
#[doc = "System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set."]
_1,
}
impl SPLLERRW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
SPLLERRW::_0 => false,
SPLLERRW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _SPLLERRW<'a> {
w: &'a mut W,
}
impl<'a> _SPLLERRW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SPLLERRW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "System PLL Clock Monitor is disabled or has not detected an error"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(SPLLERRW::_0)
}
#[doc = "System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(SPLLERRW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 26;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - System PLL Enable"]
#[inline]
pub fn spllen(&self) -> SPLLENR {
SPLLENR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 16 - System PLL Clock Monitor"]
#[inline]
pub fn spllcm(&self) -> SPLLCMR {
SPLLCMR::_from({
const MASK: bool = true;
const OFFSET: u8 = 16;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 17 - System PLL Clock Monitor Reset Enable"]
#[inline]
pub fn spllcmre(&self) -> SPLLCMRER {
SPLLCMRER::_from({
const MASK: bool = true;
const OFFSET: u8 = 17;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 23 - Lock Register"]
#[inline]
pub fn lk(&self) -> LKR {
LKR::_from({
const MASK: bool = true;
const OFFSET: u8 = 23;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 24 - System PLL Valid"]
#[inline]
pub fn spllvld(&self) -> SPLLVLDR {
SPLLVLDR::_from({
const MASK: bool = true;
const OFFSET: u8 = 24;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 25 - System PLL Selected"]
#[inline]
pub fn spllsel(&self) -> SPLLSELR {
SPLLSELR::_from({
const MASK: bool = true;
const OFFSET: u8 = 25;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 26 - System PLL Clock Error"]
#[inline]
pub fn spllerr(&self) -> SPLLERRR {
SPLLERRR::_from({
const MASK: bool = true;
const OFFSET: u8 = 26;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - System PLL Enable"]
#[inline]
pub fn spllen(&mut self) -> _SPLLENW {
_SPLLENW { w: self }
}
#[doc = "Bit 16 - System PLL Clock Monitor"]
#[inline]
pub fn spllcm(&mut self) -> _SPLLCMW {
_SPLLCMW { w: self }
}
#[doc = "Bit 17 - System PLL Clock Monitor Reset Enable"]
#[inline]
pub fn spllcmre(&mut self) -> _SPLLCMREW {
_SPLLCMREW { w: self }
}
#[doc = "Bit 23 - Lock Register"]
#[inline]
pub fn lk(&mut self) -> _LKW {
_LKW { w: self }
}
#[doc = "Bit 26 - System PLL Clock Error"]
#[inline]
pub fn spllerr(&mut self) -> _SPLLERRW {
_SPLLERRW { w: self }
}
}

470
src/scg/splldiv/mod.rs Normal file
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@ -0,0 +1,470 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::SPLLDIV {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `SPLLDIV1`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLDIV1R {
#[doc = "Clock disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl SPLLDIV1R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
SPLLDIV1R::_000 => 0,
SPLLDIV1R::_001 => 1,
SPLLDIV1R::_010 => 2,
SPLLDIV1R::_011 => 3,
SPLLDIV1R::_100 => 4,
SPLLDIV1R::_101 => 5,
SPLLDIV1R::_110 => 6,
SPLLDIV1R::_111 => 7,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> SPLLDIV1R {
match value {
0 => SPLLDIV1R::_000,
1 => SPLLDIV1R::_001,
2 => SPLLDIV1R::_010,
3 => SPLLDIV1R::_011,
4 => SPLLDIV1R::_100,
5 => SPLLDIV1R::_101,
6 => SPLLDIV1R::_110,
7 => SPLLDIV1R::_111,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_000`"]
#[inline]
pub fn is_000(&self) -> bool {
*self == SPLLDIV1R::_000
}
#[doc = "Checks if the value of the field is `_001`"]
#[inline]
pub fn is_001(&self) -> bool {
*self == SPLLDIV1R::_001
}
#[doc = "Checks if the value of the field is `_010`"]
#[inline]
pub fn is_010(&self) -> bool {
*self == SPLLDIV1R::_010
}
#[doc = "Checks if the value of the field is `_011`"]
#[inline]
pub fn is_011(&self) -> bool {
*self == SPLLDIV1R::_011
}
#[doc = "Checks if the value of the field is `_100`"]
#[inline]
pub fn is_100(&self) -> bool {
*self == SPLLDIV1R::_100
}
#[doc = "Checks if the value of the field is `_101`"]
#[inline]
pub fn is_101(&self) -> bool {
*self == SPLLDIV1R::_101
}
#[doc = "Checks if the value of the field is `_110`"]
#[inline]
pub fn is_110(&self) -> bool {
*self == SPLLDIV1R::_110
}
#[doc = "Checks if the value of the field is `_111`"]
#[inline]
pub fn is_111(&self) -> bool {
*self == SPLLDIV1R::_111
}
}
#[doc = "Possible values of the field `SPLLDIV2`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum SPLLDIV2R {
#[doc = "Clock disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl SPLLDIV2R {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
SPLLDIV2R::_000 => 0,
SPLLDIV2R::_001 => 1,
SPLLDIV2R::_010 => 2,
SPLLDIV2R::_011 => 3,
SPLLDIV2R::_100 => 4,
SPLLDIV2R::_101 => 5,
SPLLDIV2R::_110 => 6,
SPLLDIV2R::_111 => 7,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> SPLLDIV2R {
match value {
0 => SPLLDIV2R::_000,
1 => SPLLDIV2R::_001,
2 => SPLLDIV2R::_010,
3 => SPLLDIV2R::_011,
4 => SPLLDIV2R::_100,
5 => SPLLDIV2R::_101,
6 => SPLLDIV2R::_110,
7 => SPLLDIV2R::_111,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_000`"]
#[inline]
pub fn is_000(&self) -> bool {
*self == SPLLDIV2R::_000
}
#[doc = "Checks if the value of the field is `_001`"]
#[inline]
pub fn is_001(&self) -> bool {
*self == SPLLDIV2R::_001
}
#[doc = "Checks if the value of the field is `_010`"]
#[inline]
pub fn is_010(&self) -> bool {
*self == SPLLDIV2R::_010
}
#[doc = "Checks if the value of the field is `_011`"]
#[inline]
pub fn is_011(&self) -> bool {
*self == SPLLDIV2R::_011
}
#[doc = "Checks if the value of the field is `_100`"]
#[inline]
pub fn is_100(&self) -> bool {
*self == SPLLDIV2R::_100
}
#[doc = "Checks if the value of the field is `_101`"]
#[inline]
pub fn is_101(&self) -> bool {
*self == SPLLDIV2R::_101
}
#[doc = "Checks if the value of the field is `_110`"]
#[inline]
pub fn is_110(&self) -> bool {
*self == SPLLDIV2R::_110
}
#[doc = "Checks if the value of the field is `_111`"]
#[inline]
pub fn is_111(&self) -> bool {
*self == SPLLDIV2R::_111
}
}
#[doc = "Values that can be written to the field `SPLLDIV1`"]
pub enum SPLLDIV1W {
#[doc = "Clock disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl SPLLDIV1W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
SPLLDIV1W::_000 => 0,
SPLLDIV1W::_001 => 1,
SPLLDIV1W::_010 => 2,
SPLLDIV1W::_011 => 3,
SPLLDIV1W::_100 => 4,
SPLLDIV1W::_101 => 5,
SPLLDIV1W::_110 => 6,
SPLLDIV1W::_111 => 7,
}
}
}
#[doc = r" Proxy"]
pub struct _SPLLDIV1W<'a> {
w: &'a mut W,
}
impl<'a> _SPLLDIV1W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SPLLDIV1W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Clock disabled"]
#[inline]
pub fn _000(self) -> &'a mut W {
self.variant(SPLLDIV1W::_000)
}
#[doc = "Divide by 1"]
#[inline]
pub fn _001(self) -> &'a mut W {
self.variant(SPLLDIV1W::_001)
}
#[doc = "Divide by 2"]
#[inline]
pub fn _010(self) -> &'a mut W {
self.variant(SPLLDIV1W::_010)
}
#[doc = "Divide by 4"]
#[inline]
pub fn _011(self) -> &'a mut W {
self.variant(SPLLDIV1W::_011)
}
#[doc = "Divide by 8"]
#[inline]
pub fn _100(self) -> &'a mut W {
self.variant(SPLLDIV1W::_100)
}
#[doc = "Divide by 16"]
#[inline]
pub fn _101(self) -> &'a mut W {
self.variant(SPLLDIV1W::_101)
}
#[doc = "Divide by 32"]
#[inline]
pub fn _110(self) -> &'a mut W {
self.variant(SPLLDIV1W::_110)
}
#[doc = "Divide by 64"]
#[inline]
pub fn _111(self) -> &'a mut W {
self.variant(SPLLDIV1W::_111)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `SPLLDIV2`"]
pub enum SPLLDIV2W {
#[doc = "Clock disabled"]
_000,
#[doc = "Divide by 1"]
_001,
#[doc = "Divide by 2"]
_010,
#[doc = "Divide by 4"]
_011,
#[doc = "Divide by 8"]
_100,
#[doc = "Divide by 16"]
_101,
#[doc = "Divide by 32"]
_110,
#[doc = "Divide by 64"]
_111,
}
impl SPLLDIV2W {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
SPLLDIV2W::_000 => 0,
SPLLDIV2W::_001 => 1,
SPLLDIV2W::_010 => 2,
SPLLDIV2W::_011 => 3,
SPLLDIV2W::_100 => 4,
SPLLDIV2W::_101 => 5,
SPLLDIV2W::_110 => 6,
SPLLDIV2W::_111 => 7,
}
}
}
#[doc = r" Proxy"]
pub struct _SPLLDIV2W<'a> {
w: &'a mut W,
}
impl<'a> _SPLLDIV2W<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: SPLLDIV2W) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "Clock disabled"]
#[inline]
pub fn _000(self) -> &'a mut W {
self.variant(SPLLDIV2W::_000)
}
#[doc = "Divide by 1"]
#[inline]
pub fn _001(self) -> &'a mut W {
self.variant(SPLLDIV2W::_001)
}
#[doc = "Divide by 2"]
#[inline]
pub fn _010(self) -> &'a mut W {
self.variant(SPLLDIV2W::_010)
}
#[doc = "Divide by 4"]
#[inline]
pub fn _011(self) -> &'a mut W {
self.variant(SPLLDIV2W::_011)
}
#[doc = "Divide by 8"]
#[inline]
pub fn _100(self) -> &'a mut W {
self.variant(SPLLDIV2W::_100)
}
#[doc = "Divide by 16"]
#[inline]
pub fn _101(self) -> &'a mut W {
self.variant(SPLLDIV2W::_101)
}
#[doc = "Divide by 32"]
#[inline]
pub fn _110(self) -> &'a mut W {
self.variant(SPLLDIV2W::_110)
}
#[doc = "Divide by 64"]
#[inline]
pub fn _111(self) -> &'a mut W {
self.variant(SPLLDIV2W::_111)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:2 - System PLL Clock Divide 1"]
#[inline]
pub fn splldiv1(&self) -> SPLLDIV1R {
SPLLDIV1R::_from({
const MASK: u8 = 7;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bits 8:10 - System PLL Clock Divide 2"]
#[inline]
pub fn splldiv2(&self) -> SPLLDIV2R {
SPLLDIV2R::_from({
const MASK: u8 = 7;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bits 0:2 - System PLL Clock Divide 1"]
#[inline]
pub fn splldiv1(&mut self) -> _SPLLDIV1W {
_SPLLDIV1W { w: self }
}
#[doc = "Bits 8:10 - System PLL Clock Divide 2"]
#[inline]
pub fn splldiv2(&mut self) -> _SPLLDIV2W {
_SPLLDIV2W { w: self }
}
}

1033
src/scg/vccr/mod.rs Normal file
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39
src/scg/verid/mod.rs Normal file
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@ -0,0 +1,39 @@
#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
impl super::VERID {
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R { bits: self.register.get() }
}
}
#[doc = r" Value of the field"]
pub struct VERSIONR {
bits: u32,
}
impl VERSIONR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bits 0:31 - SCG Version Number"]
#[inline]
pub fn version(&self) -> VERSIONR {
let bits = {
const MASK: u32 = 4294967295;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) as u32
};
VERSIONR { bits }
}
}