Same as last commit just run through the form tool (splits up large lib.rs files)

src/rtc/cr/mod.rs

@@ -0,0 +1,763 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `SWR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SWRR {
+    #[doc = "No effect."]
+    _0,
+    #[doc = r" Reserved"]
+    _Reserved(bool),
+}
+impl SWRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SWRR::_0 => false,
+            SWRR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SWRR {
+        match value {
+            false => SWRR::_0,
+            i => SWRR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SWRR::_0
+    }
+}
+#[doc = "Possible values of the field `SUP`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SUPR {
+    #[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."]
+    _0,
+    #[doc = "Non-supervisor mode write accesses are supported."]
+    _1,
+}
+impl SUPR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SUPR::_0 => false,
+            SUPR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SUPR {
+        match value {
+            false => SUPR::_0,
+            true => SUPR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SUPR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SUPR::_1
+    }
+}
+#[doc = "Possible values of the field `UM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum UMR {
+    #[doc = "Registers cannot be written when locked."]
+    _0,
+    #[doc = "Registers can be written when locked under limited conditions."]
+    _1,
+}
+impl UMR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            UMR::_0 => false,
+            UMR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> UMR {
+        match value {
+            false => UMR::_0,
+            true => UMR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == UMR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == UMR::_1
+    }
+}
+#[doc = "Possible values of the field `CPS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CPSR {
+    #[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."]
+    _0,
+    #[doc = "The RTC 32kHz crystal clock is output on RTC_CLKOUT, provided it is output to other peripherals."]
+    _1,
+}
+impl CPSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CPSR::_0 => false,
+            CPSR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CPSR {
+        match value {
+            false => CPSR::_0,
+            true => CPSR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CPSR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CPSR::_1
+    }
+}
+#[doc = "Possible values of the field `LPOS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LPOSR {
+    #[doc = "RTC prescaler increments using 32kHz crystal."]
+    _0,
+    #[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."]
+    _1,
+}
+impl LPOSR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LPOSR::_0 => false,
+            LPOSR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LPOSR {
+        match value {
+            false => LPOSR::_0,
+            true => LPOSR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == LPOSR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == LPOSR::_1
+    }
+}
+#[doc = "Possible values of the field `CPE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CPER {
+    #[doc = "Disable RTC_CLKOUT pin."]
+    _0,
+    #[doc = "Enable RTC_CLKOUT pin."]
+    _1,
+}
+impl CPER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CPER::_0 => false,
+            CPER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CPER {
+        match value {
+            false => CPER::_0,
+            true => CPER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CPER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CPER::_1
+    }
+}
+#[doc = "Values that can be written to the field `SWR`"]
+pub enum SWRW {
+    #[doc = "No effect."]
+    _0,
+}
+impl SWRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SWRW::_0 => false,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SWRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SWRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SWRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No effect."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SWRW::_0)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SUP`"]
+pub enum SUPW {
+    #[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."]
+    _0,
+    #[doc = "Non-supervisor mode write accesses are supported."]
+    _1,
+}
+impl SUPW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SUPW::_0 => false,
+            SUPW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SUPW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SUPW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SUPW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Non-supervisor mode write accesses are not supported and generate a bus error."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SUPW::_0)
+    }
+    #[doc = "Non-supervisor mode write accesses are supported."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SUPW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `UM`"]
+pub enum UMW {
+    #[doc = "Registers cannot be written when locked."]
+    _0,
+    #[doc = "Registers can be written when locked under limited conditions."]
+    _1,
+}
+impl UMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            UMW::_0 => false,
+            UMW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _UMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _UMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: UMW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Registers cannot be written when locked."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(UMW::_0)
+    }
+    #[doc = "Registers can be written when locked under limited conditions."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(UMW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CPS`"]
+pub enum CPSW {
+    #[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."]
+    _0,
+    #[doc = "The RTC 32kHz crystal clock is output on RTC_CLKOUT, provided it is output to other peripherals."]
+    _1,
+}
+impl CPSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CPSW::_0 => false,
+            CPSW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CPSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CPSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CPSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CPSW::_0)
+    }
+    #[doc = "The RTC 32kHz crystal clock is output on RTC_CLKOUT, provided it is output to other peripherals."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CPSW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `LPOS`"]
+pub enum LPOSW {
+    #[doc = "RTC prescaler increments using 32kHz crystal."]
+    _0,
+    #[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."]
+    _1,
+}
+impl LPOSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            LPOSW::_0 => false,
+            LPOSW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LPOSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LPOSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LPOSW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "RTC prescaler increments using 32kHz crystal."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(LPOSW::_0)
+    }
+    #[doc = "RTC prescaler increments using 1kHz LPO, bits [4:0] of the prescaler are ignored."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(LPOSW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CPE`"]
+pub enum CPEW {
+    #[doc = "Disable RTC_CLKOUT pin."]
+    _0,
+    #[doc = "Enable RTC_CLKOUT pin."]
+    _1,
+}
+impl CPEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CPEW::_0 => false,
+            CPEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CPEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CPEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CPEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable RTC_CLKOUT pin."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CPEW::_0)
+    }
+    #[doc = "Enable RTC_CLKOUT pin."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CPEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 24;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Software Reset"]
+    #[inline]
+    pub fn swr(&self) -> SWRR {
+        SWRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Supervisor Access"]
+    #[inline]
+    pub fn sup(&self) -> SUPR {
+        SUPR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Update Mode"]
+    #[inline]
+    pub fn um(&self) -> UMR {
+        UMR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - Clock Pin Select"]
+    #[inline]
+    pub fn cps(&self) -> CPSR {
+        CPSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - LPO Select"]
+    #[inline]
+    pub fn lpos(&self) -> LPOSR {
+        LPOSR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 24 - Clock Pin Enable"]
+    #[inline]
+    pub fn cpe(&self) -> CPER {
+        CPER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Software Reset"]
+    #[inline]
+    pub fn swr(&mut self) -> _SWRW {
+        _SWRW { w: self }
+    }
+    #[doc = "Bit 2 - Supervisor Access"]
+    #[inline]
+    pub fn sup(&mut self) -> _SUPW {
+        _SUPW { w: self }
+    }
+    #[doc = "Bit 3 - Update Mode"]
+    #[inline]
+    pub fn um(&mut self) -> _UMW {
+        _UMW { w: self }
+    }
+    #[doc = "Bit 5 - Clock Pin Select"]
+    #[inline]
+    pub fn cps(&mut self) -> _CPSW {
+        _CPSW { w: self }
+    }
+    #[doc = "Bit 7 - LPO Select"]
+    #[inline]
+    pub fn lpos(&mut self) -> _LPOSW {
+        _LPOSW { w: self }
+    }
+    #[doc = "Bit 24 - Clock Pin Enable"]
+    #[inline]
+    pub fn cpe(&mut self) -> _CPEW {
+        _CPEW { w: self }
+    }
+}

src/rtc/ier/mod.rs

@@ -0,0 +1,742 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::IER {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TIIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TIIER {
+    #[doc = "Time invalid flag does not generate an interrupt."]
+    _0,
+    #[doc = "Time invalid flag does generate an interrupt."]
+    _1,
+}
+impl TIIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TIIER::_0 => false,
+            TIIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TIIER {
+        match value {
+            false => TIIER::_0,
+            true => TIIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TIIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TIIER::_1
+    }
+}
+#[doc = "Possible values of the field `TOIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TOIER {
+    #[doc = "Time overflow flag does not generate an interrupt."]
+    _0,
+    #[doc = "Time overflow flag does generate an interrupt."]
+    _1,
+}
+impl TOIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TOIER::_0 => false,
+            TOIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TOIER {
+        match value {
+            false => TOIER::_0,
+            true => TOIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TOIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TOIER::_1
+    }
+}
+#[doc = "Possible values of the field `TAIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAIER {
+    #[doc = "Time alarm flag does not generate an interrupt."]
+    _0,
+    #[doc = "Time alarm flag does generate an interrupt."]
+    _1,
+}
+impl TAIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TAIER::_0 => false,
+            TAIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TAIER {
+        match value {
+            false => TAIER::_0,
+            true => TAIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TAIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TAIER::_1
+    }
+}
+#[doc = "Possible values of the field `TSIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TSIER {
+    #[doc = "Seconds interrupt is disabled."]
+    _0,
+    #[doc = "Seconds interrupt is enabled."]
+    _1,
+}
+impl TSIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TSIER::_0 => false,
+            TSIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TSIER {
+        match value {
+            false => TSIER::_0,
+            true => TSIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TSIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TSIER::_1
+    }
+}
+#[doc = "Possible values of the field `TSIC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TSICR {
+    #[doc = "1 Hz."]
+    _000,
+    #[doc = "2 Hz."]
+    _001,
+    #[doc = "4 Hz."]
+    _010,
+    #[doc = "8 Hz."]
+    _011,
+    #[doc = "16 Hz."]
+    _100,
+    #[doc = "32 Hz."]
+    _101,
+    #[doc = "64 Hz."]
+    _110,
+    #[doc = "128 Hz."]
+    _111,
+}
+impl TSICR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TSICR::_000 => 0,
+            TSICR::_001 => 1,
+            TSICR::_010 => 2,
+            TSICR::_011 => 3,
+            TSICR::_100 => 4,
+            TSICR::_101 => 5,
+            TSICR::_110 => 6,
+            TSICR::_111 => 7,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TSICR {
+        match value {
+            0 => TSICR::_000,
+            1 => TSICR::_001,
+            2 => TSICR::_010,
+            3 => TSICR::_011,
+            4 => TSICR::_100,
+            5 => TSICR::_101,
+            6 => TSICR::_110,
+            7 => TSICR::_111,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_000`"]
+    #[inline]
+    pub fn is_000(&self) -> bool {
+        *self == TSICR::_000
+    }
+    #[doc = "Checks if the value of the field is `_001`"]
+    #[inline]
+    pub fn is_001(&self) -> bool {
+        *self == TSICR::_001
+    }
+    #[doc = "Checks if the value of the field is `_010`"]
+    #[inline]
+    pub fn is_010(&self) -> bool {
+        *self == TSICR::_010
+    }
+    #[doc = "Checks if the value of the field is `_011`"]
+    #[inline]
+    pub fn is_011(&self) -> bool {
+        *self == TSICR::_011
+    }
+    #[doc = "Checks if the value of the field is `_100`"]
+    #[inline]
+    pub fn is_100(&self) -> bool {
+        *self == TSICR::_100
+    }
+    #[doc = "Checks if the value of the field is `_101`"]
+    #[inline]
+    pub fn is_101(&self) -> bool {
+        *self == TSICR::_101
+    }
+    #[doc = "Checks if the value of the field is `_110`"]
+    #[inline]
+    pub fn is_110(&self) -> bool {
+        *self == TSICR::_110
+    }
+    #[doc = "Checks if the value of the field is `_111`"]
+    #[inline]
+    pub fn is_111(&self) -> bool {
+        *self == TSICR::_111
+    }
+}
+#[doc = "Values that can be written to the field `TIIE`"]
+pub enum TIIEW {
+    #[doc = "Time invalid flag does not generate an interrupt."]
+    _0,
+    #[doc = "Time invalid flag does generate an interrupt."]
+    _1,
+}
+impl TIIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TIIEW::_0 => false,
+            TIIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TIIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TIIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TIIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Time invalid flag does not generate an interrupt."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TIIEW::_0)
+    }
+    #[doc = "Time invalid flag does generate an interrupt."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TIIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TOIE`"]
+pub enum TOIEW {
+    #[doc = "Time overflow flag does not generate an interrupt."]
+    _0,
+    #[doc = "Time overflow flag does generate an interrupt."]
+    _1,
+}
+impl TOIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TOIEW::_0 => false,
+            TOIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TOIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TOIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TOIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Time overflow flag does not generate an interrupt."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TOIEW::_0)
+    }
+    #[doc = "Time overflow flag does generate an interrupt."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TOIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TAIE`"]
+pub enum TAIEW {
+    #[doc = "Time alarm flag does not generate an interrupt."]
+    _0,
+    #[doc = "Time alarm flag does generate an interrupt."]
+    _1,
+}
+impl TAIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TAIEW::_0 => false,
+            TAIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TAIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TAIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TAIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Time alarm flag does not generate an interrupt."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TAIEW::_0)
+    }
+    #[doc = "Time alarm flag does generate an interrupt."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TAIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TSIE`"]
+pub enum TSIEW {
+    #[doc = "Seconds interrupt is disabled."]
+    _0,
+    #[doc = "Seconds interrupt is enabled."]
+    _1,
+}
+impl TSIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TSIEW::_0 => false,
+            TSIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TSIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TSIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TSIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Seconds interrupt is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TSIEW::_0)
+    }
+    #[doc = "Seconds interrupt is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TSIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TSIC`"]
+pub enum TSICW {
+    #[doc = "1 Hz."]
+    _000,
+    #[doc = "2 Hz."]
+    _001,
+    #[doc = "4 Hz."]
+    _010,
+    #[doc = "8 Hz."]
+    _011,
+    #[doc = "16 Hz."]
+    _100,
+    #[doc = "32 Hz."]
+    _101,
+    #[doc = "64 Hz."]
+    _110,
+    #[doc = "128 Hz."]
+    _111,
+}
+impl TSICW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TSICW::_000 => 0,
+            TSICW::_001 => 1,
+            TSICW::_010 => 2,
+            TSICW::_011 => 3,
+            TSICW::_100 => 4,
+            TSICW::_101 => 5,
+            TSICW::_110 => 6,
+            TSICW::_111 => 7,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TSICW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TSICW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TSICW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "1 Hz."]
+    #[inline]
+    pub fn _000(self) -> &'a mut W {
+        self.variant(TSICW::_000)
+    }
+    #[doc = "2 Hz."]
+    #[inline]
+    pub fn _001(self) -> &'a mut W {
+        self.variant(TSICW::_001)
+    }
+    #[doc = "4 Hz."]
+    #[inline]
+    pub fn _010(self) -> &'a mut W {
+        self.variant(TSICW::_010)
+    }
+    #[doc = "8 Hz."]
+    #[inline]
+    pub fn _011(self) -> &'a mut W {
+        self.variant(TSICW::_011)
+    }
+    #[doc = "16 Hz."]
+    #[inline]
+    pub fn _100(self) -> &'a mut W {
+        self.variant(TSICW::_100)
+    }
+    #[doc = "32 Hz."]
+    #[inline]
+    pub fn _101(self) -> &'a mut W {
+        self.variant(TSICW::_101)
+    }
+    #[doc = "64 Hz."]
+    #[inline]
+    pub fn _110(self) -> &'a mut W {
+        self.variant(TSICW::_110)
+    }
+    #[doc = "128 Hz."]
+    #[inline]
+    pub fn _111(self) -> &'a mut W {
+        self.variant(TSICW::_111)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 7;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Time Invalid Interrupt Enable"]
+    #[inline]
+    pub fn tiie(&self) -> TIIER {
+        TIIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Time Overflow Interrupt Enable"]
+    #[inline]
+    pub fn toie(&self) -> TOIER {
+        TOIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Time Alarm Interrupt Enable"]
+    #[inline]
+    pub fn taie(&self) -> TAIER {
+        TAIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - Time Seconds Interrupt Enable"]
+    #[inline]
+    pub fn tsie(&self) -> TSIER {
+        TSIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 16:18 - Timer Seconds Interrupt Configuration"]
+    #[inline]
+    pub fn tsic(&self) -> TSICR {
+        TSICR::_from({
+            const MASK: u8 = 7;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 7 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Time Invalid Interrupt Enable"]
+    #[inline]
+    pub fn tiie(&mut self) -> _TIIEW {
+        _TIIEW { w: self }
+    }
+    #[doc = "Bit 1 - Time Overflow Interrupt Enable"]
+    #[inline]
+    pub fn toie(&mut self) -> _TOIEW {
+        _TOIEW { w: self }
+    }
+    #[doc = "Bit 2 - Time Alarm Interrupt Enable"]
+    #[inline]
+    pub fn taie(&mut self) -> _TAIEW {
+        _TAIEW { w: self }
+    }
+    #[doc = "Bit 4 - Time Seconds Interrupt Enable"]
+    #[inline]
+    pub fn tsie(&mut self) -> _TSIEW {
+        _TSIEW { w: self }
+    }
+    #[doc = "Bits 16:18 - Timer Seconds Interrupt Configuration"]
+    #[inline]
+    pub fn tsic(&mut self) -> _TSICW {
+        _TSICW { w: self }
+    }
+}

src/rtc/lr/mod.rs

@@ -0,0 +1,538 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::LR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TCL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TCLR {
+    #[doc = "Time Compensation Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Time Compensation Register is not locked and writes complete as normal."]
+    _1,
+}
+impl TCLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TCLR::_0 => false,
+            TCLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TCLR {
+        match value {
+            false => TCLR::_0,
+            true => TCLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TCLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TCLR::_1
+    }
+}
+#[doc = "Possible values of the field `CRL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CRLR {
+    #[doc = "Control Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Control Register is not locked and writes complete as normal."]
+    _1,
+}
+impl CRLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CRLR::_0 => false,
+            CRLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CRLR {
+        match value {
+            false => CRLR::_0,
+            true => CRLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CRLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CRLR::_1
+    }
+}
+#[doc = "Possible values of the field `SRL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum SRLR {
+    #[doc = "Status Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Status Register is not locked and writes complete as normal."]
+    _1,
+}
+impl SRLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            SRLR::_0 => false,
+            SRLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> SRLR {
+        match value {
+            false => SRLR::_0,
+            true => SRLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == SRLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == SRLR::_1
+    }
+}
+#[doc = "Possible values of the field `LRL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum LRLR {
+    #[doc = "Lock Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Lock Register is not locked and writes complete as normal."]
+    _1,
+}
+impl LRLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            LRLR::_0 => false,
+            LRLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> LRLR {
+        match value {
+            false => LRLR::_0,
+            true => LRLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == LRLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == LRLR::_1
+    }
+}
+#[doc = "Values that can be written to the field `TCL`"]
+pub enum TCLW {
+    #[doc = "Time Compensation Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Time Compensation Register is not locked and writes complete as normal."]
+    _1,
+}
+impl TCLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TCLW::_0 => false,
+            TCLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TCLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TCLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TCLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Time Compensation Register is locked and writes are ignored."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TCLW::_0)
+    }
+    #[doc = "Time Compensation Register is not locked and writes complete as normal."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TCLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CRL`"]
+pub enum CRLW {
+    #[doc = "Control Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Control Register is not locked and writes complete as normal."]
+    _1,
+}
+impl CRLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CRLW::_0 => false,
+            CRLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CRLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CRLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CRLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Control Register is locked and writes are ignored."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CRLW::_0)
+    }
+    #[doc = "Control Register is not locked and writes complete as normal."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CRLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `SRL`"]
+pub enum SRLW {
+    #[doc = "Status Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Status Register is not locked and writes complete as normal."]
+    _1,
+}
+impl SRLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            SRLW::_0 => false,
+            SRLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _SRLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _SRLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: SRLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Status Register is locked and writes are ignored."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(SRLW::_0)
+    }
+    #[doc = "Status Register is not locked and writes complete as normal."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(SRLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `LRL`"]
+pub enum LRLW {
+    #[doc = "Lock Register is locked and writes are ignored."]
+    _0,
+    #[doc = "Lock Register is not locked and writes complete as normal."]
+    _1,
+}
+impl LRLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            LRLW::_0 => false,
+            LRLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LRLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LRLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: LRLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Lock Register is locked and writes are ignored."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(LRLW::_0)
+    }
+    #[doc = "Lock Register is not locked and writes complete as normal."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(LRLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 3 - Time Compensation Lock"]
+    #[inline]
+    pub fn tcl(&self) -> TCLR {
+        TCLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - Control Register Lock"]
+    #[inline]
+    pub fn crl(&self) -> CRLR {
+        CRLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - Status Register Lock"]
+    #[inline]
+    pub fn srl(&self) -> SRLR {
+        SRLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - Lock Register Lock"]
+    #[inline]
+    pub fn lrl(&self) -> LRLR {
+        LRLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 255 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 3 - Time Compensation Lock"]
+    #[inline]
+    pub fn tcl(&mut self) -> _TCLW {
+        _TCLW { w: self }
+    }
+    #[doc = "Bit 4 - Control Register Lock"]
+    #[inline]
+    pub fn crl(&mut self) -> _CRLW {
+        _CRLW { w: self }
+    }
+    #[doc = "Bit 5 - Status Register Lock"]
+    #[inline]
+    pub fn srl(&mut self) -> _SRLW {
+        _SRLW { w: self }
+    }
+    #[doc = "Bit 6 - Lock Register Lock"]
+    #[inline]
+    pub fn lrl(&mut self) -> _LRLW {
+        _LRLW { w: self }
+    }
+}

src/rtc/mod.rs

@@ -0,0 +1,69 @@
+use vcell::VolatileCell;
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - RTC Time Seconds Register"]
+    pub tsr: TSR,
+    #[doc = "0x04 - RTC Time Prescaler Register"]
+    pub tpr: TPR,
+    #[doc = "0x08 - RTC Time Alarm Register"]
+    pub tar: TAR,
+    #[doc = "0x0c - RTC Time Compensation Register"]
+    pub tcr: TCR,
+    #[doc = "0x10 - RTC Control Register"]
+    pub cr: CR,
+    #[doc = "0x14 - RTC Status Register"]
+    pub sr: SR,
+    #[doc = "0x18 - RTC Lock Register"]
+    pub lr: LR,
+    #[doc = "0x1c - RTC Interrupt Enable Register"]
+    pub ier: IER,
+}
+#[doc = "RTC Time Seconds Register"]
+pub struct TSR {
+    register: VolatileCell<u32>,
+}
+#[doc = "RTC Time Seconds Register"]
+pub mod tsr;
+#[doc = "RTC Time Prescaler Register"]
+pub struct TPR {
+    register: VolatileCell<u32>,
+}
+#[doc = "RTC Time Prescaler Register"]
+pub mod tpr;
+#[doc = "RTC Time Alarm Register"]
+pub struct TAR {
+    register: VolatileCell<u32>,
+}
+#[doc = "RTC Time Alarm Register"]
+pub mod tar;
+#[doc = "RTC Time Compensation Register"]
+pub struct TCR {
+    register: VolatileCell<u32>,
+}
+#[doc = "RTC Time Compensation Register"]
+pub mod tcr;
+#[doc = "RTC Control Register"]
+pub struct CR {
+    register: VolatileCell<u32>,
+}
+#[doc = "RTC Control Register"]
+pub mod cr;
+#[doc = "RTC Status Register"]
+pub struct SR {
+    register: VolatileCell<u32>,
+}
+#[doc = "RTC Status Register"]
+pub mod sr;
+#[doc = "RTC Lock Register"]
+pub struct LR {
+    register: VolatileCell<u32>,
+}
+#[doc = "RTC Lock Register"]
+pub mod lr;
+#[doc = "RTC Interrupt Enable Register"]
+pub struct IER {
+    register: VolatileCell<u32>,
+}
+#[doc = "RTC Interrupt Enable Register"]
+pub mod ier;

src/rtc/sr/mod.rs

@@ -0,0 +1,349 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::SR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TIF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TIFR {
+    #[doc = "Time is valid."]
+    _0,
+    #[doc = "Time is invalid and time counter is read as zero."]
+    _1,
+}
+impl TIFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TIFR::_0 => false,
+            TIFR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TIFR {
+        match value {
+            false => TIFR::_0,
+            true => TIFR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TIFR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TIFR::_1
+    }
+}
+#[doc = "Possible values of the field `TOF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TOFR {
+    #[doc = "Time overflow has not occurred."]
+    _0,
+    #[doc = "Time overflow has occurred and time counter is read as zero."]
+    _1,
+}
+impl TOFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TOFR::_0 => false,
+            TOFR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TOFR {
+        match value {
+            false => TOFR::_0,
+            true => TOFR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TOFR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TOFR::_1
+    }
+}
+#[doc = "Possible values of the field `TAF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TAFR {
+    #[doc = "Time alarm has not occurred."]
+    _0,
+    #[doc = "Time alarm has occurred."]
+    _1,
+}
+impl TAFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TAFR::_0 => false,
+            TAFR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TAFR {
+        match value {
+            false => TAFR::_0,
+            true => TAFR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TAFR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TAFR::_1
+    }
+}
+#[doc = "Possible values of the field `TCE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TCER {
+    #[doc = "Time counter is disabled."]
+    _0,
+    #[doc = "Time counter is enabled."]
+    _1,
+}
+impl TCER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TCER::_0 => false,
+            TCER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TCER {
+        match value {
+            false => TCER::_0,
+            true => TCER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TCER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TCER::_1
+    }
+}
+#[doc = "Values that can be written to the field `TCE`"]
+pub enum TCEW {
+    #[doc = "Time counter is disabled."]
+    _0,
+    #[doc = "Time counter is enabled."]
+    _1,
+}
+impl TCEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TCEW::_0 => false,
+            TCEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TCEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TCEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TCEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Time counter is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TCEW::_0)
+    }
+    #[doc = "Time counter is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TCEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Time Invalid Flag"]
+    #[inline]
+    pub fn tif(&self) -> TIFR {
+        TIFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Time Overflow Flag"]
+    #[inline]
+    pub fn tof(&self) -> TOFR {
+        TOFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Time Alarm Flag"]
+    #[inline]
+    pub fn taf(&self) -> TAFR {
+        TAFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - Time Counter Enable"]
+    #[inline]
+    pub fn tce(&self) -> TCER {
+        TCER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 1 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 4 - Time Counter Enable"]
+    #[inline]
+    pub fn tce(&mut self) -> _TCEW {
+        _TCEW { w: self }
+    }
+}

src/rtc/tar/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TAR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TARR {
+    bits: u32,
+}
+impl TARR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TARW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TARW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Time Alarm Register"]
+    #[inline]
+    pub fn tar(&self) -> TARR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        TARR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Time Alarm Register"]
+    #[inline]
+    pub fn tar(&mut self) -> _TARW {
+        _TARW { w: self }
+    }
+}

src/rtc/tcr/mod.rs

@@ -0,0 +1,333 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TCR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `TCR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TCRR {
+    #[doc = "Time Prescaler Register overflows every 32896 clock cycles."]
+    _10000000,
+    #[doc = "Time Prescaler Register overflows every 32895 clock cycles."]
+    _10000001,
+    #[doc = "Time Prescaler Register overflows every 32769 clock cycles."]
+    _11111111,
+    #[doc = "Time Prescaler Register overflows every 32768 clock cycles."]
+    _00000000,
+    #[doc = "Time Prescaler Register overflows every 32767 clock cycles."]
+    _00000001,
+    #[doc = "Time Prescaler Register overflows every 32642 clock cycles."]
+    _01111110,
+    #[doc = "Time Prescaler Register overflows every 32641 clock cycles."]
+    _01111111,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl TCRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            TCRR::_10000000 => 128,
+            TCRR::_10000001 => 129,
+            TCRR::_11111111 => 255,
+            TCRR::_00000000 => 0,
+            TCRR::_00000001 => 1,
+            TCRR::_01111110 => 126,
+            TCRR::_01111111 => 127,
+            TCRR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> TCRR {
+        match value {
+            128 => TCRR::_10000000,
+            129 => TCRR::_10000001,
+            255 => TCRR::_11111111,
+            0 => TCRR::_00000000,
+            1 => TCRR::_00000001,
+            126 => TCRR::_01111110,
+            127 => TCRR::_01111111,
+            i => TCRR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_10000000`"]
+    #[inline]
+    pub fn is_10000000(&self) -> bool {
+        *self == TCRR::_10000000
+    }
+    #[doc = "Checks if the value of the field is `_10000001`"]
+    #[inline]
+    pub fn is_10000001(&self) -> bool {
+        *self == TCRR::_10000001
+    }
+    #[doc = "Checks if the value of the field is `_11111111`"]
+    #[inline]
+    pub fn is_11111111(&self) -> bool {
+        *self == TCRR::_11111111
+    }
+    #[doc = "Checks if the value of the field is `_00000000`"]
+    #[inline]
+    pub fn is_00000000(&self) -> bool {
+        *self == TCRR::_00000000
+    }
+    #[doc = "Checks if the value of the field is `_00000001`"]
+    #[inline]
+    pub fn is_00000001(&self) -> bool {
+        *self == TCRR::_00000001
+    }
+    #[doc = "Checks if the value of the field is `_01111110`"]
+    #[inline]
+    pub fn is_01111110(&self) -> bool {
+        *self == TCRR::_01111110
+    }
+    #[doc = "Checks if the value of the field is `_01111111`"]
+    #[inline]
+    pub fn is_01111111(&self) -> bool {
+        *self == TCRR::_01111111
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CIRR {
+    bits: u8,
+}
+impl CIRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TCVR {
+    bits: u8,
+}
+impl TCVR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CICR {
+    bits: u8,
+}
+impl CICR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Values that can be written to the field `TCR`"]
+pub enum TCRW {
+    #[doc = "Time Prescaler Register overflows every 32896 clock cycles."]
+    _10000000,
+    #[doc = "Time Prescaler Register overflows every 32895 clock cycles."]
+    _10000001,
+    #[doc = "Time Prescaler Register overflows every 32769 clock cycles."]
+    _11111111,
+    #[doc = "Time Prescaler Register overflows every 32768 clock cycles."]
+    _00000000,
+    #[doc = "Time Prescaler Register overflows every 32767 clock cycles."]
+    _00000001,
+    #[doc = "Time Prescaler Register overflows every 32642 clock cycles."]
+    _01111110,
+    #[doc = "Time Prescaler Register overflows every 32641 clock cycles."]
+    _01111111,
+}
+impl TCRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            TCRW::_10000000 => 128,
+            TCRW::_10000001 => 129,
+            TCRW::_11111111 => 255,
+            TCRW::_00000000 => 0,
+            TCRW::_00000001 => 1,
+            TCRW::_01111110 => 126,
+            TCRW::_01111111 => 127,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TCRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TCRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TCRW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Time Prescaler Register overflows every 32896 clock cycles."]
+    #[inline]
+    pub fn _10000000(self) -> &'a mut W {
+        self.variant(TCRW::_10000000)
+    }
+    #[doc = "Time Prescaler Register overflows every 32895 clock cycles."]
+    #[inline]
+    pub fn _10000001(self) -> &'a mut W {
+        self.variant(TCRW::_10000001)
+    }
+    #[doc = "Time Prescaler Register overflows every 32769 clock cycles."]
+    #[inline]
+    pub fn _11111111(self) -> &'a mut W {
+        self.variant(TCRW::_11111111)
+    }
+    #[doc = "Time Prescaler Register overflows every 32768 clock cycles."]
+    #[inline]
+    pub fn _00000000(self) -> &'a mut W {
+        self.variant(TCRW::_00000000)
+    }
+    #[doc = "Time Prescaler Register overflows every 32767 clock cycles."]
+    #[inline]
+    pub fn _00000001(self) -> &'a mut W {
+        self.variant(TCRW::_00000001)
+    }
+    #[doc = "Time Prescaler Register overflows every 32642 clock cycles."]
+    #[inline]
+    pub fn _01111110(self) -> &'a mut W {
+        self.variant(TCRW::_01111110)
+    }
+    #[doc = "Time Prescaler Register overflows every 32641 clock cycles."]
+    #[inline]
+    pub fn _01111111(self) -> &'a mut W {
+        self.variant(TCRW::_01111111)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CIRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CIRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 255;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:7 - Time Compensation Register"]
+    #[inline]
+    pub fn tcr(&self) -> TCRR {
+        TCRR::_from({
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 8:15 - Compensation Interval Register"]
+    #[inline]
+    pub fn cir(&self) -> CIRR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CIRR { bits }
+    }
+    #[doc = "Bits 16:23 - Time Compensation Value"]
+    #[inline]
+    pub fn tcv(&self) -> TCVR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        TCVR { bits }
+    }
+    #[doc = "Bits 24:31 - Compensation Interval Counter"]
+    #[inline]
+    pub fn cic(&self) -> CICR {
+        let bits = {
+            const MASK: u8 = 255;
+            const OFFSET: u8 = 24;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CICR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:7 - Time Compensation Register"]
+    #[inline]
+    pub fn tcr(&mut self) -> _TCRW {
+        _TCRW { w: self }
+    }
+    #[doc = "Bits 8:15 - Compensation Interval Register"]
+    #[inline]
+    pub fn cir(&mut self) -> _CIRW {
+        _CIRW { w: self }
+    }
+}

src/rtc/tpr/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TPR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TPRR {
+    bits: u16,
+}
+impl TPRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TPRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TPRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Time Prescaler Register"]
+    #[inline]
+    pub fn tpr(&self) -> TPRR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        TPRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Time Prescaler Register"]
+    #[inline]
+    pub fn tpr(&mut self) -> _TPRW {
+        _TPRW { w: self }
+    }
+}

src/rtc/tsr/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::TSR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct TSRR {
+    bits: u32,
+}
+impl TSRR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TSRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TSRW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u32) -> &'a mut W {
+        const MASK: u32 = 4294967295;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:31 - Time Seconds Register"]
+    #[inline]
+    pub fn tsr(&self) -> TSRR {
+        let bits = {
+            const MASK: u32 = 4294967295;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u32
+        };
+        TSRR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:31 - Time Seconds Register"]
+    #[inline]
+    pub fn tsr(&mut self) -> _TSRW {
+        _TSRW { w: self }
+    }
+}