Same as last commit just run through the form tool (splits up large lib.rs files)

src/ftm1/c0sc/mod.rs

@@ -0,0 +1,942 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C0SC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `DMA`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAR {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DMAR::_0 => false,
+            DMAR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DMAR {
+        match value {
+            false => DMAR::_0,
+            true => DMAR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == DMAR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == DMAR::_1
+    }
+}
+#[doc = "Possible values of the field `ICRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ICRSTR {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ICRSTR::_0 => false,
+            ICRSTR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ICRSTR {
+        match value {
+            false => ICRSTR::_0,
+            true => ICRSTR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ICRSTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ICRSTR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSAR {
+    bits: bool,
+}
+impl ELSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSBR {
+    bits: bool,
+}
+impl ELSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSAR {
+    bits: bool,
+}
+impl MSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSBR {
+    bits: bool,
+}
+impl MSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CHIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHIER {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHIER::_0 => false,
+            CHIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHIER {
+        match value {
+            false => CHIER::_0,
+            true => CHIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHIER::_1
+    }
+}
+#[doc = "Possible values of the field `CHF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHFR {
+    #[doc = "No channel (n) event has occurred."]
+    _0,
+    #[doc = "A channel (n) event has occurred."]
+    _1,
+}
+impl CHFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHFR::_0 => false,
+            CHFR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHFR {
+        match value {
+            false => CHFR::_0,
+            true => CHFR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHFR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHFR::_1
+    }
+}
+#[doc = "Possible values of the field `TRIGMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRIGMODER {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRIGMODER::_0 => false,
+            TRIGMODER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRIGMODER {
+        match value {
+            false => TRIGMODER::_0,
+            true => TRIGMODER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRIGMODER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRIGMODER::_1
+    }
+}
+#[doc = "Possible values of the field `CHIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHISR {
+    #[doc = "The channel (n) input is zero."]
+    _0,
+    #[doc = "The channel (n) input is one."]
+    _1,
+}
+impl CHISR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHISR::_0 => false,
+            CHISR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHISR {
+        match value {
+            false => CHISR::_0,
+            true => CHISR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHISR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHISR::_1
+    }
+}
+#[doc = "Possible values of the field `CHOV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHOVR {
+    #[doc = "The channel (n) output is zero."]
+    _0,
+    #[doc = "The channel (n) output is one."]
+    _1,
+}
+impl CHOVR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHOVR::_0 => false,
+            CHOVR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHOVR {
+        match value {
+            false => CHOVR::_0,
+            true => CHOVR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHOVR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHOVR::_1
+    }
+}
+#[doc = "Values that can be written to the field `DMA`"]
+pub enum DMAW {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DMAW::_0 => false,
+            DMAW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DMAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DMAW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DMAW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable DMA transfers."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(DMAW::_0)
+    }
+    #[doc = "Enable DMA transfers."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(DMAW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ICRST`"]
+pub enum ICRSTW {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ICRSTW::_0 => false,
+            ICRSTW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ICRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ICRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ICRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ICRSTW::_0)
+    }
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ICRSTW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CHIE`"]
+pub enum CHIEW {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CHIEW::_0 => false,
+            CHIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CHIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CHIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CHIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CHIEW::_0)
+    }
+    #[doc = "Enable channel (n) interrupt."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CHIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRIGMODE`"]
+pub enum TRIGMODEW {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRIGMODEW::_0 => false,
+            TRIGMODEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRIGMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRIGMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRIGMODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_0)
+    }
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&self) -> DMAR {
+        DMAR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&self) -> ICRSTR {
+        ICRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&self) -> ELSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSAR { bits }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&self) -> ELSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSBR { bits }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&self) -> MSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSAR { bits }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&self) -> MSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSBR { bits }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&self) -> CHIER {
+        CHIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Channel (n) Flag"]
+    #[inline]
+    pub fn chf(&self) -> CHFR {
+        CHFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&self) -> TRIGMODER {
+        TRIGMODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Channel (n) Input State"]
+    #[inline]
+    pub fn chis(&self) -> CHISR {
+        CHISR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Channel (n) Output Value"]
+    #[inline]
+    pub fn chov(&self) -> CHOVR {
+        CHOVR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&mut self) -> _DMAW {
+        _DMAW { w: self }
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&mut self) -> _ICRSTW {
+        _ICRSTW { w: self }
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&mut self) -> _ELSAW {
+        _ELSAW { w: self }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&mut self) -> _ELSBW {
+        _ELSBW { w: self }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&mut self) -> _MSAW {
+        _MSAW { w: self }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&mut self) -> _MSBW {
+        _MSBW { w: self }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&mut self) -> _CHIEW {
+        _CHIEW { w: self }
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&mut self) -> _TRIGMODEW {
+        _TRIGMODEW { w: self }
+    }
+}

src/ftm1/c0v/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C0V {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VALR {
+    bits: u16,
+}
+impl VALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&self) -> VALR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        VALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&mut self) -> _VALW {
+        _VALW { w: self }
+    }
+}

src/ftm1/c1sc/mod.rs

@@ -0,0 +1,942 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C1SC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `DMA`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAR {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DMAR::_0 => false,
+            DMAR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DMAR {
+        match value {
+            false => DMAR::_0,
+            true => DMAR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == DMAR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == DMAR::_1
+    }
+}
+#[doc = "Possible values of the field `ICRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ICRSTR {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ICRSTR::_0 => false,
+            ICRSTR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ICRSTR {
+        match value {
+            false => ICRSTR::_0,
+            true => ICRSTR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ICRSTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ICRSTR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSAR {
+    bits: bool,
+}
+impl ELSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSBR {
+    bits: bool,
+}
+impl ELSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSAR {
+    bits: bool,
+}
+impl MSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSBR {
+    bits: bool,
+}
+impl MSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CHIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHIER {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHIER::_0 => false,
+            CHIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHIER {
+        match value {
+            false => CHIER::_0,
+            true => CHIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHIER::_1
+    }
+}
+#[doc = "Possible values of the field `CHF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHFR {
+    #[doc = "No channel (n) event has occurred."]
+    _0,
+    #[doc = "A channel (n) event has occurred."]
+    _1,
+}
+impl CHFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHFR::_0 => false,
+            CHFR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHFR {
+        match value {
+            false => CHFR::_0,
+            true => CHFR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHFR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHFR::_1
+    }
+}
+#[doc = "Possible values of the field `TRIGMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRIGMODER {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRIGMODER::_0 => false,
+            TRIGMODER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRIGMODER {
+        match value {
+            false => TRIGMODER::_0,
+            true => TRIGMODER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRIGMODER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRIGMODER::_1
+    }
+}
+#[doc = "Possible values of the field `CHIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHISR {
+    #[doc = "The channel (n) input is zero."]
+    _0,
+    #[doc = "The channel (n) input is one."]
+    _1,
+}
+impl CHISR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHISR::_0 => false,
+            CHISR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHISR {
+        match value {
+            false => CHISR::_0,
+            true => CHISR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHISR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHISR::_1
+    }
+}
+#[doc = "Possible values of the field `CHOV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHOVR {
+    #[doc = "The channel (n) output is zero."]
+    _0,
+    #[doc = "The channel (n) output is one."]
+    _1,
+}
+impl CHOVR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHOVR::_0 => false,
+            CHOVR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHOVR {
+        match value {
+            false => CHOVR::_0,
+            true => CHOVR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHOVR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHOVR::_1
+    }
+}
+#[doc = "Values that can be written to the field `DMA`"]
+pub enum DMAW {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DMAW::_0 => false,
+            DMAW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DMAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DMAW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DMAW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable DMA transfers."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(DMAW::_0)
+    }
+    #[doc = "Enable DMA transfers."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(DMAW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ICRST`"]
+pub enum ICRSTW {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ICRSTW::_0 => false,
+            ICRSTW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ICRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ICRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ICRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ICRSTW::_0)
+    }
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ICRSTW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CHIE`"]
+pub enum CHIEW {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CHIEW::_0 => false,
+            CHIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CHIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CHIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CHIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CHIEW::_0)
+    }
+    #[doc = "Enable channel (n) interrupt."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CHIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRIGMODE`"]
+pub enum TRIGMODEW {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRIGMODEW::_0 => false,
+            TRIGMODEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRIGMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRIGMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRIGMODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_0)
+    }
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&self) -> DMAR {
+        DMAR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&self) -> ICRSTR {
+        ICRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&self) -> ELSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSAR { bits }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&self) -> ELSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSBR { bits }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&self) -> MSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSAR { bits }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&self) -> MSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSBR { bits }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&self) -> CHIER {
+        CHIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Channel (n) Flag"]
+    #[inline]
+    pub fn chf(&self) -> CHFR {
+        CHFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&self) -> TRIGMODER {
+        TRIGMODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Channel (n) Input State"]
+    #[inline]
+    pub fn chis(&self) -> CHISR {
+        CHISR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Channel (n) Output Value"]
+    #[inline]
+    pub fn chov(&self) -> CHOVR {
+        CHOVR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&mut self) -> _DMAW {
+        _DMAW { w: self }
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&mut self) -> _ICRSTW {
+        _ICRSTW { w: self }
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&mut self) -> _ELSAW {
+        _ELSAW { w: self }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&mut self) -> _ELSBW {
+        _ELSBW { w: self }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&mut self) -> _MSAW {
+        _MSAW { w: self }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&mut self) -> _MSBW {
+        _MSBW { w: self }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&mut self) -> _CHIEW {
+        _CHIEW { w: self }
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&mut self) -> _TRIGMODEW {
+        _TRIGMODEW { w: self }
+    }
+}

src/ftm1/c1v/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C1V {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VALR {
+    bits: u16,
+}
+impl VALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&self) -> VALR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        VALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&mut self) -> _VALW {
+        _VALW { w: self }
+    }
+}

src/ftm1/c2sc/mod.rs

@@ -0,0 +1,942 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C2SC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `DMA`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAR {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DMAR::_0 => false,
+            DMAR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DMAR {
+        match value {
+            false => DMAR::_0,
+            true => DMAR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == DMAR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == DMAR::_1
+    }
+}
+#[doc = "Possible values of the field `ICRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ICRSTR {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ICRSTR::_0 => false,
+            ICRSTR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ICRSTR {
+        match value {
+            false => ICRSTR::_0,
+            true => ICRSTR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ICRSTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ICRSTR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSAR {
+    bits: bool,
+}
+impl ELSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSBR {
+    bits: bool,
+}
+impl ELSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSAR {
+    bits: bool,
+}
+impl MSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSBR {
+    bits: bool,
+}
+impl MSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CHIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHIER {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHIER::_0 => false,
+            CHIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHIER {
+        match value {
+            false => CHIER::_0,
+            true => CHIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHIER::_1
+    }
+}
+#[doc = "Possible values of the field `CHF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHFR {
+    #[doc = "No channel (n) event has occurred."]
+    _0,
+    #[doc = "A channel (n) event has occurred."]
+    _1,
+}
+impl CHFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHFR::_0 => false,
+            CHFR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHFR {
+        match value {
+            false => CHFR::_0,
+            true => CHFR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHFR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHFR::_1
+    }
+}
+#[doc = "Possible values of the field `TRIGMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRIGMODER {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRIGMODER::_0 => false,
+            TRIGMODER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRIGMODER {
+        match value {
+            false => TRIGMODER::_0,
+            true => TRIGMODER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRIGMODER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRIGMODER::_1
+    }
+}
+#[doc = "Possible values of the field `CHIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHISR {
+    #[doc = "The channel (n) input is zero."]
+    _0,
+    #[doc = "The channel (n) input is one."]
+    _1,
+}
+impl CHISR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHISR::_0 => false,
+            CHISR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHISR {
+        match value {
+            false => CHISR::_0,
+            true => CHISR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHISR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHISR::_1
+    }
+}
+#[doc = "Possible values of the field `CHOV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHOVR {
+    #[doc = "The channel (n) output is zero."]
+    _0,
+    #[doc = "The channel (n) output is one."]
+    _1,
+}
+impl CHOVR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHOVR::_0 => false,
+            CHOVR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHOVR {
+        match value {
+            false => CHOVR::_0,
+            true => CHOVR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHOVR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHOVR::_1
+    }
+}
+#[doc = "Values that can be written to the field `DMA`"]
+pub enum DMAW {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DMAW::_0 => false,
+            DMAW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DMAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DMAW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DMAW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable DMA transfers."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(DMAW::_0)
+    }
+    #[doc = "Enable DMA transfers."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(DMAW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ICRST`"]
+pub enum ICRSTW {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ICRSTW::_0 => false,
+            ICRSTW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ICRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ICRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ICRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ICRSTW::_0)
+    }
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ICRSTW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CHIE`"]
+pub enum CHIEW {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CHIEW::_0 => false,
+            CHIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CHIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CHIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CHIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CHIEW::_0)
+    }
+    #[doc = "Enable channel (n) interrupt."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CHIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRIGMODE`"]
+pub enum TRIGMODEW {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRIGMODEW::_0 => false,
+            TRIGMODEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRIGMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRIGMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRIGMODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_0)
+    }
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&self) -> DMAR {
+        DMAR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&self) -> ICRSTR {
+        ICRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&self) -> ELSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSAR { bits }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&self) -> ELSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSBR { bits }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&self) -> MSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSAR { bits }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&self) -> MSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSBR { bits }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&self) -> CHIER {
+        CHIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Channel (n) Flag"]
+    #[inline]
+    pub fn chf(&self) -> CHFR {
+        CHFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&self) -> TRIGMODER {
+        TRIGMODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Channel (n) Input State"]
+    #[inline]
+    pub fn chis(&self) -> CHISR {
+        CHISR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Channel (n) Output Value"]
+    #[inline]
+    pub fn chov(&self) -> CHOVR {
+        CHOVR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&mut self) -> _DMAW {
+        _DMAW { w: self }
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&mut self) -> _ICRSTW {
+        _ICRSTW { w: self }
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&mut self) -> _ELSAW {
+        _ELSAW { w: self }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&mut self) -> _ELSBW {
+        _ELSBW { w: self }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&mut self) -> _MSAW {
+        _MSAW { w: self }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&mut self) -> _MSBW {
+        _MSBW { w: self }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&mut self) -> _CHIEW {
+        _CHIEW { w: self }
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&mut self) -> _TRIGMODEW {
+        _TRIGMODEW { w: self }
+    }
+}

src/ftm1/c2v/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C2V {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VALR {
+    bits: u16,
+}
+impl VALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&self) -> VALR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        VALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&mut self) -> _VALW {
+        _VALW { w: self }
+    }
+}

src/ftm1/c3sc/mod.rs

@@ -0,0 +1,942 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C3SC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `DMA`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAR {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DMAR::_0 => false,
+            DMAR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DMAR {
+        match value {
+            false => DMAR::_0,
+            true => DMAR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == DMAR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == DMAR::_1
+    }
+}
+#[doc = "Possible values of the field `ICRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ICRSTR {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ICRSTR::_0 => false,
+            ICRSTR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ICRSTR {
+        match value {
+            false => ICRSTR::_0,
+            true => ICRSTR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ICRSTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ICRSTR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSAR {
+    bits: bool,
+}
+impl ELSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSBR {
+    bits: bool,
+}
+impl ELSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSAR {
+    bits: bool,
+}
+impl MSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSBR {
+    bits: bool,
+}
+impl MSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CHIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHIER {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHIER::_0 => false,
+            CHIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHIER {
+        match value {
+            false => CHIER::_0,
+            true => CHIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHIER::_1
+    }
+}
+#[doc = "Possible values of the field `CHF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHFR {
+    #[doc = "No channel (n) event has occurred."]
+    _0,
+    #[doc = "A channel (n) event has occurred."]
+    _1,
+}
+impl CHFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHFR::_0 => false,
+            CHFR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHFR {
+        match value {
+            false => CHFR::_0,
+            true => CHFR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHFR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHFR::_1
+    }
+}
+#[doc = "Possible values of the field `TRIGMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRIGMODER {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRIGMODER::_0 => false,
+            TRIGMODER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRIGMODER {
+        match value {
+            false => TRIGMODER::_0,
+            true => TRIGMODER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRIGMODER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRIGMODER::_1
+    }
+}
+#[doc = "Possible values of the field `CHIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHISR {
+    #[doc = "The channel (n) input is zero."]
+    _0,
+    #[doc = "The channel (n) input is one."]
+    _1,
+}
+impl CHISR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHISR::_0 => false,
+            CHISR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHISR {
+        match value {
+            false => CHISR::_0,
+            true => CHISR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHISR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHISR::_1
+    }
+}
+#[doc = "Possible values of the field `CHOV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHOVR {
+    #[doc = "The channel (n) output is zero."]
+    _0,
+    #[doc = "The channel (n) output is one."]
+    _1,
+}
+impl CHOVR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHOVR::_0 => false,
+            CHOVR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHOVR {
+        match value {
+            false => CHOVR::_0,
+            true => CHOVR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHOVR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHOVR::_1
+    }
+}
+#[doc = "Values that can be written to the field `DMA`"]
+pub enum DMAW {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DMAW::_0 => false,
+            DMAW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DMAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DMAW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DMAW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable DMA transfers."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(DMAW::_0)
+    }
+    #[doc = "Enable DMA transfers."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(DMAW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ICRST`"]
+pub enum ICRSTW {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ICRSTW::_0 => false,
+            ICRSTW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ICRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ICRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ICRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ICRSTW::_0)
+    }
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ICRSTW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CHIE`"]
+pub enum CHIEW {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CHIEW::_0 => false,
+            CHIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CHIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CHIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CHIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CHIEW::_0)
+    }
+    #[doc = "Enable channel (n) interrupt."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CHIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRIGMODE`"]
+pub enum TRIGMODEW {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRIGMODEW::_0 => false,
+            TRIGMODEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRIGMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRIGMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRIGMODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_0)
+    }
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&self) -> DMAR {
+        DMAR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&self) -> ICRSTR {
+        ICRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&self) -> ELSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSAR { bits }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&self) -> ELSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSBR { bits }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&self) -> MSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSAR { bits }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&self) -> MSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSBR { bits }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&self) -> CHIER {
+        CHIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Channel (n) Flag"]
+    #[inline]
+    pub fn chf(&self) -> CHFR {
+        CHFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&self) -> TRIGMODER {
+        TRIGMODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Channel (n) Input State"]
+    #[inline]
+    pub fn chis(&self) -> CHISR {
+        CHISR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Channel (n) Output Value"]
+    #[inline]
+    pub fn chov(&self) -> CHOVR {
+        CHOVR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&mut self) -> _DMAW {
+        _DMAW { w: self }
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&mut self) -> _ICRSTW {
+        _ICRSTW { w: self }
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&mut self) -> _ELSAW {
+        _ELSAW { w: self }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&mut self) -> _ELSBW {
+        _ELSBW { w: self }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&mut self) -> _MSAW {
+        _MSAW { w: self }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&mut self) -> _MSBW {
+        _MSBW { w: self }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&mut self) -> _CHIEW {
+        _CHIEW { w: self }
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&mut self) -> _TRIGMODEW {
+        _TRIGMODEW { w: self }
+    }
+}

src/ftm1/c3v/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C3V {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VALR {
+    bits: u16,
+}
+impl VALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&self) -> VALR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        VALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&mut self) -> _VALW {
+        _VALW { w: self }
+    }
+}

src/ftm1/c4sc/mod.rs

@@ -0,0 +1,942 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C4SC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `DMA`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAR {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DMAR::_0 => false,
+            DMAR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DMAR {
+        match value {
+            false => DMAR::_0,
+            true => DMAR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == DMAR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == DMAR::_1
+    }
+}
+#[doc = "Possible values of the field `ICRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ICRSTR {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ICRSTR::_0 => false,
+            ICRSTR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ICRSTR {
+        match value {
+            false => ICRSTR::_0,
+            true => ICRSTR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ICRSTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ICRSTR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSAR {
+    bits: bool,
+}
+impl ELSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSBR {
+    bits: bool,
+}
+impl ELSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSAR {
+    bits: bool,
+}
+impl MSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSBR {
+    bits: bool,
+}
+impl MSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CHIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHIER {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHIER::_0 => false,
+            CHIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHIER {
+        match value {
+            false => CHIER::_0,
+            true => CHIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHIER::_1
+    }
+}
+#[doc = "Possible values of the field `CHF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHFR {
+    #[doc = "No channel (n) event has occurred."]
+    _0,
+    #[doc = "A channel (n) event has occurred."]
+    _1,
+}
+impl CHFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHFR::_0 => false,
+            CHFR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHFR {
+        match value {
+            false => CHFR::_0,
+            true => CHFR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHFR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHFR::_1
+    }
+}
+#[doc = "Possible values of the field `TRIGMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRIGMODER {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRIGMODER::_0 => false,
+            TRIGMODER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRIGMODER {
+        match value {
+            false => TRIGMODER::_0,
+            true => TRIGMODER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRIGMODER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRIGMODER::_1
+    }
+}
+#[doc = "Possible values of the field `CHIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHISR {
+    #[doc = "The channel (n) input is zero."]
+    _0,
+    #[doc = "The channel (n) input is one."]
+    _1,
+}
+impl CHISR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHISR::_0 => false,
+            CHISR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHISR {
+        match value {
+            false => CHISR::_0,
+            true => CHISR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHISR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHISR::_1
+    }
+}
+#[doc = "Possible values of the field `CHOV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHOVR {
+    #[doc = "The channel (n) output is zero."]
+    _0,
+    #[doc = "The channel (n) output is one."]
+    _1,
+}
+impl CHOVR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHOVR::_0 => false,
+            CHOVR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHOVR {
+        match value {
+            false => CHOVR::_0,
+            true => CHOVR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHOVR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHOVR::_1
+    }
+}
+#[doc = "Values that can be written to the field `DMA`"]
+pub enum DMAW {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DMAW::_0 => false,
+            DMAW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DMAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DMAW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DMAW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable DMA transfers."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(DMAW::_0)
+    }
+    #[doc = "Enable DMA transfers."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(DMAW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ICRST`"]
+pub enum ICRSTW {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ICRSTW::_0 => false,
+            ICRSTW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ICRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ICRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ICRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ICRSTW::_0)
+    }
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ICRSTW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CHIE`"]
+pub enum CHIEW {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CHIEW::_0 => false,
+            CHIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CHIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CHIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CHIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CHIEW::_0)
+    }
+    #[doc = "Enable channel (n) interrupt."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CHIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRIGMODE`"]
+pub enum TRIGMODEW {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRIGMODEW::_0 => false,
+            TRIGMODEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRIGMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRIGMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRIGMODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_0)
+    }
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&self) -> DMAR {
+        DMAR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&self) -> ICRSTR {
+        ICRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&self) -> ELSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSAR { bits }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&self) -> ELSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSBR { bits }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&self) -> MSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSAR { bits }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&self) -> MSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSBR { bits }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&self) -> CHIER {
+        CHIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Channel (n) Flag"]
+    #[inline]
+    pub fn chf(&self) -> CHFR {
+        CHFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&self) -> TRIGMODER {
+        TRIGMODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Channel (n) Input State"]
+    #[inline]
+    pub fn chis(&self) -> CHISR {
+        CHISR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Channel (n) Output Value"]
+    #[inline]
+    pub fn chov(&self) -> CHOVR {
+        CHOVR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&mut self) -> _DMAW {
+        _DMAW { w: self }
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&mut self) -> _ICRSTW {
+        _ICRSTW { w: self }
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&mut self) -> _ELSAW {
+        _ELSAW { w: self }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&mut self) -> _ELSBW {
+        _ELSBW { w: self }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&mut self) -> _MSAW {
+        _MSAW { w: self }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&mut self) -> _MSBW {
+        _MSBW { w: self }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&mut self) -> _CHIEW {
+        _CHIEW { w: self }
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&mut self) -> _TRIGMODEW {
+        _TRIGMODEW { w: self }
+    }
+}

src/ftm1/c4v/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C4V {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VALR {
+    bits: u16,
+}
+impl VALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&self) -> VALR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        VALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&mut self) -> _VALW {
+        _VALW { w: self }
+    }
+}

src/ftm1/c5sc/mod.rs

@@ -0,0 +1,942 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C5SC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `DMA`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAR {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DMAR::_0 => false,
+            DMAR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DMAR {
+        match value {
+            false => DMAR::_0,
+            true => DMAR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == DMAR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == DMAR::_1
+    }
+}
+#[doc = "Possible values of the field `ICRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ICRSTR {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ICRSTR::_0 => false,
+            ICRSTR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ICRSTR {
+        match value {
+            false => ICRSTR::_0,
+            true => ICRSTR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ICRSTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ICRSTR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSAR {
+    bits: bool,
+}
+impl ELSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSBR {
+    bits: bool,
+}
+impl ELSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSAR {
+    bits: bool,
+}
+impl MSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSBR {
+    bits: bool,
+}
+impl MSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CHIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHIER {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHIER::_0 => false,
+            CHIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHIER {
+        match value {
+            false => CHIER::_0,
+            true => CHIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHIER::_1
+    }
+}
+#[doc = "Possible values of the field `CHF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHFR {
+    #[doc = "No channel (n) event has occurred."]
+    _0,
+    #[doc = "A channel (n) event has occurred."]
+    _1,
+}
+impl CHFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHFR::_0 => false,
+            CHFR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHFR {
+        match value {
+            false => CHFR::_0,
+            true => CHFR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHFR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHFR::_1
+    }
+}
+#[doc = "Possible values of the field `TRIGMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRIGMODER {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRIGMODER::_0 => false,
+            TRIGMODER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRIGMODER {
+        match value {
+            false => TRIGMODER::_0,
+            true => TRIGMODER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRIGMODER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRIGMODER::_1
+    }
+}
+#[doc = "Possible values of the field `CHIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHISR {
+    #[doc = "The channel (n) input is zero."]
+    _0,
+    #[doc = "The channel (n) input is one."]
+    _1,
+}
+impl CHISR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHISR::_0 => false,
+            CHISR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHISR {
+        match value {
+            false => CHISR::_0,
+            true => CHISR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHISR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHISR::_1
+    }
+}
+#[doc = "Possible values of the field `CHOV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHOVR {
+    #[doc = "The channel (n) output is zero."]
+    _0,
+    #[doc = "The channel (n) output is one."]
+    _1,
+}
+impl CHOVR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHOVR::_0 => false,
+            CHOVR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHOVR {
+        match value {
+            false => CHOVR::_0,
+            true => CHOVR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHOVR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHOVR::_1
+    }
+}
+#[doc = "Values that can be written to the field `DMA`"]
+pub enum DMAW {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DMAW::_0 => false,
+            DMAW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DMAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DMAW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DMAW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable DMA transfers."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(DMAW::_0)
+    }
+    #[doc = "Enable DMA transfers."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(DMAW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ICRST`"]
+pub enum ICRSTW {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ICRSTW::_0 => false,
+            ICRSTW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ICRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ICRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ICRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ICRSTW::_0)
+    }
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ICRSTW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CHIE`"]
+pub enum CHIEW {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CHIEW::_0 => false,
+            CHIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CHIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CHIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CHIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CHIEW::_0)
+    }
+    #[doc = "Enable channel (n) interrupt."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CHIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRIGMODE`"]
+pub enum TRIGMODEW {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRIGMODEW::_0 => false,
+            TRIGMODEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRIGMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRIGMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRIGMODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_0)
+    }
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&self) -> DMAR {
+        DMAR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&self) -> ICRSTR {
+        ICRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&self) -> ELSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSAR { bits }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&self) -> ELSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSBR { bits }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&self) -> MSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSAR { bits }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&self) -> MSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSBR { bits }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&self) -> CHIER {
+        CHIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Channel (n) Flag"]
+    #[inline]
+    pub fn chf(&self) -> CHFR {
+        CHFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&self) -> TRIGMODER {
+        TRIGMODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Channel (n) Input State"]
+    #[inline]
+    pub fn chis(&self) -> CHISR {
+        CHISR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Channel (n) Output Value"]
+    #[inline]
+    pub fn chov(&self) -> CHOVR {
+        CHOVR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&mut self) -> _DMAW {
+        _DMAW { w: self }
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&mut self) -> _ICRSTW {
+        _ICRSTW { w: self }
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&mut self) -> _ELSAW {
+        _ELSAW { w: self }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&mut self) -> _ELSBW {
+        _ELSBW { w: self }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&mut self) -> _MSAW {
+        _MSAW { w: self }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&mut self) -> _MSBW {
+        _MSBW { w: self }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&mut self) -> _CHIEW {
+        _CHIEW { w: self }
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&mut self) -> _TRIGMODEW {
+        _TRIGMODEW { w: self }
+    }
+}

src/ftm1/c5v/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C5V {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VALR {
+    bits: u16,
+}
+impl VALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&self) -> VALR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        VALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&mut self) -> _VALW {
+        _VALW { w: self }
+    }
+}

src/ftm1/c6sc/mod.rs

@@ -0,0 +1,942 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C6SC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `DMA`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAR {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DMAR::_0 => false,
+            DMAR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DMAR {
+        match value {
+            false => DMAR::_0,
+            true => DMAR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == DMAR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == DMAR::_1
+    }
+}
+#[doc = "Possible values of the field `ICRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ICRSTR {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ICRSTR::_0 => false,
+            ICRSTR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ICRSTR {
+        match value {
+            false => ICRSTR::_0,
+            true => ICRSTR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ICRSTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ICRSTR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSAR {
+    bits: bool,
+}
+impl ELSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSBR {
+    bits: bool,
+}
+impl ELSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSAR {
+    bits: bool,
+}
+impl MSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSBR {
+    bits: bool,
+}
+impl MSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CHIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHIER {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHIER::_0 => false,
+            CHIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHIER {
+        match value {
+            false => CHIER::_0,
+            true => CHIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHIER::_1
+    }
+}
+#[doc = "Possible values of the field `CHF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHFR {
+    #[doc = "No channel (n) event has occurred."]
+    _0,
+    #[doc = "A channel (n) event has occurred."]
+    _1,
+}
+impl CHFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHFR::_0 => false,
+            CHFR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHFR {
+        match value {
+            false => CHFR::_0,
+            true => CHFR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHFR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHFR::_1
+    }
+}
+#[doc = "Possible values of the field `TRIGMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRIGMODER {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRIGMODER::_0 => false,
+            TRIGMODER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRIGMODER {
+        match value {
+            false => TRIGMODER::_0,
+            true => TRIGMODER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRIGMODER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRIGMODER::_1
+    }
+}
+#[doc = "Possible values of the field `CHIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHISR {
+    #[doc = "The channel (n) input is zero."]
+    _0,
+    #[doc = "The channel (n) input is one."]
+    _1,
+}
+impl CHISR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHISR::_0 => false,
+            CHISR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHISR {
+        match value {
+            false => CHISR::_0,
+            true => CHISR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHISR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHISR::_1
+    }
+}
+#[doc = "Possible values of the field `CHOV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHOVR {
+    #[doc = "The channel (n) output is zero."]
+    _0,
+    #[doc = "The channel (n) output is one."]
+    _1,
+}
+impl CHOVR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHOVR::_0 => false,
+            CHOVR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHOVR {
+        match value {
+            false => CHOVR::_0,
+            true => CHOVR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHOVR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHOVR::_1
+    }
+}
+#[doc = "Values that can be written to the field `DMA`"]
+pub enum DMAW {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DMAW::_0 => false,
+            DMAW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DMAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DMAW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DMAW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable DMA transfers."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(DMAW::_0)
+    }
+    #[doc = "Enable DMA transfers."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(DMAW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ICRST`"]
+pub enum ICRSTW {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ICRSTW::_0 => false,
+            ICRSTW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ICRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ICRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ICRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ICRSTW::_0)
+    }
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ICRSTW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CHIE`"]
+pub enum CHIEW {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CHIEW::_0 => false,
+            CHIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CHIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CHIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CHIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CHIEW::_0)
+    }
+    #[doc = "Enable channel (n) interrupt."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CHIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRIGMODE`"]
+pub enum TRIGMODEW {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRIGMODEW::_0 => false,
+            TRIGMODEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRIGMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRIGMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRIGMODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_0)
+    }
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&self) -> DMAR {
+        DMAR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&self) -> ICRSTR {
+        ICRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&self) -> ELSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSAR { bits }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&self) -> ELSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSBR { bits }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&self) -> MSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSAR { bits }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&self) -> MSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSBR { bits }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&self) -> CHIER {
+        CHIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Channel (n) Flag"]
+    #[inline]
+    pub fn chf(&self) -> CHFR {
+        CHFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&self) -> TRIGMODER {
+        TRIGMODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Channel (n) Input State"]
+    #[inline]
+    pub fn chis(&self) -> CHISR {
+        CHISR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Channel (n) Output Value"]
+    #[inline]
+    pub fn chov(&self) -> CHOVR {
+        CHOVR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&mut self) -> _DMAW {
+        _DMAW { w: self }
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&mut self) -> _ICRSTW {
+        _ICRSTW { w: self }
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&mut self) -> _ELSAW {
+        _ELSAW { w: self }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&mut self) -> _ELSBW {
+        _ELSBW { w: self }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&mut self) -> _MSAW {
+        _MSAW { w: self }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&mut self) -> _MSBW {
+        _MSBW { w: self }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&mut self) -> _CHIEW {
+        _CHIEW { w: self }
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&mut self) -> _TRIGMODEW {
+        _TRIGMODEW { w: self }
+    }
+}

src/ftm1/c6v/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C6V {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VALR {
+    bits: u16,
+}
+impl VALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&self) -> VALR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        VALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&mut self) -> _VALW {
+        _VALW { w: self }
+    }
+}

src/ftm1/c7sc/mod.rs

@@ -0,0 +1,942 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C7SC {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `DMA`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DMAR {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            DMAR::_0 => false,
+            DMAR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> DMAR {
+        match value {
+            false => DMAR::_0,
+            true => DMAR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == DMAR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == DMAR::_1
+    }
+}
+#[doc = "Possible values of the field `ICRST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ICRSTR {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ICRSTR::_0 => false,
+            ICRSTR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ICRSTR {
+        match value {
+            false => ICRSTR::_0,
+            true => ICRSTR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ICRSTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ICRSTR::_1
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSAR {
+    bits: bool,
+}
+impl ELSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct ELSBR {
+    bits: bool,
+}
+impl ELSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSAR {
+    bits: bool,
+}
+impl MSAR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MSBR {
+    bits: bool,
+}
+impl MSBR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `CHIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHIER {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHIER::_0 => false,
+            CHIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHIER {
+        match value {
+            false => CHIER::_0,
+            true => CHIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHIER::_1
+    }
+}
+#[doc = "Possible values of the field `CHF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHFR {
+    #[doc = "No channel (n) event has occurred."]
+    _0,
+    #[doc = "A channel (n) event has occurred."]
+    _1,
+}
+impl CHFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHFR::_0 => false,
+            CHFR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHFR {
+        match value {
+            false => CHFR::_0,
+            true => CHFR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHFR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHFR::_1
+    }
+}
+#[doc = "Possible values of the field `TRIGMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TRIGMODER {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TRIGMODER::_0 => false,
+            TRIGMODER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TRIGMODER {
+        match value {
+            false => TRIGMODER::_0,
+            true => TRIGMODER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TRIGMODER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TRIGMODER::_1
+    }
+}
+#[doc = "Possible values of the field `CHIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHISR {
+    #[doc = "The channel (n) input is zero."]
+    _0,
+    #[doc = "The channel (n) input is one."]
+    _1,
+}
+impl CHISR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHISR::_0 => false,
+            CHISR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHISR {
+        match value {
+            false => CHISR::_0,
+            true => CHISR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHISR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHISR::_1
+    }
+}
+#[doc = "Possible values of the field `CHOV`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CHOVR {
+    #[doc = "The channel (n) output is zero."]
+    _0,
+    #[doc = "The channel (n) output is one."]
+    _1,
+}
+impl CHOVR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CHOVR::_0 => false,
+            CHOVR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CHOVR {
+        match value {
+            false => CHOVR::_0,
+            true => CHOVR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CHOVR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CHOVR::_1
+    }
+}
+#[doc = "Values that can be written to the field `DMA`"]
+pub enum DMAW {
+    #[doc = "Disable DMA transfers."]
+    _0,
+    #[doc = "Enable DMA transfers."]
+    _1,
+}
+impl DMAW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            DMAW::_0 => false,
+            DMAW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DMAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DMAW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DMAW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable DMA transfers."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(DMAW::_0)
+    }
+    #[doc = "Enable DMA transfers."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(DMAW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ICRST`"]
+pub enum ICRSTW {
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    _0,
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    _1,
+}
+impl ICRSTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ICRSTW::_0 => false,
+            ICRSTW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ICRSTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ICRSTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ICRSTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "FTM counter is not reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ICRSTW::_0)
+    }
+    #[doc = "FTM counter is reset when the selected channel (n) input event is detected."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ICRSTW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ELSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ELSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSAW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSAW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MSBW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MSBW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CHIE`"]
+pub enum CHIEW {
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    _0,
+    #[doc = "Enable channel (n) interrupt."]
+    _1,
+}
+impl CHIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CHIEW::_0 => false,
+            CHIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CHIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CHIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CHIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Disable channel (n) interrupt. Use software polling."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CHIEW::_0)
+    }
+    #[doc = "Enable channel (n) interrupt."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CHIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `TRIGMODE`"]
+pub enum TRIGMODEW {
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    _0,
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    _1,
+}
+impl TRIGMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            TRIGMODEW::_0 => false,
+            TRIGMODEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _TRIGMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _TRIGMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: TRIGMODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Channel outputs will generate the normal PWM outputs without generating a pulse."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_0)
+    }
+    #[doc = "If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(TRIGMODEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&self) -> DMAR {
+        DMAR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&self) -> ICRSTR {
+        ICRSTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&self) -> ELSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSAR { bits }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&self) -> ELSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        ELSBR { bits }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&self) -> MSAR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSAR { bits }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&self) -> MSBR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        MSBR { bits }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&self) -> CHIER {
+        CHIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Channel (n) Flag"]
+    #[inline]
+    pub fn chf(&self) -> CHFR {
+        CHFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&self) -> TRIGMODER {
+        TRIGMODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 9 - Channel (n) Input State"]
+    #[inline]
+    pub fn chis(&self) -> CHISR {
+        CHISR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 10 - Channel (n) Output Value"]
+    #[inline]
+    pub fn chov(&self) -> CHOVR {
+        CHOVR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - DMA Enable"]
+    #[inline]
+    pub fn dma(&mut self) -> _DMAW {
+        _DMAW { w: self }
+    }
+    #[doc = "Bit 1 - FTM counter reset by the selected input capture event."]
+    #[inline]
+    pub fn icrst(&mut self) -> _ICRSTW {
+        _ICRSTW { w: self }
+    }
+    #[doc = "Bit 2 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsa(&mut self) -> _ELSAW {
+        _ELSAW { w: self }
+    }
+    #[doc = "Bit 3 - Channel (n) Edge or Level Select"]
+    #[inline]
+    pub fn elsb(&mut self) -> _ELSBW {
+        _ELSBW { w: self }
+    }
+    #[doc = "Bit 4 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msa(&mut self) -> _MSAW {
+        _MSAW { w: self }
+    }
+    #[doc = "Bit 5 - Channel (n) Mode Select"]
+    #[inline]
+    pub fn msb(&mut self) -> _MSBW {
+        _MSBW { w: self }
+    }
+    #[doc = "Bit 6 - Channel (n) Interrupt Enable"]
+    #[inline]
+    pub fn chie(&mut self) -> _CHIEW {
+        _CHIEW { w: self }
+    }
+    #[doc = "Bit 8 - Trigger mode control"]
+    #[inline]
+    pub fn trigmode(&mut self) -> _TRIGMODEW {
+        _TRIGMODEW { w: self }
+    }
+}

src/ftm1/c7v/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::C7V {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct VALR {
+    bits: u16,
+}
+impl VALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _VALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _VALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&self) -> VALR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        VALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Channel Value"]
+    #[inline]
+    pub fn val(&mut self) -> _VALW {
+        _VALW { w: self }
+    }
+}

src/ftm1/cnt/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CNT {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct COUNTR {
+    bits: u16,
+}
+impl COUNTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _COUNTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _COUNTW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Counter Value"]
+    #[inline]
+    pub fn count(&self) -> COUNTR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        COUNTR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Counter Value"]
+    #[inline]
+    pub fn count(&mut self) -> _COUNTW {
+        _COUNTW { w: self }
+    }
+}

src/ftm1/cntin/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CNTIN {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct INITR {
+    bits: u16,
+}
+impl INITR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INITW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - INIT"]
+    #[inline]
+    pub fn init(&self) -> INITR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        INITR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - INIT"]
+    #[inline]
+    pub fn init(&mut self) -> _INITW {
+        _INITW { w: self }
+    }
+}

src/ftm1/conf/mod.rs

@@ -0,0 +1,381 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::CONF {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct LDFQR {
+    bits: u8,
+}
+impl LDFQR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct BDMMODER {
+    bits: u8,
+}
+impl BDMMODER {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct GTBEENR {
+    bits: bool,
+}
+impl GTBEENR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = r" Value of the field"]
+pub struct GTBEOUTR {
+    bits: bool,
+}
+impl GTBEOUTR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        self.bits
+    }
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+}
+#[doc = "Possible values of the field `ITRIGR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum ITRIGRR {
+    #[doc = "Initialization trigger is generated on counter wrap events."]
+    _0,
+    #[doc = "Initialization trigger is generated when a reload point is reached."]
+    _1,
+}
+impl ITRIGRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            ITRIGRR::_0 => false,
+            ITRIGRR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> ITRIGRR {
+        match value {
+            false => ITRIGRR::_0,
+            true => ITRIGRR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == ITRIGRR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == ITRIGRR::_1
+    }
+}
+#[doc = r" Proxy"]
+pub struct _LDFQW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _LDFQW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 31;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _BDMMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _BDMMODEW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _GTBEENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _GTBEENW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 9;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _GTBEOUTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _GTBEOUTW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 10;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `ITRIGR`"]
+pub enum ITRIGRW {
+    #[doc = "Initialization trigger is generated on counter wrap events."]
+    _0,
+    #[doc = "Initialization trigger is generated when a reload point is reached."]
+    _1,
+}
+impl ITRIGRW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            ITRIGRW::_0 => false,
+            ITRIGRW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _ITRIGRW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _ITRIGRW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: ITRIGRW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Initialization trigger is generated on counter wrap events."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(ITRIGRW::_0)
+    }
+    #[doc = "Initialization trigger is generated when a reload point is reached."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(ITRIGRW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 11;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:4 - Frequency of the Reload Opportunities"]
+    #[inline]
+    pub fn ldfq(&self) -> LDFQR {
+        let bits = {
+            const MASK: u8 = 31;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        LDFQR { bits }
+    }
+    #[doc = "Bits 6:7 - Debug Mode"]
+    #[inline]
+    pub fn bdmmode(&self) -> BDMMODER {
+        let bits = {
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        BDMMODER { bits }
+    }
+    #[doc = "Bit 9 - Global Time Base Enable"]
+    #[inline]
+    pub fn gtbeen(&self) -> GTBEENR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 9;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        GTBEENR { bits }
+    }
+    #[doc = "Bit 10 - Global Time Base Output"]
+    #[inline]
+    pub fn gtbeout(&self) -> GTBEOUTR {
+        let bits = {
+            const MASK: bool = true;
+            const OFFSET: u8 = 10;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        };
+        GTBEOUTR { bits }
+    }
+    #[doc = "Bit 11 - Initialization trigger on Reload Point"]
+    #[inline]
+    pub fn itrigr(&self) -> ITRIGRR {
+        ITRIGRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 11;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:4 - Frequency of the Reload Opportunities"]
+    #[inline]
+    pub fn ldfq(&mut self) -> _LDFQW {
+        _LDFQW { w: self }
+    }
+    #[doc = "Bits 6:7 - Debug Mode"]
+    #[inline]
+    pub fn bdmmode(&mut self) -> _BDMMODEW {
+        _BDMMODEW { w: self }
+    }
+    #[doc = "Bit 9 - Global Time Base Enable"]
+    #[inline]
+    pub fn gtbeen(&mut self) -> _GTBEENW {
+        _GTBEENW { w: self }
+    }
+    #[doc = "Bit 10 - Global Time Base Output"]
+    #[inline]
+    pub fn gtbeout(&mut self) -> _GTBEOUTW {
+        _GTBEOUTW { w: self }
+    }
+    #[doc = "Bit 11 - Initialization trigger on Reload Point"]
+    #[inline]
+    pub fn itrigr(&mut self) -> _ITRIGRW {
+        _ITRIGRW { w: self }
+    }
+}

src/ftm1/deadtime/mod.rs

@@ -0,0 +1,264 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::DEADTIME {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DTVALR {
+    bits: u8,
+}
+impl DTVALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `DTPS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DTPSR {
+    #[doc = "Divide the FTM input clock by 1."]
+    _0X,
+    #[doc = "Divide the FTM input clock by 4."]
+    _10,
+    #[doc = "Divide the FTM input clock by 16."]
+    _11,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl DTPSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            DTPSR::_0X => 0,
+            DTPSR::_10 => 2,
+            DTPSR::_11 => 3,
+            DTPSR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> DTPSR {
+        match value {
+            0 => DTPSR::_0X,
+            2 => DTPSR::_10,
+            3 => DTPSR::_11,
+            i => DTPSR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0X`"]
+    #[inline]
+    pub fn is_0x(&self) -> bool {
+        *self == DTPSR::_0X
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == DTPSR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == DTPSR::_11
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DTVALEXR {
+    bits: u8,
+}
+impl DTVALEXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTVALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTVALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DTPS`"]
+pub enum DTPSW {
+    #[doc = "Divide the FTM input clock by 1."]
+    _0X,
+    #[doc = "Divide the FTM input clock by 4."]
+    _10,
+    #[doc = "Divide the FTM input clock by 16."]
+    _11,
+}
+impl DTPSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            DTPSW::_0X => 0,
+            DTPSW::_10 => 2,
+            DTPSW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTPSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTPSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DTPSW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Divide the FTM input clock by 1."]
+    #[inline]
+    pub fn _0x(self) -> &'a mut W {
+        self.variant(DTPSW::_0X)
+    }
+    #[doc = "Divide the FTM input clock by 4."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(DTPSW::_10)
+    }
+    #[doc = "Divide the FTM input clock by 16."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(DTPSW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTVALEXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTVALEXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:5 - Deadtime Value"]
+    #[inline]
+    pub fn dtval(&self) -> DTVALR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DTVALR { bits }
+    }
+    #[doc = "Bits 6:7 - Deadtime Prescaler Value"]
+    #[inline]
+    pub fn dtps(&self) -> DTPSR {
+        DTPSR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 16:19 - Extended Deadtime Value"]
+    #[inline]
+    pub fn dtvalex(&self) -> DTVALEXR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DTVALEXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:5 - Deadtime Value"]
+    #[inline]
+    pub fn dtval(&mut self) -> _DTVALW {
+        _DTVALW { w: self }
+    }
+    #[doc = "Bits 6:7 - Deadtime Prescaler Value"]
+    #[inline]
+    pub fn dtps(&mut self) -> _DTPSW {
+        _DTPSW { w: self }
+    }
+    #[doc = "Bits 16:19 - Extended Deadtime Value"]
+    #[inline]
+    pub fn dtvalex(&mut self) -> _DTVALEXW {
+        _DTVALEXW { w: self }
+    }
+}

src/ftm1/filter/mod.rs

@@ -0,0 +1,226 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FILTER {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH0FVALR {
+    bits: u8,
+}
+impl CH0FVALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH1FVALR {
+    bits: u8,
+}
+impl CH1FVALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH2FVALR {
+    bits: u8,
+}
+impl CH2FVALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Value of the field"]
+pub struct CH3FVALR {
+    bits: u8,
+}
+impl CH3FVALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH0FVALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH0FVALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH1FVALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH1FVALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH2FVALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH2FVALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 8;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CH3FVALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CH3FVALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 12;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:3 - Channel 0 Input Filter"]
+    #[inline]
+    pub fn ch0fval(&self) -> CH0FVALR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CH0FVALR { bits }
+    }
+    #[doc = "Bits 4:7 - Channel 1 Input Filter"]
+    #[inline]
+    pub fn ch1fval(&self) -> CH1FVALR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CH1FVALR { bits }
+    }
+    #[doc = "Bits 8:11 - Channel 2 Input Filter"]
+    #[inline]
+    pub fn ch2fval(&self) -> CH2FVALR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 8;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CH2FVALR { bits }
+    }
+    #[doc = "Bits 12:15 - Channel 3 Input Filter"]
+    #[inline]
+    pub fn ch3fval(&self) -> CH3FVALR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 12;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        CH3FVALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:3 - Channel 0 Input Filter"]
+    #[inline]
+    pub fn ch0fval(&mut self) -> _CH0FVALW {
+        _CH0FVALW { w: self }
+    }
+    #[doc = "Bits 4:7 - Channel 1 Input Filter"]
+    #[inline]
+    pub fn ch1fval(&mut self) -> _CH1FVALW {
+        _CH1FVALW { w: self }
+    }
+    #[doc = "Bits 8:11 - Channel 2 Input Filter"]
+    #[inline]
+    pub fn ch2fval(&mut self) -> _CH2FVALW {
+        _CH2FVALW { w: self }
+    }
+    #[doc = "Bits 12:15 - Channel 3 Input Filter"]
+    #[inline]
+    pub fn ch3fval(&mut self) -> _CH3FVALW {
+        _CH3FVALW { w: self }
+    }
+}

src/ftm1/fltpol/mod.rs

@@ -0,0 +1,538 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FLTPOL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `FLT0POL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FLT0POLR {
+    #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
+    _0,
+    #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
+    _1,
+}
+impl FLT0POLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FLT0POLR::_0 => false,
+            FLT0POLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FLT0POLR {
+        match value {
+            false => FLT0POLR::_0,
+            true => FLT0POLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FLT0POLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FLT0POLR::_1
+    }
+}
+#[doc = "Possible values of the field `FLT1POL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FLT1POLR {
+    #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
+    _0,
+    #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
+    _1,
+}
+impl FLT1POLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FLT1POLR::_0 => false,
+            FLT1POLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FLT1POLR {
+        match value {
+            false => FLT1POLR::_0,
+            true => FLT1POLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FLT1POLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FLT1POLR::_1
+    }
+}
+#[doc = "Possible values of the field `FLT2POL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FLT2POLR {
+    #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
+    _0,
+    #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
+    _1,
+}
+impl FLT2POLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FLT2POLR::_0 => false,
+            FLT2POLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FLT2POLR {
+        match value {
+            false => FLT2POLR::_0,
+            true => FLT2POLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FLT2POLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FLT2POLR::_1
+    }
+}
+#[doc = "Possible values of the field `FLT3POL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FLT3POLR {
+    #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
+    _0,
+    #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
+    _1,
+}
+impl FLT3POLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FLT3POLR::_0 => false,
+            FLT3POLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FLT3POLR {
+        match value {
+            false => FLT3POLR::_0,
+            true => FLT3POLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FLT3POLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FLT3POLR::_1
+    }
+}
+#[doc = "Values that can be written to the field `FLT0POL`"]
+pub enum FLT0POLW {
+    #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
+    _0,
+    #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
+    _1,
+}
+impl FLT0POLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FLT0POLW::_0 => false,
+            FLT0POLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FLT0POLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FLT0POLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FLT0POLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FLT0POLW::_0)
+    }
+    #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FLT0POLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FLT1POL`"]
+pub enum FLT1POLW {
+    #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
+    _0,
+    #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
+    _1,
+}
+impl FLT1POLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FLT1POLW::_0 => false,
+            FLT1POLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FLT1POLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FLT1POLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FLT1POLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FLT1POLW::_0)
+    }
+    #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FLT1POLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FLT2POL`"]
+pub enum FLT2POLW {
+    #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
+    _0,
+    #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
+    _1,
+}
+impl FLT2POLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FLT2POLW::_0 => false,
+            FLT2POLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FLT2POLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FLT2POLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FLT2POLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FLT2POLW::_0)
+    }
+    #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FLT2POLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FLT3POL`"]
+pub enum FLT3POLW {
+    #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
+    _0,
+    #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
+    _1,
+}
+impl FLT3POLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FLT3POLW::_0 => false,
+            FLT3POLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FLT3POLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FLT3POLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FLT3POLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "The fault input polarity is active high. A 1 at the fault input indicates a fault."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FLT3POLW::_0)
+    }
+    #[doc = "The fault input polarity is active low. A 0 at the fault input indicates a fault."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FLT3POLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Fault Input 0 Polarity"]
+    #[inline]
+    pub fn flt0pol(&self) -> FLT0POLR {
+        FLT0POLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Fault Input 1 Polarity"]
+    #[inline]
+    pub fn flt1pol(&self) -> FLT1POLR {
+        FLT1POLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Fault Input 2 Polarity"]
+    #[inline]
+    pub fn flt2pol(&self) -> FLT2POLR {
+        FLT2POLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Fault Input 3 Polarity"]
+    #[inline]
+    pub fn flt3pol(&self) -> FLT3POLR {
+        FLT3POLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Fault Input 0 Polarity"]
+    #[inline]
+    pub fn flt0pol(&mut self) -> _FLT0POLW {
+        _FLT0POLW { w: self }
+    }
+    #[doc = "Bit 1 - Fault Input 1 Polarity"]
+    #[inline]
+    pub fn flt1pol(&mut self) -> _FLT1POLW {
+        _FLT1POLW { w: self }
+    }
+    #[doc = "Bit 2 - Fault Input 2 Polarity"]
+    #[inline]
+    pub fn flt2pol(&mut self) -> _FLT2POLW {
+        _FLT2POLW { w: self }
+    }
+    #[doc = "Bit 3 - Fault Input 3 Polarity"]
+    #[inline]
+    pub fn flt3pol(&mut self) -> _FLT3POLW {
+        _FLT3POLW { w: self }
+    }
+}

src/ftm1/fms/mod.rs

@@ -0,0 +1,517 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::FMS {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `FAULTF0`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FAULTF0R {
+    #[doc = "No fault condition was detected at the fault input."]
+    _0,
+    #[doc = "A fault condition was detected at the fault input."]
+    _1,
+}
+impl FAULTF0R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FAULTF0R::_0 => false,
+            FAULTF0R::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FAULTF0R {
+        match value {
+            false => FAULTF0R::_0,
+            true => FAULTF0R::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FAULTF0R::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FAULTF0R::_1
+    }
+}
+#[doc = "Possible values of the field `FAULTF1`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FAULTF1R {
+    #[doc = "No fault condition was detected at the fault input."]
+    _0,
+    #[doc = "A fault condition was detected at the fault input."]
+    _1,
+}
+impl FAULTF1R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FAULTF1R::_0 => false,
+            FAULTF1R::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FAULTF1R {
+        match value {
+            false => FAULTF1R::_0,
+            true => FAULTF1R::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FAULTF1R::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FAULTF1R::_1
+    }
+}
+#[doc = "Possible values of the field `FAULTF2`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FAULTF2R {
+    #[doc = "No fault condition was detected at the fault input."]
+    _0,
+    #[doc = "A fault condition was detected at the fault input."]
+    _1,
+}
+impl FAULTF2R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FAULTF2R::_0 => false,
+            FAULTF2R::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FAULTF2R {
+        match value {
+            false => FAULTF2R::_0,
+            true => FAULTF2R::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FAULTF2R::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FAULTF2R::_1
+    }
+}
+#[doc = "Possible values of the field `FAULTF3`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FAULTF3R {
+    #[doc = "No fault condition was detected at the fault input."]
+    _0,
+    #[doc = "A fault condition was detected at the fault input."]
+    _1,
+}
+impl FAULTF3R {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FAULTF3R::_0 => false,
+            FAULTF3R::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FAULTF3R {
+        match value {
+            false => FAULTF3R::_0,
+            true => FAULTF3R::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FAULTF3R::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FAULTF3R::_1
+    }
+}
+#[doc = "Possible values of the field `FAULTIN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FAULTINR {
+    #[doc = "The logic OR of the enabled fault inputs is 0."]
+    _0,
+    #[doc = "The logic OR of the enabled fault inputs is 1."]
+    _1,
+}
+impl FAULTINR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FAULTINR::_0 => false,
+            FAULTINR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FAULTINR {
+        match value {
+            false => FAULTINR::_0,
+            true => FAULTINR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FAULTINR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FAULTINR::_1
+    }
+}
+#[doc = "Possible values of the field `WPEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WPENR {
+    #[doc = "Write protection is disabled. Write protected bits can be written."]
+    _0,
+    #[doc = "Write protection is enabled. Write protected bits cannot be written."]
+    _1,
+}
+impl WPENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            WPENR::_0 => false,
+            WPENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> WPENR {
+        match value {
+            false => WPENR::_0,
+            true => WPENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == WPENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == WPENR::_1
+    }
+}
+#[doc = "Possible values of the field `FAULTF`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FAULTFR {
+    #[doc = "No fault condition was detected."]
+    _0,
+    #[doc = "A fault condition was detected."]
+    _1,
+}
+impl FAULTFR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FAULTFR::_0 => false,
+            FAULTFR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FAULTFR {
+        match value {
+            false => FAULTFR::_0,
+            true => FAULTFR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FAULTFR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FAULTFR::_1
+    }
+}
+#[doc = "Values that can be written to the field `WPEN`"]
+pub enum WPENW {
+    #[doc = "Write protection is disabled. Write protected bits can be written."]
+    _0,
+    #[doc = "Write protection is enabled. Write protected bits cannot be written."]
+    _1,
+}
+impl WPENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            WPENW::_0 => false,
+            WPENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _WPENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _WPENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: WPENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Write protection is disabled. Write protected bits can be written."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(WPENW::_0)
+    }
+    #[doc = "Write protection is enabled. Write protected bits cannot be written."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(WPENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Fault Detection Flag 0"]
+    #[inline]
+    pub fn faultf0(&self) -> FAULTF0R {
+        FAULTF0R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Fault Detection Flag 1"]
+    #[inline]
+    pub fn faultf1(&self) -> FAULTF1R {
+        FAULTF1R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Fault Detection Flag 2"]
+    #[inline]
+    pub fn faultf2(&self) -> FAULTF2R {
+        FAULTF2R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Fault Detection Flag 3"]
+    #[inline]
+    pub fn faultf3(&self) -> FAULTF3R {
+        FAULTF3R::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - Fault Inputs"]
+    #[inline]
+    pub fn faultin(&self) -> FAULTINR {
+        FAULTINR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - Write Protection Enable"]
+    #[inline]
+    pub fn wpen(&self) -> WPENR {
+        WPENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Fault Detection Flag"]
+    #[inline]
+    pub fn faultf(&self) -> FAULTFR {
+        FAULTFR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 6 - Write Protection Enable"]
+    #[inline]
+    pub fn wpen(&mut self) -> _WPENW {
+        _WPENW { w: self }
+    }
+}

src/ftm1/hcr/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::HCR {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct HCVALR {
+    bits: u16,
+}
+impl HCVALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _HCVALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _HCVALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - Half Cycle Value"]
+    #[inline]
+    pub fn hcval(&self) -> HCVALR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        HCVALR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - Half Cycle Value"]
+    #[inline]
+    pub fn hcval(&mut self) -> _HCVALW {
+        _HCVALW { w: self }
+    }
+}

src/ftm1/invctrl/mod.rs

@@ -0,0 +1,538 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::INVCTRL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `INV0EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INV0ENR {
+    #[doc = "Inverting is disabled."]
+    _0,
+    #[doc = "Inverting is enabled."]
+    _1,
+}
+impl INV0ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            INV0ENR::_0 => false,
+            INV0ENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> INV0ENR {
+        match value {
+            false => INV0ENR::_0,
+            true => INV0ENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == INV0ENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == INV0ENR::_1
+    }
+}
+#[doc = "Possible values of the field `INV1EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INV1ENR {
+    #[doc = "Inverting is disabled."]
+    _0,
+    #[doc = "Inverting is enabled."]
+    _1,
+}
+impl INV1ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            INV1ENR::_0 => false,
+            INV1ENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> INV1ENR {
+        match value {
+            false => INV1ENR::_0,
+            true => INV1ENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == INV1ENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == INV1ENR::_1
+    }
+}
+#[doc = "Possible values of the field `INV2EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INV2ENR {
+    #[doc = "Inverting is disabled."]
+    _0,
+    #[doc = "Inverting is enabled."]
+    _1,
+}
+impl INV2ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            INV2ENR::_0 => false,
+            INV2ENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> INV2ENR {
+        match value {
+            false => INV2ENR::_0,
+            true => INV2ENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == INV2ENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == INV2ENR::_1
+    }
+}
+#[doc = "Possible values of the field `INV3EN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum INV3ENR {
+    #[doc = "Inverting is disabled."]
+    _0,
+    #[doc = "Inverting is enabled."]
+    _1,
+}
+impl INV3ENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            INV3ENR::_0 => false,
+            INV3ENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> INV3ENR {
+        match value {
+            false => INV3ENR::_0,
+            true => INV3ENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == INV3ENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == INV3ENR::_1
+    }
+}
+#[doc = "Values that can be written to the field `INV0EN`"]
+pub enum INV0ENW {
+    #[doc = "Inverting is disabled."]
+    _0,
+    #[doc = "Inverting is enabled."]
+    _1,
+}
+impl INV0ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            INV0ENW::_0 => false,
+            INV0ENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INV0ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INV0ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: INV0ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Inverting is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(INV0ENW::_0)
+    }
+    #[doc = "Inverting is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(INV0ENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `INV1EN`"]
+pub enum INV1ENW {
+    #[doc = "Inverting is disabled."]
+    _0,
+    #[doc = "Inverting is enabled."]
+    _1,
+}
+impl INV1ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            INV1ENW::_0 => false,
+            INV1ENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INV1ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INV1ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: INV1ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Inverting is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(INV1ENW::_0)
+    }
+    #[doc = "Inverting is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(INV1ENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `INV2EN`"]
+pub enum INV2ENW {
+    #[doc = "Inverting is disabled."]
+    _0,
+    #[doc = "Inverting is enabled."]
+    _1,
+}
+impl INV2ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            INV2ENW::_0 => false,
+            INV2ENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INV2ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INV2ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: INV2ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Inverting is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(INV2ENW::_0)
+    }
+    #[doc = "Inverting is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(INV2ENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `INV3EN`"]
+pub enum INV3ENW {
+    #[doc = "Inverting is disabled."]
+    _0,
+    #[doc = "Inverting is enabled."]
+    _1,
+}
+impl INV3ENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            INV3ENW::_0 => false,
+            INV3ENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INV3ENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INV3ENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: INV3ENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Inverting is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(INV3ENW::_0)
+    }
+    #[doc = "Inverting is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(INV3ENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Pair Channels 0 Inverting Enable"]
+    #[inline]
+    pub fn inv0en(&self) -> INV0ENR {
+        INV0ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Pair Channels 1 Inverting Enable"]
+    #[inline]
+    pub fn inv1en(&self) -> INV1ENR {
+        INV1ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Pair Channels 2 Inverting Enable"]
+    #[inline]
+    pub fn inv2en(&self) -> INV2ENR {
+        INV2ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Pair Channels 3 Inverting Enable"]
+    #[inline]
+    pub fn inv3en(&self) -> INV3ENR {
+        INV3ENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Pair Channels 0 Inverting Enable"]
+    #[inline]
+    pub fn inv0en(&mut self) -> _INV0ENW {
+        _INV0ENW { w: self }
+    }
+    #[doc = "Bit 1 - Pair Channels 1 Inverting Enable"]
+    #[inline]
+    pub fn inv1en(&mut self) -> _INV1ENW {
+        _INV1ENW { w: self }
+    }
+    #[doc = "Bit 2 - Pair Channels 2 Inverting Enable"]
+    #[inline]
+    pub fn inv2en(&mut self) -> _INV2ENW {
+        _INV2ENW { w: self }
+    }
+    #[doc = "Bit 3 - Pair Channels 3 Inverting Enable"]
+    #[inline]
+    pub fn inv3en(&mut self) -> _INV3ENW {
+        _INV3ENW { w: self }
+    }
+}

src/ftm1/mod.rs

@@ -0,0 +1,360 @@
+use vcell::VolatileCell;
+#[doc = r" Register block"]
+#[repr(C)]
+pub struct RegisterBlock {
+    #[doc = "0x00 - Status And Control"]
+    pub sc: SC,
+    #[doc = "0x04 - Counter"]
+    pub cnt: CNT,
+    #[doc = "0x08 - Modulo"]
+    pub mod_: MOD,
+    #[doc = "0x0c - Channel (n) Status And Control"]
+    pub c0sc: C0SC,
+    #[doc = "0x10 - Channel (n) Value"]
+    pub c0v: C0V,
+    #[doc = "0x14 - Channel (n) Status And Control"]
+    pub c1sc: C1SC,
+    #[doc = "0x18 - Channel (n) Value"]
+    pub c1v: C1V,
+    #[doc = "0x1c - Channel (n) Status And Control"]
+    pub c2sc: C2SC,
+    #[doc = "0x20 - Channel (n) Value"]
+    pub c2v: C2V,
+    #[doc = "0x24 - Channel (n) Status And Control"]
+    pub c3sc: C3SC,
+    #[doc = "0x28 - Channel (n) Value"]
+    pub c3v: C3V,
+    #[doc = "0x2c - Channel (n) Status And Control"]
+    pub c4sc: C4SC,
+    #[doc = "0x30 - Channel (n) Value"]
+    pub c4v: C4V,
+    #[doc = "0x34 - Channel (n) Status And Control"]
+    pub c5sc: C5SC,
+    #[doc = "0x38 - Channel (n) Value"]
+    pub c5v: C5V,
+    #[doc = "0x3c - Channel (n) Status And Control"]
+    pub c6sc: C6SC,
+    #[doc = "0x40 - Channel (n) Value"]
+    pub c6v: C6V,
+    #[doc = "0x44 - Channel (n) Status And Control"]
+    pub c7sc: C7SC,
+    #[doc = "0x48 - Channel (n) Value"]
+    pub c7v: C7V,
+    #[doc = "0x4c - Counter Initial Value"]
+    pub cntin: CNTIN,
+    #[doc = "0x50 - Capture And Compare Status"]
+    pub status: STATUS,
+    #[doc = "0x54 - Features Mode Selection"]
+    pub mode: MODE,
+    #[doc = "0x58 - Synchronization"]
+    pub sync: SYNC,
+    #[doc = "0x5c - Initial State For Channels Output"]
+    pub outinit: OUTINIT,
+    #[doc = "0x60 - Output Mask"]
+    pub outmask: OUTMASK,
+    #[doc = "0x64 - Function For Linked Channels"]
+    pub combine: COMBINE,
+    #[doc = "0x68 - Deadtime Configuration"]
+    pub deadtime: DEADTIME,
+    #[doc = "0x6c - FTM External Trigger"]
+    pub exttrig: EXTTRIG,
+    #[doc = "0x70 - Channels Polarity"]
+    pub pol: POL,
+    #[doc = "0x74 - Fault Mode Status"]
+    pub fms: FMS,
+    #[doc = "0x78 - Input Capture Filter Control"]
+    pub filter: FILTER,
+    #[doc = "0x7c - Fault Control"]
+    pub fltctrl: FLTCTRL,
+    #[doc = "0x80 - Quadrature Decoder Control And Status"]
+    pub qdctrl: QDCTRL,
+    #[doc = "0x84 - Configuration"]
+    pub conf: CONF,
+    #[doc = "0x88 - FTM Fault Input Polarity"]
+    pub fltpol: FLTPOL,
+    #[doc = "0x8c - Synchronization Configuration"]
+    pub synconf: SYNCONF,
+    #[doc = "0x90 - FTM Inverting Control"]
+    pub invctrl: INVCTRL,
+    #[doc = "0x94 - FTM Software Output Control"]
+    pub swoctrl: SWOCTRL,
+    #[doc = "0x98 - FTM PWM Load"]
+    pub pwmload: PWMLOAD,
+    #[doc = "0x9c - Half Cycle Register"]
+    pub hcr: HCR,
+    #[doc = "0xa0 - Pair 0 Deadtime Configuration"]
+    pub pair0deadtime: PAIR0DEADTIME,
+    _reserved0: [u8; 4usize],
+    #[doc = "0xa8 - Pair 1 Deadtime Configuration"]
+    pub pair1deadtime: PAIR1DEADTIME,
+    _reserved1: [u8; 4usize],
+    #[doc = "0xb0 - Pair 2 Deadtime Configuration"]
+    pub pair2deadtime: PAIR2DEADTIME,
+    _reserved2: [u8; 4usize],
+    #[doc = "0xb8 - Pair 3 Deadtime Configuration"]
+    pub pair3deadtime: PAIR3DEADTIME,
+}
+#[doc = "Status And Control"]
+pub struct SC {
+    register: VolatileCell<u32>,
+}
+#[doc = "Status And Control"]
+pub mod sc;
+#[doc = "Counter"]
+pub struct CNT {
+    register: VolatileCell<u32>,
+}
+#[doc = "Counter"]
+pub mod cnt;
+#[doc = "Modulo"]
+pub struct MOD {
+    register: VolatileCell<u32>,
+}
+#[doc = "Modulo"]
+pub mod mod_;
+#[doc = "Channel (n) Status And Control"]
+pub struct C0SC {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Status And Control"]
+pub mod c0sc;
+#[doc = "Channel (n) Value"]
+pub struct C0V {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Value"]
+pub mod c0v;
+#[doc = "Channel (n) Status And Control"]
+pub struct C1SC {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Status And Control"]
+pub mod c1sc;
+#[doc = "Channel (n) Value"]
+pub struct C1V {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Value"]
+pub mod c1v;
+#[doc = "Channel (n) Status And Control"]
+pub struct C2SC {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Status And Control"]
+pub mod c2sc;
+#[doc = "Channel (n) Value"]
+pub struct C2V {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Value"]
+pub mod c2v;
+#[doc = "Channel (n) Status And Control"]
+pub struct C3SC {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Status And Control"]
+pub mod c3sc;
+#[doc = "Channel (n) Value"]
+pub struct C3V {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Value"]
+pub mod c3v;
+#[doc = "Channel (n) Status And Control"]
+pub struct C4SC {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Status And Control"]
+pub mod c4sc;
+#[doc = "Channel (n) Value"]
+pub struct C4V {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Value"]
+pub mod c4v;
+#[doc = "Channel (n) Status And Control"]
+pub struct C5SC {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Status And Control"]
+pub mod c5sc;
+#[doc = "Channel (n) Value"]
+pub struct C5V {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Value"]
+pub mod c5v;
+#[doc = "Channel (n) Status And Control"]
+pub struct C6SC {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Status And Control"]
+pub mod c6sc;
+#[doc = "Channel (n) Value"]
+pub struct C6V {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Value"]
+pub mod c6v;
+#[doc = "Channel (n) Status And Control"]
+pub struct C7SC {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Status And Control"]
+pub mod c7sc;
+#[doc = "Channel (n) Value"]
+pub struct C7V {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channel (n) Value"]
+pub mod c7v;
+#[doc = "Counter Initial Value"]
+pub struct CNTIN {
+    register: VolatileCell<u32>,
+}
+#[doc = "Counter Initial Value"]
+pub mod cntin;
+#[doc = "Capture And Compare Status"]
+pub struct STATUS {
+    register: VolatileCell<u32>,
+}
+#[doc = "Capture And Compare Status"]
+pub mod status;
+#[doc = "Features Mode Selection"]
+pub struct MODE {
+    register: VolatileCell<u32>,
+}
+#[doc = "Features Mode Selection"]
+pub mod mode;
+#[doc = "Synchronization"]
+pub struct SYNC {
+    register: VolatileCell<u32>,
+}
+#[doc = "Synchronization"]
+pub mod sync;
+#[doc = "Initial State For Channels Output"]
+pub struct OUTINIT {
+    register: VolatileCell<u32>,
+}
+#[doc = "Initial State For Channels Output"]
+pub mod outinit;
+#[doc = "Output Mask"]
+pub struct OUTMASK {
+    register: VolatileCell<u32>,
+}
+#[doc = "Output Mask"]
+pub mod outmask;
+#[doc = "Function For Linked Channels"]
+pub struct COMBINE {
+    register: VolatileCell<u32>,
+}
+#[doc = "Function For Linked Channels"]
+pub mod combine;
+#[doc = "Deadtime Configuration"]
+pub struct DEADTIME {
+    register: VolatileCell<u32>,
+}
+#[doc = "Deadtime Configuration"]
+pub mod deadtime;
+#[doc = "FTM External Trigger"]
+pub struct EXTTRIG {
+    register: VolatileCell<u32>,
+}
+#[doc = "FTM External Trigger"]
+pub mod exttrig;
+#[doc = "Channels Polarity"]
+pub struct POL {
+    register: VolatileCell<u32>,
+}
+#[doc = "Channels Polarity"]
+pub mod pol;
+#[doc = "Fault Mode Status"]
+pub struct FMS {
+    register: VolatileCell<u32>,
+}
+#[doc = "Fault Mode Status"]
+pub mod fms;
+#[doc = "Input Capture Filter Control"]
+pub struct FILTER {
+    register: VolatileCell<u32>,
+}
+#[doc = "Input Capture Filter Control"]
+pub mod filter;
+#[doc = "Fault Control"]
+pub struct FLTCTRL {
+    register: VolatileCell<u32>,
+}
+#[doc = "Fault Control"]
+pub mod fltctrl;
+#[doc = "Quadrature Decoder Control And Status"]
+pub struct QDCTRL {
+    register: VolatileCell<u32>,
+}
+#[doc = "Quadrature Decoder Control And Status"]
+pub mod qdctrl;
+#[doc = "Configuration"]
+pub struct CONF {
+    register: VolatileCell<u32>,
+}
+#[doc = "Configuration"]
+pub mod conf;
+#[doc = "FTM Fault Input Polarity"]
+pub struct FLTPOL {
+    register: VolatileCell<u32>,
+}
+#[doc = "FTM Fault Input Polarity"]
+pub mod fltpol;
+#[doc = "Synchronization Configuration"]
+pub struct SYNCONF {
+    register: VolatileCell<u32>,
+}
+#[doc = "Synchronization Configuration"]
+pub mod synconf;
+#[doc = "FTM Inverting Control"]
+pub struct INVCTRL {
+    register: VolatileCell<u32>,
+}
+#[doc = "FTM Inverting Control"]
+pub mod invctrl;
+#[doc = "FTM Software Output Control"]
+pub struct SWOCTRL {
+    register: VolatileCell<u32>,
+}
+#[doc = "FTM Software Output Control"]
+pub mod swoctrl;
+#[doc = "FTM PWM Load"]
+pub struct PWMLOAD {
+    register: VolatileCell<u32>,
+}
+#[doc = "FTM PWM Load"]
+pub mod pwmload;
+#[doc = "Half Cycle Register"]
+pub struct HCR {
+    register: VolatileCell<u32>,
+}
+#[doc = "Half Cycle Register"]
+pub mod hcr;
+#[doc = "Pair 0 Deadtime Configuration"]
+pub struct PAIR0DEADTIME {
+    register: VolatileCell<u32>,
+}
+#[doc = "Pair 0 Deadtime Configuration"]
+pub mod pair0deadtime;
+#[doc = "Pair 1 Deadtime Configuration"]
+pub struct PAIR1DEADTIME {
+    register: VolatileCell<u32>,
+}
+#[doc = "Pair 1 Deadtime Configuration"]
+pub mod pair1deadtime;
+#[doc = "Pair 2 Deadtime Configuration"]
+pub struct PAIR2DEADTIME {
+    register: VolatileCell<u32>,
+}
+#[doc = "Pair 2 Deadtime Configuration"]
+pub mod pair2deadtime;
+#[doc = "Pair 3 Deadtime Configuration"]
+pub struct PAIR3DEADTIME {
+    register: VolatileCell<u32>,
+}
+#[doc = "Pair 3 Deadtime Configuration"]
+pub mod pair3deadtime;

src/ftm1/mod_/mod.rs

@@ -0,0 +1,103 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::MOD {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct MODR {
+    bits: u16,
+}
+impl MODR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u16 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _MODW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _MODW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u16) -> &'a mut W {
+        const MASK: u16 = 65535;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:15 - MOD"]
+    #[inline]
+    pub fn mod_(&self) -> MODR {
+        let bits = {
+            const MASK: u16 = 65535;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u16
+        };
+        MODR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:15 - MOD"]
+    #[inline]
+    pub fn mod_(&mut self) -> _MODW {
+        _MODW { w: self }
+    }
+}

src/ftm1/mode/mod.rs

@@ -0,0 +1,821 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::MODE {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `FTMEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FTMENR {
+    #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."]
+    _0,
+    #[doc = "Free running counter and synchronization are different from TPM behavior."]
+    _1,
+}
+impl FTMENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FTMENR::_0 => false,
+            FTMENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FTMENR {
+        match value {
+            false => FTMENR::_0,
+            true => FTMENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FTMENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FTMENR::_1
+    }
+}
+#[doc = "Possible values of the field `WPDIS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum WPDISR {
+    #[doc = "Write protection is enabled."]
+    _0,
+    #[doc = "Write protection is disabled."]
+    _1,
+}
+impl WPDISR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            WPDISR::_0 => false,
+            WPDISR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> WPDISR {
+        match value {
+            false => WPDISR::_0,
+            true => WPDISR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == WPDISR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == WPDISR::_1
+    }
+}
+#[doc = "Possible values of the field `PWMSYNC`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PWMSYNCR {
+    #[doc = "No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization."]
+    _0,
+    #[doc = "Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization."]
+    _1,
+}
+impl PWMSYNCR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PWMSYNCR::_0 => false,
+            PWMSYNCR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PWMSYNCR {
+        match value {
+            false => PWMSYNCR::_0,
+            true => PWMSYNCR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PWMSYNCR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PWMSYNCR::_1
+    }
+}
+#[doc = "Possible values of the field `CAPTEST`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CAPTESTR {
+    #[doc = "Capture test mode is disabled."]
+    _0,
+    #[doc = "Capture test mode is enabled."]
+    _1,
+}
+impl CAPTESTR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CAPTESTR::_0 => false,
+            CAPTESTR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CAPTESTR {
+        match value {
+            false => CAPTESTR::_0,
+            true => CAPTESTR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CAPTESTR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CAPTESTR::_1
+    }
+}
+#[doc = "Possible values of the field `FAULTM`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FAULTMR {
+    #[doc = "Fault control is disabled for all channels."]
+    _00,
+    #[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."]
+    _01,
+    #[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."]
+    _10,
+    #[doc = "Fault control is enabled for all channels, and the selected mode is the automatic fault clearing."]
+    _11,
+}
+impl FAULTMR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            FAULTMR::_00 => 0,
+            FAULTMR::_01 => 1,
+            FAULTMR::_10 => 2,
+            FAULTMR::_11 => 3,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> FAULTMR {
+        match value {
+            0 => FAULTMR::_00,
+            1 => FAULTMR::_01,
+            2 => FAULTMR::_10,
+            3 => FAULTMR::_11,
+            _ => unreachable!(),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_00`"]
+    #[inline]
+    pub fn is_00(&self) -> bool {
+        *self == FAULTMR::_00
+    }
+    #[doc = "Checks if the value of the field is `_01`"]
+    #[inline]
+    pub fn is_01(&self) -> bool {
+        *self == FAULTMR::_01
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == FAULTMR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == FAULTMR::_11
+    }
+}
+#[doc = "Possible values of the field `FAULTIE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum FAULTIER {
+    #[doc = "Fault control interrupt is disabled."]
+    _0,
+    #[doc = "Fault control interrupt is enabled."]
+    _1,
+}
+impl FAULTIER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            FAULTIER::_0 => false,
+            FAULTIER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> FAULTIER {
+        match value {
+            false => FAULTIER::_0,
+            true => FAULTIER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == FAULTIER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == FAULTIER::_1
+    }
+}
+#[doc = "Values that can be written to the field `FTMEN`"]
+pub enum FTMENW {
+    #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."]
+    _0,
+    #[doc = "Free running counter and synchronization are different from TPM behavior."]
+    _1,
+}
+impl FTMENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FTMENW::_0 => false,
+            FTMENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FTMENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FTMENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FTMENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "TPM compatibility. Free running counter and synchronization compatible with TPM."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FTMENW::_0)
+    }
+    #[doc = "Free running counter and synchronization are different from TPM behavior."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FTMENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _INITW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _INITW<'a> {
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 1;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `WPDIS`"]
+pub enum WPDISW {
+    #[doc = "Write protection is enabled."]
+    _0,
+    #[doc = "Write protection is disabled."]
+    _1,
+}
+impl WPDISW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            WPDISW::_0 => false,
+            WPDISW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _WPDISW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _WPDISW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: WPDISW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Write protection is enabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(WPDISW::_0)
+    }
+    #[doc = "Write protection is disabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(WPDISW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 2;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PWMSYNC`"]
+pub enum PWMSYNCW {
+    #[doc = "No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization."]
+    _0,
+    #[doc = "Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization."]
+    _1,
+}
+impl PWMSYNCW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PWMSYNCW::_0 => false,
+            PWMSYNCW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PWMSYNCW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PWMSYNCW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PWMSYNCW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PWMSYNCW::_0)
+    }
+    #[doc = "Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PWMSYNCW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `CAPTEST`"]
+pub enum CAPTESTW {
+    #[doc = "Capture test mode is disabled."]
+    _0,
+    #[doc = "Capture test mode is enabled."]
+    _1,
+}
+impl CAPTESTW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            CAPTESTW::_0 => false,
+            CAPTESTW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _CAPTESTW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _CAPTESTW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: CAPTESTW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Capture test mode is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(CAPTESTW::_0)
+    }
+    #[doc = "Capture test mode is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(CAPTESTW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FAULTM`"]
+pub enum FAULTMW {
+    #[doc = "Fault control is disabled for all channels."]
+    _00,
+    #[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."]
+    _01,
+    #[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."]
+    _10,
+    #[doc = "Fault control is enabled for all channels, and the selected mode is the automatic fault clearing."]
+    _11,
+}
+impl FAULTMW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            FAULTMW::_00 => 0,
+            FAULTMW::_01 => 1,
+            FAULTMW::_10 => 2,
+            FAULTMW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FAULTMW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FAULTMW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FAULTMW) -> &'a mut W {
+        {
+            self.bits(variant._bits())
+        }
+    }
+    #[doc = "Fault control is disabled for all channels."]
+    #[inline]
+    pub fn _00(self) -> &'a mut W {
+        self.variant(FAULTMW::_00)
+    }
+    #[doc = "Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing."]
+    #[inline]
+    pub fn _01(self) -> &'a mut W {
+        self.variant(FAULTMW::_01)
+    }
+    #[doc = "Fault control is enabled for all channels, and the selected mode is the manual fault clearing."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(FAULTMW::_10)
+    }
+    #[doc = "Fault control is enabled for all channels, and the selected mode is the automatic fault clearing."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(FAULTMW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `FAULTIE`"]
+pub enum FAULTIEW {
+    #[doc = "Fault control interrupt is disabled."]
+    _0,
+    #[doc = "Fault control interrupt is enabled."]
+    _1,
+}
+impl FAULTIEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            FAULTIEW::_0 => false,
+            FAULTIEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _FAULTIEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _FAULTIEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: FAULTIEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Fault control interrupt is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(FAULTIEW::_0)
+    }
+    #[doc = "Fault control interrupt is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(FAULTIEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - FTM Enable"]
+    #[inline]
+    pub fn ftmen(&self) -> FTMENR {
+        FTMENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Write Protection Disable"]
+    #[inline]
+    pub fn wpdis(&self) -> WPDISR {
+        WPDISR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - PWM Synchronization Mode"]
+    #[inline]
+    pub fn pwmsync(&self) -> PWMSYNCR {
+        PWMSYNCR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - Capture Test Mode Enable"]
+    #[inline]
+    pub fn captest(&self) -> CAPTESTR {
+        CAPTESTR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bits 5:6 - Fault Control Mode"]
+    #[inline]
+    pub fn faultm(&self) -> FAULTMR {
+        FAULTMR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bit 7 - Fault Interrupt Enable"]
+    #[inline]
+    pub fn faultie(&self) -> FAULTIER {
+        FAULTIER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 4 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - FTM Enable"]
+    #[inline]
+    pub fn ftmen(&mut self) -> _FTMENW {
+        _FTMENW { w: self }
+    }
+    #[doc = "Bit 1 - Initialize The Channels Output"]
+    #[inline]
+    pub fn init(&mut self) -> _INITW {
+        _INITW { w: self }
+    }
+    #[doc = "Bit 2 - Write Protection Disable"]
+    #[inline]
+    pub fn wpdis(&mut self) -> _WPDISW {
+        _WPDISW { w: self }
+    }
+    #[doc = "Bit 3 - PWM Synchronization Mode"]
+    #[inline]
+    pub fn pwmsync(&mut self) -> _PWMSYNCW {
+        _PWMSYNCW { w: self }
+    }
+    #[doc = "Bit 4 - Capture Test Mode Enable"]
+    #[inline]
+    pub fn captest(&mut self) -> _CAPTESTW {
+        _CAPTESTW { w: self }
+    }
+    #[doc = "Bits 5:6 - Fault Control Mode"]
+    #[inline]
+    pub fn faultm(&mut self) -> _FAULTMW {
+        _FAULTMW { w: self }
+    }
+    #[doc = "Bit 7 - Fault Interrupt Enable"]
+    #[inline]
+    pub fn faultie(&mut self) -> _FAULTIEW {
+        _FAULTIEW { w: self }
+    }
+}

src/ftm1/pair0deadtime/mod.rs

@@ -0,0 +1,264 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PAIR0DEADTIME {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DTVALR {
+    bits: u8,
+}
+impl DTVALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `DTPS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DTPSR {
+    #[doc = "Divide the FTM input clock by 1."]
+    _0X,
+    #[doc = "Divide the FTM input clock by 4."]
+    _10,
+    #[doc = "Divide the FTM input clock by 16."]
+    _11,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl DTPSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            DTPSR::_0X => 0,
+            DTPSR::_10 => 2,
+            DTPSR::_11 => 3,
+            DTPSR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> DTPSR {
+        match value {
+            0 => DTPSR::_0X,
+            2 => DTPSR::_10,
+            3 => DTPSR::_11,
+            i => DTPSR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0X`"]
+    #[inline]
+    pub fn is_0x(&self) -> bool {
+        *self == DTPSR::_0X
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == DTPSR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == DTPSR::_11
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DTVALEXR {
+    bits: u8,
+}
+impl DTVALEXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTVALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTVALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DTPS`"]
+pub enum DTPSW {
+    #[doc = "Divide the FTM input clock by 1."]
+    _0X,
+    #[doc = "Divide the FTM input clock by 4."]
+    _10,
+    #[doc = "Divide the FTM input clock by 16."]
+    _11,
+}
+impl DTPSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            DTPSW::_0X => 0,
+            DTPSW::_10 => 2,
+            DTPSW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTPSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTPSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DTPSW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Divide the FTM input clock by 1."]
+    #[inline]
+    pub fn _0x(self) -> &'a mut W {
+        self.variant(DTPSW::_0X)
+    }
+    #[doc = "Divide the FTM input clock by 4."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(DTPSW::_10)
+    }
+    #[doc = "Divide the FTM input clock by 16."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(DTPSW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTVALEXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTVALEXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:5 - Deadtime Value"]
+    #[inline]
+    pub fn dtval(&self) -> DTVALR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DTVALR { bits }
+    }
+    #[doc = "Bits 6:7 - Deadtime Prescaler Value"]
+    #[inline]
+    pub fn dtps(&self) -> DTPSR {
+        DTPSR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 16:19 - Extended Deadtime Value"]
+    #[inline]
+    pub fn dtvalex(&self) -> DTVALEXR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DTVALEXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:5 - Deadtime Value"]
+    #[inline]
+    pub fn dtval(&mut self) -> _DTVALW {
+        _DTVALW { w: self }
+    }
+    #[doc = "Bits 6:7 - Deadtime Prescaler Value"]
+    #[inline]
+    pub fn dtps(&mut self) -> _DTPSW {
+        _DTPSW { w: self }
+    }
+    #[doc = "Bits 16:19 - Extended Deadtime Value"]
+    #[inline]
+    pub fn dtvalex(&mut self) -> _DTVALEXW {
+        _DTVALEXW { w: self }
+    }
+}

src/ftm1/pair1deadtime/mod.rs

@@ -0,0 +1,264 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PAIR1DEADTIME {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DTVALR {
+    bits: u8,
+}
+impl DTVALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `DTPS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DTPSR {
+    #[doc = "Divide the FTM input clock by 1."]
+    _0X,
+    #[doc = "Divide the FTM input clock by 4."]
+    _10,
+    #[doc = "Divide the FTM input clock by 16."]
+    _11,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl DTPSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            DTPSR::_0X => 0,
+            DTPSR::_10 => 2,
+            DTPSR::_11 => 3,
+            DTPSR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> DTPSR {
+        match value {
+            0 => DTPSR::_0X,
+            2 => DTPSR::_10,
+            3 => DTPSR::_11,
+            i => DTPSR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0X`"]
+    #[inline]
+    pub fn is_0x(&self) -> bool {
+        *self == DTPSR::_0X
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == DTPSR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == DTPSR::_11
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DTVALEXR {
+    bits: u8,
+}
+impl DTVALEXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTVALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTVALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DTPS`"]
+pub enum DTPSW {
+    #[doc = "Divide the FTM input clock by 1."]
+    _0X,
+    #[doc = "Divide the FTM input clock by 4."]
+    _10,
+    #[doc = "Divide the FTM input clock by 16."]
+    _11,
+}
+impl DTPSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            DTPSW::_0X => 0,
+            DTPSW::_10 => 2,
+            DTPSW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTPSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTPSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DTPSW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Divide the FTM input clock by 1."]
+    #[inline]
+    pub fn _0x(self) -> &'a mut W {
+        self.variant(DTPSW::_0X)
+    }
+    #[doc = "Divide the FTM input clock by 4."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(DTPSW::_10)
+    }
+    #[doc = "Divide the FTM input clock by 16."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(DTPSW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTVALEXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTVALEXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:5 - Deadtime Value"]
+    #[inline]
+    pub fn dtval(&self) -> DTVALR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DTVALR { bits }
+    }
+    #[doc = "Bits 6:7 - Deadtime Prescaler Value"]
+    #[inline]
+    pub fn dtps(&self) -> DTPSR {
+        DTPSR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 16:19 - Extended Deadtime Value"]
+    #[inline]
+    pub fn dtvalex(&self) -> DTVALEXR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DTVALEXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:5 - Deadtime Value"]
+    #[inline]
+    pub fn dtval(&mut self) -> _DTVALW {
+        _DTVALW { w: self }
+    }
+    #[doc = "Bits 6:7 - Deadtime Prescaler Value"]
+    #[inline]
+    pub fn dtps(&mut self) -> _DTPSW {
+        _DTPSW { w: self }
+    }
+    #[doc = "Bits 16:19 - Extended Deadtime Value"]
+    #[inline]
+    pub fn dtvalex(&mut self) -> _DTVALEXW {
+        _DTVALEXW { w: self }
+    }
+}

src/ftm1/pair2deadtime/mod.rs

@@ -0,0 +1,264 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PAIR2DEADTIME {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DTVALR {
+    bits: u8,
+}
+impl DTVALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `DTPS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DTPSR {
+    #[doc = "Divide the FTM input clock by 1."]
+    _0X,
+    #[doc = "Divide the FTM input clock by 4."]
+    _10,
+    #[doc = "Divide the FTM input clock by 16."]
+    _11,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl DTPSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            DTPSR::_0X => 0,
+            DTPSR::_10 => 2,
+            DTPSR::_11 => 3,
+            DTPSR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> DTPSR {
+        match value {
+            0 => DTPSR::_0X,
+            2 => DTPSR::_10,
+            3 => DTPSR::_11,
+            i => DTPSR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0X`"]
+    #[inline]
+    pub fn is_0x(&self) -> bool {
+        *self == DTPSR::_0X
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == DTPSR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == DTPSR::_11
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DTVALEXR {
+    bits: u8,
+}
+impl DTVALEXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTVALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTVALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DTPS`"]
+pub enum DTPSW {
+    #[doc = "Divide the FTM input clock by 1."]
+    _0X,
+    #[doc = "Divide the FTM input clock by 4."]
+    _10,
+    #[doc = "Divide the FTM input clock by 16."]
+    _11,
+}
+impl DTPSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            DTPSW::_0X => 0,
+            DTPSW::_10 => 2,
+            DTPSW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTPSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTPSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DTPSW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Divide the FTM input clock by 1."]
+    #[inline]
+    pub fn _0x(self) -> &'a mut W {
+        self.variant(DTPSW::_0X)
+    }
+    #[doc = "Divide the FTM input clock by 4."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(DTPSW::_10)
+    }
+    #[doc = "Divide the FTM input clock by 16."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(DTPSW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTVALEXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTVALEXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:5 - Deadtime Value"]
+    #[inline]
+    pub fn dtval(&self) -> DTVALR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DTVALR { bits }
+    }
+    #[doc = "Bits 6:7 - Deadtime Prescaler Value"]
+    #[inline]
+    pub fn dtps(&self) -> DTPSR {
+        DTPSR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 16:19 - Extended Deadtime Value"]
+    #[inline]
+    pub fn dtvalex(&self) -> DTVALEXR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DTVALEXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:5 - Deadtime Value"]
+    #[inline]
+    pub fn dtval(&mut self) -> _DTVALW {
+        _DTVALW { w: self }
+    }
+    #[doc = "Bits 6:7 - Deadtime Prescaler Value"]
+    #[inline]
+    pub fn dtps(&mut self) -> _DTPSW {
+        _DTPSW { w: self }
+    }
+    #[doc = "Bits 16:19 - Extended Deadtime Value"]
+    #[inline]
+    pub fn dtvalex(&mut self) -> _DTVALEXW {
+        _DTVALEXW { w: self }
+    }
+}

src/ftm1/pair3deadtime/mod.rs

@@ -0,0 +1,264 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::PAIR3DEADTIME {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DTVALR {
+    bits: u8,
+}
+impl DTVALR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = "Possible values of the field `DTPS`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum DTPSR {
+    #[doc = "Divide the FTM input clock by 1."]
+    _0X,
+    #[doc = "Divide the FTM input clock by 4."]
+    _10,
+    #[doc = "Divide the FTM input clock by 16."]
+    _11,
+    #[doc = r" Reserved"]
+    _Reserved(u8),
+}
+impl DTPSR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        match *self {
+            DTPSR::_0X => 0,
+            DTPSR::_10 => 2,
+            DTPSR::_11 => 3,
+            DTPSR::_Reserved(bits) => bits,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: u8) -> DTPSR {
+        match value {
+            0 => DTPSR::_0X,
+            2 => DTPSR::_10,
+            3 => DTPSR::_11,
+            i => DTPSR::_Reserved(i),
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0X`"]
+    #[inline]
+    pub fn is_0x(&self) -> bool {
+        *self == DTPSR::_0X
+    }
+    #[doc = "Checks if the value of the field is `_10`"]
+    #[inline]
+    pub fn is_10(&self) -> bool {
+        *self == DTPSR::_10
+    }
+    #[doc = "Checks if the value of the field is `_11`"]
+    #[inline]
+    pub fn is_11(&self) -> bool {
+        *self == DTPSR::_11
+    }
+}
+#[doc = r" Value of the field"]
+pub struct DTVALEXR {
+    bits: u8,
+}
+impl DTVALEXR {
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u8 {
+        self.bits
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTVALW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTVALW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 63;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `DTPS`"]
+pub enum DTPSW {
+    #[doc = "Divide the FTM input clock by 1."]
+    _0X,
+    #[doc = "Divide the FTM input clock by 4."]
+    _10,
+    #[doc = "Divide the FTM input clock by 16."]
+    _11,
+}
+impl DTPSW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> u8 {
+        match *self {
+            DTPSW::_0X => 0,
+            DTPSW::_10 => 2,
+            DTPSW::_11 => 3,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTPSW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTPSW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: DTPSW) -> &'a mut W {
+        unsafe { self.bits(variant._bits()) }
+    }
+    #[doc = "Divide the FTM input clock by 1."]
+    #[inline]
+    pub fn _0x(self) -> &'a mut W {
+        self.variant(DTPSW::_0X)
+    }
+    #[doc = "Divide the FTM input clock by 4."]
+    #[inline]
+    pub fn _10(self) -> &'a mut W {
+        self.variant(DTPSW::_10)
+    }
+    #[doc = "Divide the FTM input clock by 16."]
+    #[inline]
+    pub fn _11(self) -> &'a mut W {
+        self.variant(DTPSW::_11)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 3;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = r" Proxy"]
+pub struct _DTVALEXW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _DTVALEXW<'a> {
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub unsafe fn bits(self, value: u8) -> &'a mut W {
+        const MASK: u8 = 15;
+        const OFFSET: u8 = 16;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bits 0:5 - Deadtime Value"]
+    #[inline]
+    pub fn dtval(&self) -> DTVALR {
+        let bits = {
+            const MASK: u8 = 63;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DTVALR { bits }
+    }
+    #[doc = "Bits 6:7 - Deadtime Prescaler Value"]
+    #[inline]
+    pub fn dtps(&self) -> DTPSR {
+        DTPSR::_from({
+            const MASK: u8 = 3;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        })
+    }
+    #[doc = "Bits 16:19 - Extended Deadtime Value"]
+    #[inline]
+    pub fn dtvalex(&self) -> DTVALEXR {
+        let bits = {
+            const MASK: u8 = 15;
+            const OFFSET: u8 = 16;
+            ((self.bits >> OFFSET) & MASK as u32) as u8
+        };
+        DTVALEXR { bits }
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bits 0:5 - Deadtime Value"]
+    #[inline]
+    pub fn dtval(&mut self) -> _DTVALW {
+        _DTVALW { w: self }
+    }
+    #[doc = "Bits 6:7 - Deadtime Prescaler Value"]
+    #[inline]
+    pub fn dtps(&mut self) -> _DTPSW {
+        _DTPSW { w: self }
+    }
+    #[doc = "Bits 16:19 - Extended Deadtime Value"]
+    #[inline]
+    pub fn dtvalex(&mut self) -> _DTVALEXW {
+        _DTVALEXW { w: self }
+    }
+}

src/ftm1/qdctrl/mod.rs

@@ -0,0 +1,888 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+#[doc = r" Value to write to the register"]
+pub struct W {
+    bits: u32,
+}
+impl super::QDCTRL {
+    #[doc = r" Modifies the contents of the register"]
+    #[inline]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
+    {
+        let bits = self.register.get();
+        let r = R { bits: bits };
+        let mut w = W { bits: bits };
+        f(&r, &mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+    #[doc = r" Writes to the register"]
+    #[inline]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W) -> &mut W,
+    {
+        let mut w = W::reset_value();
+        f(&mut w);
+        self.register.set(w.bits);
+    }
+    #[doc = r" Writes the reset value to the register"]
+    #[inline]
+    pub fn reset(&self) {
+        self.write(|w| w)
+    }
+}
+#[doc = "Possible values of the field `QUADEN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum QUADENR {
+    #[doc = "Quadrature Decoder mode is disabled."]
+    _0,
+    #[doc = "Quadrature Decoder mode is enabled."]
+    _1,
+}
+impl QUADENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            QUADENR::_0 => false,
+            QUADENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> QUADENR {
+        match value {
+            false => QUADENR::_0,
+            true => QUADENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == QUADENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == QUADENR::_1
+    }
+}
+#[doc = "Possible values of the field `TOFDIR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum TOFDIRR {
+    #[doc = "TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register)."]
+    _0,
+    #[doc = "TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register)."]
+    _1,
+}
+impl TOFDIRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            TOFDIRR::_0 => false,
+            TOFDIRR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> TOFDIRR {
+        match value {
+            false => TOFDIRR::_0,
+            true => TOFDIRR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == TOFDIRR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == TOFDIRR::_1
+    }
+}
+#[doc = "Possible values of the field `QUADIR`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum QUADIRR {
+    #[doc = "Counting direction is decreasing (FTM counter decrement)."]
+    _0,
+    #[doc = "Counting direction is increasing (FTM counter increment)."]
+    _1,
+}
+impl QUADIRR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            QUADIRR::_0 => false,
+            QUADIRR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> QUADIRR {
+        match value {
+            false => QUADIRR::_0,
+            true => QUADIRR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == QUADIRR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == QUADIRR::_1
+    }
+}
+#[doc = "Possible values of the field `QUADMODE`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum QUADMODER {
+    #[doc = "Phase A and phase B encoding mode."]
+    _0,
+    #[doc = "Count and direction encoding mode."]
+    _1,
+}
+impl QUADMODER {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            QUADMODER::_0 => false,
+            QUADMODER::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> QUADMODER {
+        match value {
+            false => QUADMODER::_0,
+            true => QUADMODER::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == QUADMODER::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == QUADMODER::_1
+    }
+}
+#[doc = "Possible values of the field `PHBPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PHBPOLR {
+    #[doc = "Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal."]
+    _0,
+    #[doc = "Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal."]
+    _1,
+}
+impl PHBPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PHBPOLR::_0 => false,
+            PHBPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PHBPOLR {
+        match value {
+            false => PHBPOLR::_0,
+            true => PHBPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PHBPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PHBPOLR::_1
+    }
+}
+#[doc = "Possible values of the field `PHAPOL`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PHAPOLR {
+    #[doc = "Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal."]
+    _0,
+    #[doc = "Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal."]
+    _1,
+}
+impl PHAPOLR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PHAPOLR::_0 => false,
+            PHAPOLR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PHAPOLR {
+        match value {
+            false => PHAPOLR::_0,
+            true => PHAPOLR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PHAPOLR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PHAPOLR::_1
+    }
+}
+#[doc = "Possible values of the field `PHBFLTREN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PHBFLTRENR {
+    #[doc = "Phase B input filter is disabled."]
+    _0,
+    #[doc = "Phase B input filter is enabled."]
+    _1,
+}
+impl PHBFLTRENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PHBFLTRENR::_0 => false,
+            PHBFLTRENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PHBFLTRENR {
+        match value {
+            false => PHBFLTRENR::_0,
+            true => PHBFLTRENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PHBFLTRENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PHBFLTRENR::_1
+    }
+}
+#[doc = "Possible values of the field `PHAFLTREN`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum PHAFLTRENR {
+    #[doc = "Phase A input filter is disabled."]
+    _0,
+    #[doc = "Phase A input filter is enabled."]
+    _1,
+}
+impl PHAFLTRENR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            PHAFLTRENR::_0 => false,
+            PHAFLTRENR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> PHAFLTRENR {
+        match value {
+            false => PHAFLTRENR::_0,
+            true => PHAFLTRENR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == PHAFLTRENR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == PHAFLTRENR::_1
+    }
+}
+#[doc = "Values that can be written to the field `QUADEN`"]
+pub enum QUADENW {
+    #[doc = "Quadrature Decoder mode is disabled."]
+    _0,
+    #[doc = "Quadrature Decoder mode is enabled."]
+    _1,
+}
+impl QUADENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            QUADENW::_0 => false,
+            QUADENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _QUADENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _QUADENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: QUADENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Quadrature Decoder mode is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(QUADENW::_0)
+    }
+    #[doc = "Quadrature Decoder mode is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(QUADENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 0;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `QUADMODE`"]
+pub enum QUADMODEW {
+    #[doc = "Phase A and phase B encoding mode."]
+    _0,
+    #[doc = "Count and direction encoding mode."]
+    _1,
+}
+impl QUADMODEW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            QUADMODEW::_0 => false,
+            QUADMODEW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _QUADMODEW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _QUADMODEW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: QUADMODEW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Phase A and phase B encoding mode."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(QUADMODEW::_0)
+    }
+    #[doc = "Count and direction encoding mode."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(QUADMODEW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 3;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PHBPOL`"]
+pub enum PHBPOLW {
+    #[doc = "Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal."]
+    _0,
+    #[doc = "Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal."]
+    _1,
+}
+impl PHBPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PHBPOLW::_0 => false,
+            PHBPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PHBPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PHBPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PHBPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PHBPOLW::_0)
+    }
+    #[doc = "Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PHBPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 4;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PHAPOL`"]
+pub enum PHAPOLW {
+    #[doc = "Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal."]
+    _0,
+    #[doc = "Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal."]
+    _1,
+}
+impl PHAPOLW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PHAPOLW::_0 => false,
+            PHAPOLW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PHAPOLW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PHAPOLW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PHAPOLW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PHAPOLW::_0)
+    }
+    #[doc = "Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PHAPOLW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 5;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PHBFLTREN`"]
+pub enum PHBFLTRENW {
+    #[doc = "Phase B input filter is disabled."]
+    _0,
+    #[doc = "Phase B input filter is enabled."]
+    _1,
+}
+impl PHBFLTRENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PHBFLTRENW::_0 => false,
+            PHBFLTRENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PHBFLTRENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PHBFLTRENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PHBFLTRENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Phase B input filter is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PHBFLTRENW::_0)
+    }
+    #[doc = "Phase B input filter is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PHBFLTRENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 6;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+#[doc = "Values that can be written to the field `PHAFLTREN`"]
+pub enum PHAFLTRENW {
+    #[doc = "Phase A input filter is disabled."]
+    _0,
+    #[doc = "Phase A input filter is enabled."]
+    _1,
+}
+impl PHAFLTRENW {
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _bits(&self) -> bool {
+        match *self {
+            PHAFLTRENW::_0 => false,
+            PHAFLTRENW::_1 => true,
+        }
+    }
+}
+#[doc = r" Proxy"]
+pub struct _PHAFLTRENW<'a> {
+    w: &'a mut W,
+}
+impl<'a> _PHAFLTRENW<'a> {
+    #[doc = r" Writes `variant` to the field"]
+    #[inline]
+    pub fn variant(self, variant: PHAFLTRENW) -> &'a mut W {
+        {
+            self.bit(variant._bits())
+        }
+    }
+    #[doc = "Phase A input filter is disabled."]
+    #[inline]
+    pub fn _0(self) -> &'a mut W {
+        self.variant(PHAFLTRENW::_0)
+    }
+    #[doc = "Phase A input filter is enabled."]
+    #[inline]
+    pub fn _1(self) -> &'a mut W {
+        self.variant(PHAFLTRENW::_1)
+    }
+    #[doc = r" Sets the field bit"]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r" Clears the field bit"]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r" Writes raw bits to the field"]
+    #[inline]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        const MASK: bool = true;
+        const OFFSET: u8 = 7;
+        self.w.bits &= !((MASK as u32) << OFFSET);
+        self.w.bits |= ((value & MASK) as u32) << OFFSET;
+        self.w
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Quadrature Decoder Mode Enable"]
+    #[inline]
+    pub fn quaden(&self) -> QUADENR {
+        QUADENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Timer Overflow Direction In Quadrature Decoder Mode"]
+    #[inline]
+    pub fn tofdir(&self) -> TOFDIRR {
+        TOFDIRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - FTM Counter Direction In Quadrature Decoder Mode"]
+    #[inline]
+    pub fn quadir(&self) -> QUADIRR {
+        QUADIRR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Quadrature Decoder Mode"]
+    #[inline]
+    pub fn quadmode(&self) -> QUADMODER {
+        QUADMODER::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - Phase B Input Polarity"]
+    #[inline]
+    pub fn phbpol(&self) -> PHBPOLR {
+        PHBPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - Phase A Input Polarity"]
+    #[inline]
+    pub fn phapol(&self) -> PHAPOLR {
+        PHAPOLR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - Phase B Input Filter Enable"]
+    #[inline]
+    pub fn phbfltren(&self) -> PHBFLTRENR {
+        PHBFLTRENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Phase A Input Filter Enable"]
+    #[inline]
+    pub fn phafltren(&self) -> PHAFLTRENR {
+        PHAFLTRENR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}
+impl W {
+    #[doc = r" Reset value of the register"]
+    #[inline]
+    pub fn reset_value() -> W {
+        W { bits: 0 }
+    }
+    #[doc = r" Writes raw bits to the register"]
+    #[inline]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+    #[doc = "Bit 0 - Quadrature Decoder Mode Enable"]
+    #[inline]
+    pub fn quaden(&mut self) -> _QUADENW {
+        _QUADENW { w: self }
+    }
+    #[doc = "Bit 3 - Quadrature Decoder Mode"]
+    #[inline]
+    pub fn quadmode(&mut self) -> _QUADMODEW {
+        _QUADMODEW { w: self }
+    }
+    #[doc = "Bit 4 - Phase B Input Polarity"]
+    #[inline]
+    pub fn phbpol(&mut self) -> _PHBPOLW {
+        _PHBPOLW { w: self }
+    }
+    #[doc = "Bit 5 - Phase A Input Polarity"]
+    #[inline]
+    pub fn phapol(&mut self) -> _PHAPOLW {
+        _PHAPOLW { w: self }
+    }
+    #[doc = "Bit 6 - Phase B Input Filter Enable"]
+    #[inline]
+    pub fn phbfltren(&mut self) -> _PHBFLTRENW {
+        _PHBFLTRENW { w: self }
+    }
+    #[doc = "Bit 7 - Phase A Input Filter Enable"]
+    #[inline]
+    pub fn phafltren(&mut self) -> _PHAFLTRENW {
+        _PHAFLTRENW { w: self }
+    }
+}

src/ftm1/status/mod.rs

@@ -0,0 +1,466 @@
+#[doc = r" Value read from the register"]
+pub struct R {
+    bits: u32,
+}
+impl super::STATUS {
+    #[doc = r" Reads the contents of the register"]
+    #[inline]
+    pub fn read(&self) -> R {
+        R { bits: self.register.get() }
+    }
+}
+#[doc = "Possible values of the field `CH0F`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CH0FR {
+    #[doc = "No channel event has occurred."]
+    _0,
+    #[doc = "A channel event has occurred."]
+    _1,
+}
+impl CH0FR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CH0FR::_0 => false,
+            CH0FR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CH0FR {
+        match value {
+            false => CH0FR::_0,
+            true => CH0FR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CH0FR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CH0FR::_1
+    }
+}
+#[doc = "Possible values of the field `CH1F`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CH1FR {
+    #[doc = "No channel event has occurred."]
+    _0,
+    #[doc = "A channel event has occurred."]
+    _1,
+}
+impl CH1FR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CH1FR::_0 => false,
+            CH1FR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CH1FR {
+        match value {
+            false => CH1FR::_0,
+            true => CH1FR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CH1FR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CH1FR::_1
+    }
+}
+#[doc = "Possible values of the field `CH2F`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CH2FR {
+    #[doc = "No channel event has occurred."]
+    _0,
+    #[doc = "A channel event has occurred."]
+    _1,
+}
+impl CH2FR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CH2FR::_0 => false,
+            CH2FR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CH2FR {
+        match value {
+            false => CH2FR::_0,
+            true => CH2FR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CH2FR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CH2FR::_1
+    }
+}
+#[doc = "Possible values of the field `CH3F`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CH3FR {
+    #[doc = "No channel event has occurred."]
+    _0,
+    #[doc = "A channel event has occurred."]
+    _1,
+}
+impl CH3FR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CH3FR::_0 => false,
+            CH3FR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CH3FR {
+        match value {
+            false => CH3FR::_0,
+            true => CH3FR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CH3FR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CH3FR::_1
+    }
+}
+#[doc = "Possible values of the field `CH4F`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CH4FR {
+    #[doc = "No channel event has occurred."]
+    _0,
+    #[doc = "A channel event has occurred."]
+    _1,
+}
+impl CH4FR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CH4FR::_0 => false,
+            CH4FR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CH4FR {
+        match value {
+            false => CH4FR::_0,
+            true => CH4FR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CH4FR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CH4FR::_1
+    }
+}
+#[doc = "Possible values of the field `CH5F`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CH5FR {
+    #[doc = "No channel event has occurred."]
+    _0,
+    #[doc = "A channel event has occurred."]
+    _1,
+}
+impl CH5FR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CH5FR::_0 => false,
+            CH5FR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CH5FR {
+        match value {
+            false => CH5FR::_0,
+            true => CH5FR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CH5FR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CH5FR::_1
+    }
+}
+#[doc = "Possible values of the field `CH6F`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CH6FR {
+    #[doc = "No channel event has occurred."]
+    _0,
+    #[doc = "A channel event has occurred."]
+    _1,
+}
+impl CH6FR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CH6FR::_0 => false,
+            CH6FR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CH6FR {
+        match value {
+            false => CH6FR::_0,
+            true => CH6FR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CH6FR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CH6FR::_1
+    }
+}
+#[doc = "Possible values of the field `CH7F`"]
+#[derive(Clone, Copy, Debug, PartialEq)]
+pub enum CH7FR {
+    #[doc = "No channel event has occurred."]
+    _0,
+    #[doc = "A channel event has occurred."]
+    _1,
+}
+impl CH7FR {
+    #[doc = r" Returns `true` if the bit is clear (0)"]
+    #[inline]
+    pub fn bit_is_clear(&self) -> bool {
+        !self.bit()
+    }
+    #[doc = r" Returns `true` if the bit is set (1)"]
+    #[inline]
+    pub fn bit_is_set(&self) -> bool {
+        self.bit()
+    }
+    #[doc = r" Value of the field as raw bits"]
+    #[inline]
+    pub fn bit(&self) -> bool {
+        match *self {
+            CH7FR::_0 => false,
+            CH7FR::_1 => true,
+        }
+    }
+    #[allow(missing_docs)]
+    #[doc(hidden)]
+    #[inline]
+    pub fn _from(value: bool) -> CH7FR {
+        match value {
+            false => CH7FR::_0,
+            true => CH7FR::_1,
+        }
+    }
+    #[doc = "Checks if the value of the field is `_0`"]
+    #[inline]
+    pub fn is_0(&self) -> bool {
+        *self == CH7FR::_0
+    }
+    #[doc = "Checks if the value of the field is `_1`"]
+    #[inline]
+    pub fn is_1(&self) -> bool {
+        *self == CH7FR::_1
+    }
+}
+impl R {
+    #[doc = r" Value of the register as raw bits"]
+    #[inline]
+    pub fn bits(&self) -> u32 {
+        self.bits
+    }
+    #[doc = "Bit 0 - Channel 0 Flag"]
+    #[inline]
+    pub fn ch0f(&self) -> CH0FR {
+        CH0FR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 0;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 1 - Channel 1 Flag"]
+    #[inline]
+    pub fn ch1f(&self) -> CH1FR {
+        CH1FR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 1;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 2 - Channel 2 Flag"]
+    #[inline]
+    pub fn ch2f(&self) -> CH2FR {
+        CH2FR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 2;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 3 - Channel 3 Flag"]
+    #[inline]
+    pub fn ch3f(&self) -> CH3FR {
+        CH3FR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 3;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 4 - Channel 4 Flag"]
+    #[inline]
+    pub fn ch4f(&self) -> CH4FR {
+        CH4FR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 4;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 5 - Channel 5 Flag"]
+    #[inline]
+    pub fn ch5f(&self) -> CH5FR {
+        CH5FR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 5;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 6 - Channel 6 Flag"]
+    #[inline]
+    pub fn ch6f(&self) -> CH6FR {
+        CH6FR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 6;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+    #[doc = "Bit 7 - Channel 7 Flag"]
+    #[inline]
+    pub fn ch7f(&self) -> CH7FR {
+        CH7FR::_from({
+            const MASK: bool = true;
+            const OFFSET: u8 = 7;
+            ((self.bits >> OFFSET) & MASK as u32) != 0
+        })
+    }
+}